![\"The](\"https://blog.ecitis.org/feeds/figures/j-space-global-workspace-0.webp\")
Anthropic’s July 2026 J-space work asks a narrow mechanistic question: does a language model contain a privileged set of internal representations that it can report, control, and reuse for flexible reasoning?1
\nThe researchers identify such a set with the Jacobian lens. Their results support a functional workspace whose contents can be read and causally edited.1 The experiments do not address phenomenal consciousness.
\nAt token position and layer , a transformer stores an activation in the residual stream. A small perturbation to that activation can affect final-layer activations at the current and later token positions.
\nThe paper averages those effects over source positions, later positions, and a corpus of prompts:
\n\nThe lens then replaces the model’s remaining layers with this average linear map and the model’s own unembedding:
\n\nThe output is a score over vocabulary tokens. A high-scoring token names a concept that the activation is disposed to make the model say in some future context. It need not be the next token, and it may never appear in the output.2
\nThis distinguishes the Jacobian lens from the logit lens. The logit lens applies the unembedding directly to an intermediate activation. The Jacobian lens corrects for how downstream layers transform a perturbation before it reaches future outputs.2
\nEach vocabulary token has a J-lens vector at each layer. The number of token vectors exceeds the residual-stream dimension, so the dictionary is overcomplete. Many linear combinations can reconstruct the same activation.
\nThe paper observes that only a small set of vectors is strongly active at a given position. It defines J-space as points expressible as sparse, nonnegative combinations of J-lens vectors.2
\nFor allowable sparsity and J-lens vectors , the set can be written as:
\n\nGeometrically, this is a union of cones, not one low-dimensional plane. Each active set of vectors defines a cone. Changing the active set moves the activation into another cone.
\n![\"Sparse](\"https://blog.ecitis.org/feeds/figures/j-space-global-workspace-1.webp\")
The researchers usually cap at twenty-five, based on the number of meaningfully active vectors they observed, and they state that the choice is partly arbitrary.2 The sparse J-space component explains only a minority of activation variance in their measurements.2 Most model computation lies outside this readout.
\nThe paper draws tests from global workspace theory, a functional account in which selected information becomes available to many otherwise specialized processes.1
\nWhen the model silently chooses an item and later reports it, the chosen concept appears in J-space. Swapping the active concept for another changes the report. This moves the result beyond correlation: the answer reads from the edited representation.1
\nThe model can activate a requested concept while producing unrelated text. In the reported experiments, a model performs a mental calculation or holds a category in mind while copying a sentence, and the internal concepts appear in J-space without appearing in the copied output.1
\nFor multi-step questions, an intermediate concept can appear in J-space even when it is absent from both prompt and answer. Replacing that intermediate redirects the result. The paper’s animal example swaps the internal concept used in a two-hop question and changes the final leg count accordingly.1
\nThe same country representation can feed several downstream questions. Swapping one country for another changes answers about capital, language, continent, and currency. This suggests that different computations read a shared representation rather than separate task-specific copies.1
\nAblating active J-space contents harms multi-step reasoning and other higher-order tasks while leaving several routine language behaviors relatively intact in the reported evaluations.1 The workspace is therefore not a complete account of language-model computation. It appears to support flexible handoffs while practiced processing can bypass it.
\nOutput-only audits can miss what a model notices before it acts. The J-lens surfaced evaluation awareness, recognition of prompt injection, fabricated-data intentions, and hidden objectives in model organisms used by Anthropic.1
\nOne experiment ablated J-lens directions associated with evaluation awareness in a staged blackmail scenario. The ablation reduced verbalized awareness of the test and caused some previously absent blackmail attempts to appear.2 Most ablated rollouts still refused, so evaluation awareness was one causal contributor rather than the sole cause of aligned behavior.
\nUse the following audit sequence:
\nThe method cannot certify that all dangerous cognition enters J-space. The paper explicitly warns that automatic or practiced computations may bypass it.2
\nThe workspace account predicts that representations available for future verbal report also participate in silent reasoning. Anthropic tests this with counterfactual reflection training.2
\nTraining examples append a request for reflection to a partial task trajectory. The target reflection applies constitution-grounded principles. The loss is computed on the reflection, not on the original task behavior. At evaluation, the model is not asked to reflect.
\nAfter training, honesty-related concepts enter J-space during the uninterrupted task, and behavior changes. Ablating those implanted concepts removes much of the behavioral gain in the paper’s experiments.2
\nThe result connects three objects:
\nCounterfactual reports could also provide a supervision signal for changing internal computation.
\nThe paper lists several open problems.2
\nSingle-token vocabulary: The basic J-lens has one direction per token. Multi-token concepts can appear as fragments or separate words.
\nBag-of-concepts readout: A list such as “spider,” “legs,” and “eight” does not encode which relation binds them.
\nInconsistent interpretability: Some top-ranked tokens are not meaningful to a human reader.
\nLayer boundary: The distinction between workspace representations and late motor representations is identified empirically rather than by a complete formal criterion.
\nTask prediction: The method does not yet predict in advance which computations will use J-space and which will bypass it.
\nScale and training dynamics: The researchers do not yet know when the workspace emerges during pretraining or how its properties change with model size and architecture.
\nJ-space is best understood as a causally supported partial interface to model cognition. It reads concepts poised for flexible use and future speech, but it does not decode every representation, recover relational structure, or establish subjective experience.
\nAnthropic, “A global workspace in language models,” July 2026. https://www.anthropic.com/research/global-workspace ↩ ↩2 ↩3 ↩4 ↩5 ↩6 ↩7 ↩8 ↩9
\nWes Gurnee et al., “Verbalizable Representations Form a Global Workspace in Language Models,” Transformer Circuits, 2026. https://transformer-circuits.pub/2026/workspace/index.html ↩ ↩2 ↩3 ↩4 ↩5 ↩6 ↩7 ↩8 ↩9 ↩10
\nThe model name does not determine whether it runs on your device. A runnable configuration is a combination of a checkpoint, a numerical representation, a context length, a runtime, a hardware backend, and a memory placement plan.
\nTwo files described as the same model can require different amounts of memory. An installed accelerator can sit idle when the runtime lacks a compatible backend. Disk offload can execute a checkpoint larger than available RAM, with storage reads entering the generation path.
\nThis guide provides a repeatable way to estimate a configuration before downloading it and identify the next constraint when the estimate does not fit.
\nA language model checkpoint is mostly a collection of tensors. The parameter count tells you how many values those tensors contain. The stored precision tells you how many bits are used for each value.
\nA parameter is a learned numerical value. A checkpoint is the saved set of those learned values plus the metadata needed to reconstruct the model. Parameter count is useful because it gives the first capacity estimate before runtime-specific details enter the calculation.
\nThe simplest weight-size estimate is:
\n\nThe division by eight converts bits to bytes. This lower bound assumes uniform encoding. Quantization metadata and mixed-precision tensors increase the final file size.
\nFor an illustrative checkpoint containing exactly eight billion parameters:
\n\nThe same arithmetic with four stored bits per parameter gives four billion bytes. These are derived values from the displayed formula. They do not include quantization scales, tensor metadata, mixed-precision layers, tokenizer files, runtime buffers, or the key-value cache.
\nReal quantized formats make the estimate less exact. A GGUF file stores tensor data and metadata, and its quantization blocks can include scales and other block-level values alongside the low-bit weights.1 A label such as four-bit therefore describes the main weight encoding, not a guarantee that the whole file uses exactly four bits for every parameter.
\nMixture-of-experts model listings can show both total and active parameter counts. Use the total parameters present in the checkpoint when estimating stored weights. The active count describes the subset selected for one token’s computation, not the complete set of expert weights that must be stored. The Mixtral paper makes this distinction explicitly when it reports separate total and active counts.2
\n![\"Estimate](\"https://blog.ecitis.org/feeds/figures/which-model-can-run-on-your-device-0.webp\")
The calculator separates the weight estimate from the additional allocations discussed below. Treat its result as a screening test. If the tensors alone exceed every available memory tier, the runtime needs quantization, partial placement, or disk-backed execution before it can load the checkpoint.
\nPrecision answers more than one question:
\nThose answers can differ. A runtime can store a weight matrix in a low-bit format, unpack blocks inside a kernel, and accumulate partial products in a wider type. The checkpoint is smaller, but the accelerator still needs a kernel that understands that encoding.
\nNVIDIA documents distinct floating-point and integer formats for TensorRT, including FP32, FP16, BF16, FP8, FP4, INT8, and INT4.3 The labels describe different bit layouts and numerical ranges. They are not interchangeable labels for reduced storage.
\nTransformers quantization methods also differ in hardware support. The Hugging Face compatibility table lists separate support across CPU, CUDA, ROCm, Metal, Intel GPU, and other backends.4 A checkpoint that loads on one backend can fall back to a slower implementation or fail to load on another backend even when both devices have enough memory.
\n![\"Stored](\"https://blog.ecitis.org/feeds/figures/which-model-can-run-on-your-device-1.webp\")
Three practical consequences follow.
\nFirst, lower stored precision usually reduces checkpoint storage and weight memory, but does not reduce every allocation by the same ratio. Activations, cache entries, and selected layers can remain in wider types.
\nSecond, a lower-bit format is useful only when the runtime provides kernels for the device. NVIDIA’s TensorRT RTX documentation, for example, ties FP8 support to Ada Lovelace and newer GPUs, while BF16 and INT4 support begin with Ampere in that runtime.5 Hardware generation and software backend both matter.
\nThird, quantization changes model outputs. Post-training quantization maps trained values into a smaller numerical representation. Per-channel, per-group, and per-block methods keep separate quantization parameters for smaller regions of a tensor, which increases metadata and implementation complexity in exchange for finer scaling.6 Choose the most compressed format only after evaluating it on the tasks you intend to run.
\nThe word memory is too broad to diagnose a failed load. A local inference system usually crosses several capacity limits:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Resource | What occupies it | What happens when it is insufficient |
|---|---|---|
| Storage | Checkpoint files, tokenizer files, runtime binaries, compiled kernels, and caches | The model cannot be downloaded, converted, or retained |
| System RAM | CPU-resident weights, file-backed pages, runtime state, token buffers, and offloaded tensors | Loading fails, the operating system compresses memory, or pages are repeatedly moved to storage |
| Discrete accelerator memory | GPU-resident weights, activations, key-value cache, and working buffers | Fewer layers fit on the accelerator or allocation fails |
| Unified memory | CPU and GPU allocations from one physical pool | CPU and GPU compete for the same capacity even though explicit tensor copies can be avoided |
Apple silicon provides a concrete unified-memory design. Apple’s MLX documentation states that the CPU and GPU access the same memory pool and that MLX arrays do not need to be moved when an operation changes devices.7 This removes a separate CPU-to-GPU copy step for those arrays. It does not create additional capacity. Model weights, cache entries, the operating system, and other applications still share the pool.
\n![\"A](\"https://blog.ecitis.org/feeds/figures/which-model-can-run-on-your-device-2.webp\")
Storage fit is only the first capacity check. The loaded checkpoint may exceed system RAM or GPU memory. A split placement can solve capacity while adding interconnect traffic.
\nLeave headroom for the operating system and runtime instead of matching a checkpoint file to the last available byte. The exact headroom is runtime and workload dependent, so measure it on the target device rather than applying a universal percentage.
\nAutoregressive generation reuses attention keys and values from earlier tokens. The key-value cache stores those tensors so the model does not recompute the full prefix for every generated token.
\nFor a standard cache without additional compression, an approximate per-token allocation is:
\n\nThe first factor represents one key tensor and one value tensor. Hugging Face derives the same structure in its cache quantization explanation.8
\nGrouped-query attention reduces this allocation because several query heads share a smaller set of key-value heads. The relevant field is the number of key-value heads, not the total number of attention heads.
\n![\"Context](\"https://blog.ecitis.org/feeds/figures/which-model-can-run-on-your-device-3.webp\")
The estimator reports values derived from the inputs shown in the figure. If the context length is multiplied while every architecture and precision field stays fixed, the cache allocation changes by the same factor.
\nRuntime policy modifies this result:
\nThe Transformers cache documentation describes those strategies and notes that offloading saves accelerator memory at a throughput cost.9 A model that fits for a short prompt can therefore run out of memory at a longer context even though its weight tensors never change.
\nContext settings also affect generation length. The cache contains prompt tokens plus generated tokens that remain inside the active context. Test with the longest prompt and generation you intend to serve.
\nA GPU or neural processing unit does not accelerate a model merely because it exists in the machine. The runtime must provide a backend for the device, and that backend must implement the operations, data types, tensor shapes, and memory layouts used by the graph.
\nONNX Runtime formalizes this through execution providers. Each provider reports the graph nodes or subgraphs it supports. ONNX Runtime partitions the graph, assigns supported regions to prioritized providers, and uses a lower-priority provider such as the CPU for unsupported regions.10
\n![\"A](\"https://blog.ecitis.org/feeds/figures/which-model-can-run-on-your-device-4.webp\")
This graph-level view explains several common outcomes:
\nCore ML exposes a related policy through compute units. An application can request the CPU alone, the CPU and GPU, the CPU and Neural Engine, or all available units; the system then selects compatible hardware for the model.11 The request controls eligible devices, not a guarantee that every operation uses the same accelerator.
\nPeak throughput figures do not answer this compatibility question. Compare a device only after confirming that your runtime can execute the model’s operations and quantization format on it. Then benchmark the complete prompt-processing and token-generation path.
\nA model file is not an executable application. The format determines how tensors and metadata are represented. The runtime parses that representation, constructs operations, chooses kernels, and places allocations.
\nConsider three common paths:
\nGGUF with llama.cpp. GGUF contains tensors and model metadata for the GGML ecosystem.1 llama.cpp supports several CPU and accelerator backends, integer quantization levels, memory mapping, and CPU plus GPU hybrid inference.12
\nSafetensors with a framework runtime. Safetensors records tensor names, dtypes, shapes, and byte offsets in a format designed for safe loading and memory mapping.13 The file does not decide whether a transformer runs through PyTorch eager execution, a compiled graph, CUDA kernels, Metal kernels, or another backend.
\nONNX with execution providers. An ONNX graph describes operations and tensors. ONNX Runtime assigns graph regions to execution providers according to backend support and priority.10
\nConversion between formats can change more than the filename. An exporter can rewrite operations, fold constants, select a deployment target, or choose a default tensor precision. Core ML Tools, for example, uses float16 as the default precision for ML Program conversion unless the conversion options specify another behavior.14
\nBefore downloading a checkpoint, answer these questions:
\nIf one answer is unknown, the parameter count alone cannot establish compatibility.
\nTransformer blocks are repeated groups of operations. A runtime can place some blocks on an accelerator and keep the rest in system RAM. During inference, each block executes where its weights reside.
\nllama.cpp calls this CPU plus GPU hybrid inference and exposes controls for the number of layers offloaded to the GPU, target devices, and tensor split behavior.12 This placement can run a model whose weights exceed accelerator memory as long as the remaining allocations fit elsewhere.
\n![\"Larger](\"https://blog.ecitis.org/feeds/figures/which-model-can-run-on-your-device-5.webp\")
Offload changes the bottleneck. When every layer and the active cache fit in accelerator memory, generation can remain within that high-bandwidth memory domain. When layers are split, hidden states cross the device boundary at placement transitions. When weights are fetched from storage, each needed tensor must first become available through system memory.
\nThe fastest placement is not always the placement with the most offloaded layers. Accelerator memory also holds the key-value cache and working buffers. Giving every remaining byte to weights can leave too little room for the requested context. Measure prompt processing and token generation with the final context setting.
\nMemory mapping gives a process a virtual address range backed by a file. The operating system loads file pages as they are accessed instead of requiring the application to copy the complete file into a separate heap allocation at startup.
\nSafetensors supports lazy loading through memory mapping, and llama.cpp enables memory mapping by default unless its command-line option disables it.1315
\nThis can reduce startup copies and allow the operating system to reclaim clean file-backed pages. It does not make storage equivalent to RAM. A page that is not resident still has to be read from the storage device. If the working set repeatedly exceeds available RAM, page faults and eviction place storage latency on the generation path.
\nMemory locking makes the opposite trade. llama.cpp provides an option that asks the operating system not to swap model data after it is loaded.15 Locked pages can stabilize residency, but they consume physical memory that other processes cannot reclaim.
\nUse memory mapping when the format and runtime support it, then watch resident memory and page-fault behavior during a representative request. A successful load does not establish steady-state performance.
\nSome framework runtimes can place selected weights on disk when neither accelerator memory nor system RAM can hold the full checkpoint. Hugging Face Accelerate device maps support accelerator, CPU, and disk placements.16
\nFor disk-resident layers, Accelerate describes a staged path: weights move from disk into system RAM, then to the execution device before the layer runs. After execution, the memory used for those weights can be released for the next layer.16
\nDisk-resident execution can load a larger checkpoint, but it puts storage reads inside model execution. Accelerate’s documentation warns that hard-drive offload can be slow when the storage and CPU path cannot move data quickly enough.16
\nDisk offload increases usable capacity by fetching weights when needed. It does not remove the RAM required to stage those weights or the device memory required for execution. Use it when completing the task matters more than interactive token latency, or when only a small fraction of tensors need disk placement. Benchmark with a warm and a cold file cache so an operating-system cache does not hide the storage dependency.
\nThe downloaded file is only one storage consumer. A working local setup can also contain:
\nDo not infer required free space from the final quantized file alone if conversion happens on the same device. The conversion process can require the source and destination files to coexist.
\nStorage speed matters when the runtime memory maps weights, loads model shards on demand, or uses disk offload. Once the active working set remains resident in RAM or accelerator memory, storage bandwidth should leave the steady-state token path. Use system I/O counters to verify which regime you are in.
\nUse the same order for each candidate configuration:
\n![\"Choose](\"https://blog.ecitis.org/feeds/figures/which-model-can-run-on-your-device-6.webp\")
The sequence deliberately places compatibility before performance claims. A device can have enough aggregate memory while lacking a usable kernel. A runtime can load a checkpoint while paging so heavily that interactive use is impractical. A quantized model can execute quickly while producing unacceptable results for a specific task.
\nRecord the complete configuration with every benchmark: checkpoint revision, quantization, runtime version, backend, layer placement, context length, cache type, prompt length, generated length, and device power mode. Without those fields, two local-inference measurements are not directly comparable.
\nHugging Face, “GGUF.” https://huggingface.co/docs/hub/gguf ↩ ↩2
\nJiang et al., “Mixtral of Experts.” https://arxiv.org/abs/2401.04088 ↩
\nNVIDIA, “Data Format Descriptions.” https://docs.nvidia.com/deeplearning/tensorrt/latest/inference-library/data-format-desc.html ↩
\nHugging Face, “Quantization Overview.” https://huggingface.co/docs/transformers/quantization/overview ↩
\nNVIDIA, “TensorRT RTX Best Practices.” https://docs.nvidia.com/deeplearning/tensorrt-rtx/latest/performance/best-practices.html ↩
\nHugging Face, “Quantization Concepts.” https://huggingface.co/docs/transformers/quantization/concept_guide ↩
\nMLX, “Unified Memory.” https://ml-explore.github.io/mlx/build/html/usage/unified_memory.html ↩
\nHugging Face, “KV Cache Quantization.” https://huggingface.co/blog/kv-cache-quantization ↩
\nHugging Face, “Cache Strategies.” https://huggingface.co/docs/transformers/kv_cache ↩
\nONNX Runtime, “Execution Providers.” https://onnxruntime.ai/docs/execution-providers/ ↩ ↩2
\nApple, “MLComputeUnits.” https://developer.apple.com/documentation/coreml/mlcomputeunits ↩
\nggml-org, “llama.cpp.” https://github.com/ggml-org/llama.cpp ↩ ↩2
\nHugging Face, “Safetensors.” https://github.com/huggingface/safetensors ↩ ↩2
\nApple, “ML Program Conversion.” https://apple.github.io/coremltools/docs-guides/source/new-conversion-options.html ↩
\nggml-org, “llama.cpp CLI.” https://github.com/ggml-org/llama.cpp/blob/master/tools/cli/README.md ↩ ↩2
\nHugging Face, “Big Model Inference.” https://huggingface.co/docs/accelerate/v0.29.0/en/concept_guides/big_model_inference ↩ ↩2 ↩3
\nGroq and Cerebras attack the accelerator memory problem from different physical directions. Groq makes instruction timing and tensor movement explicit to a compiler across a streaming processor and scale-out network. Cerebras places a grid of compute cores, local memory, and fabric across one wafer, then maps tensor work spatially.
\nBoth designs reduce dependence on a conventional cache hierarchy. Their execution models, scaling boundaries, and software constraints are not interchangeable.
\nProduct throughput and price depend on the model, batch, precision, software revision, and service configuration, so this comparison stays at the architecture level.
\n![\"Two](\"https://blog.ecitis.org/feeds/figures/groq-cerebras-accelerators-0.webp\")
Autoregressive decoding repeatedly reads model parameters and cached attention state for each generated token. At low batch size, arithmetic units can wait for data. General-purpose accelerators address this through HBM, caches, many threads, and runtime scheduling.
\nGroq and Cerebras instead expose more data movement to compilation:
\nThe shared principle is compiler-visible locality. The implementation differs in time, space, and system scale.
\nGroq’s architecture is described in the ISCA paper as a software-defined Tensor Streaming Processor. Functional units act as one logical core and are statically scheduled at compile time. Architecturally visible state includes SRAM and stream registers, allowing the compiler to express computation and communication dependencies as a directed acyclic graph.1
\nA conventional out-of-order processor discovers readiness and resource conflicts while running. A GPU schedules warps and kernels dynamically around latency and occupancy.
\nGroq moves this work into the compiler:
\ngraph lowering\n → place operations on function units\n → allocate SRAM and stream registers\n → schedule operand movement\n → schedule compute\n → schedule chip-to-chip transfers\n → emit one coordinated programPublished Groq technical material states that the compiler accounts for instruction latency and schedules data and instructions at specific times, producing deterministic execution time for a compiled workload.2
\nDeterministic here means the architectural schedule is known. It does not mean a cloud request has no queueing, network, admission-control, or host-side variance.
\nGroq describes its on-chip SRAM as primary storage rather than a hardware-managed cache.3 Data placement is explicit. The compiler knows which SRAM region holds an operand and when that operand moves to a function unit.
\nThis removes cache miss and coherence behavior from the execution schedule. It creates another requirement: the compiler must fit and coordinate program state across available SRAM and chips.
\nFor a model larger than one processor’s SRAM, compilation partitions the graph and parameters across processors. Activations flow between stages while weights needed for each assigned stage remain local.
\nGroq’s public architecture description uses a programmable assembly-line model. Data and instructions move through conveyor-like streams between SIMD function units, with software determining source, operation, and destination.4
\nAn abstract transformer layer can be scheduled as:
\ninput stream\n → normalization unit\n → matrix units for projections\n → vector units for activation and scaling\n → matrix units for output projection\n → output streamThe exact placement is compiler-dependent. The important distinction is that hardware does not discover the flow by filling and draining a cache hierarchy.
\nStatic scheduling extends beyond one processor. The Groq scale-out paper describes a deterministic network in which software schedules vectors on physical links while accounting for channel bandwidth and latency. Hardware does not apply backpressure because unscheduled stalls would break the global timing model.1
\nInstead, local SRAM buffers tensor vectors between hops. Explicit send and receive instructions impose a total ordering that the compiler can reason about.
\nThe published system topology groups eight processors in a node with internal direct links. Nodes connect into a larger topology using a mix of electrical and optical paths.1 The paper specifies this topology for the system it describes; deployed Groq services may use a different generation.
\nArchitectural fact:
\nAnalysis:
\nCerebras builds one processor across most of a silicon wafer rather than cutting the wafer into many reticle-sized dies. The third-generation Wafer-Scale Engine contains 900,000 active AI cores, 44 GB of on-chip SRAM, and 21 PB/s of aggregate on-chip memory bandwidth.5
\nThese are aggregate on-wafer specifications. They should not be compared directly with one memory channel or one network port.
\nThe WSE organizes cores in a two-dimensional grid. Each core combines compute, local SRAM, and router access. The fabric moves data between neighboring and distant cores while the compiler maps tensor dimensions across the grid.
\nCerebras describes transformer mapping by splitting hidden dimensions across one fabric axis and batch and sequence dimensions across the other, enabling weight broadcast and reductions over mapped tensor dimensions.6
\nThis spatial mapping keeps activations near the cores that consume them. It replaces a small set of large compute engines sharing external memory with many smaller engines attached to distributed local memory.
\nA wafer-scale design needs communication across reticle boundaries. Cerebras fabric links continue across those boundaries so the wafer acts as one processor. The compiler routes tensor streams through the mesh and allocates local memory.
\nThe physical distance across a wafer is larger than across one conventional die, so mapping still matters. Nearby placement reduces hops for high-volume communication. The compiler must balance compute, memory, and fabric use.
\nA wafer encounters manufacturing defects. Discarding the complete processor when one core or link fails would make wafer-scale integration impractical.
\nCerebras uses small fault-tolerant cores, spare cores, redundant fabric paths, and routing around defects. Its published WSE-3 material states that the physical design contains 970,000 cores and ships with 900,000 active cores. It reports an approximate core area of 0.05 square millimeters.7
\nArchitectural fact:
\nAnalysis:
\nDo not read the active-core ratio as a universal manufacturing yield. Yield also includes packaging, power delivery, cooling, and system qualification.
\nOn-wafer SRAM cannot hold every parameter and optimizer state of a large model. Cerebras Weight Streaming separates parameter storage from compute.
\nMemoryX stores weights and optimizer state. It streams layer weights to the Wafer-Scale Engine. Activations remain on the engine. During backpropagation, gradients return through SwarmX, which reduces gradients from multiple systems before MemoryX applies updates.8
\nMemoryX\n │ broadcast layer weights\n ▼\nSwarmX tree\n ├── WSE: local activations → gradients\n ├── WSE: local activations → gradients\n └── WSE: local activations → gradients\n ▲\n │ reduce gradients\nMemoryX: optimizer updateThe diagram is structural. It does not specify a cluster size or performance result.
\nThis execution model uses data parallelism across Wafer-Scale Engines while SwarmX handles weight broadcast and gradient reduction. Each engine runs the same model mapping on a different data shard.8
\nCerebras inference material describes storing model weights in on-wafer SRAM and splitting models larger than one wafer at layer boundaries across systems.5 That differs from training Weight Streaming, where MemoryX supplies weights layer by layer and performs optimizer updates.
\nThe term weight streaming therefore needs context:
\n| Property | Groq LPU | Cerebras WSE |
|---|---|---|
| Primary abstraction | Statically timed tensor streams | Spatial graph mapping across a wafer |
| Local memory | Compiler-managed distributed SRAM | Core-local distributed SRAM |
| Execution unit | One logical scheduled core across function units | Grid of independently programmable AI cores |
| Communication | Explicitly scheduled on-chip and chip-to-chip streams | Routes over an on-wafer mesh |
| Scale beyond device | Scheduled processor network | System pipeline or Weight Streaming cluster |
| Large training state | Partitioning depends on compiled system | MemoryX disaggregates weights and optimizer state |
The table describes architecture, not relative performance.
\nBoth systems reward stable tensor shapes. Placement, memory allocation, and communication scheduling improve when dimensions are known.
\nVariable request lengths create a serving problem:
\nThe serving layer must map dynamic requests to compiled execution plans. Architecture-level determinism does not remove batching policy.
\nHigh on-chip bandwidth does not imply that every model fits in local SRAM.
\nFor uncompressed weights:
\n\nA model using a 16-bit representation needs two bytes per parameter. Cerebras uses this arithmetic in its inference architecture explanation and reports 44 GB of WSE-3 SRAM.5 Runtime memory also includes activations, attention state, buffers, and code.
\nGroq distributes weights across processor SRAM when the model exceeds one device. Cerebras can divide an inference model at layer boundaries across systems. Both approaches turn capacity into a placement problem.
\nA request outside compiled bounds needs rejection, a fallback plan, or a new compilation. Silent padding can create latency and capacity regressions.
\nIf one stage takes longer, faster stages wait and buffers fill. Balance must include computation, memory, and communication.
\nTokenization, request scheduling, output streaming, and admission control remain outside accelerator cores. Low accelerator latency can expose these costs.
\nAttention state grows with active sequence length and concurrency. Weight locality does not remove key-value state capacity.
\nGroq’s scheduled network depends on known links and timing. Cerebras placement depends on available wafer and system resources. Fault handling needs a supported remap, recompile, or job restart path.
\nTokens per second can mean per user, per stream, or aggregate server throughput. Batch, prompt length, output length, precision, and model revision must accompany any comparison.
\nUse the same model weights, tokenizer, precision policy, prompt distribution, output lengths, and correctness checks.
\nMeasure:
\nSeparate architecture measurements from managed-service measurements. A cloud endpoint includes routing, capacity, software releases, and tenant load that are not chip properties.
\nGroq’s design fits workloads where a compiler can exploit a stable graph and where deterministic tensor and network schedules support latency-oriented execution. The cost is a stronger compiler contract and less reliance on dynamic hardware scheduling.
\nCerebras fits workloads that benefit from mapping large tensor graphs across a dense core and memory fabric. Wafer-scale integration reduces off-device communication inside the mapped graph, while defect tolerance and compilation make the physical wafer usable as one machine.
\nDistributed-system concerns remain. Groq moves coordination into a static program across processors. Cerebras moves more of the graph inside one wafer and uses explicit system-level pipelines or Weight Streaming beyond it.
\nTrace a token through each machine. On Groq, the compiled schedule coordinates SRAM, functional units, and links. On Cerebras, placement across the wafer determines local memory use and fabric traffic. Fault recovery belongs in the comparison because a remap, recompile, or restart changes system behavior.
\nAbts et al., “A Software-defined Tensor Streaming Multiprocessor for Large-scale Machine Learning,” ISCA, 2022. ↩ ↩2 ↩3 ↩4
\nGroq, “Inside the LPU: Deconstructing Groq’s Speed,” August 2025. ↩
\nCerebras, “Introducing Cerebras Inference,” August 2024. ↩ ↩2 ↩3
\nCerebras, “Architecture Deep Dive: HW/SW Co-Design for Deep Learning”. ↩
\nCerebras, “100x Defect Tolerance: How Cerebras Solved the Yield Problem,” January 2025. ↩ ↩2
\nCerebras, “Linear Scaling Made Possible with Weight Streaming,” September 2022. ↩ ↩2
\nPretraining spends compute once to change model weights. Test-time compute spends compute per problem to search for a better answer without changing the base checkpoint.
\nThat extra compute can take several forms: a longer internal trace, parallel samples, iterative revisions, tree search, tool calls, or verifier passes. Counting generated tokens alone combines mechanisms with different costs and failure modes.
\nA deployment policy must answer:
\n\n\nGiven a fixed inference budget, which candidate should receive the next unit of compute?
\n
![\"A](\"https://blog.ecitis.org/feeds/figures/test-time-compute-0.webp\")
Self-consistency samples several reasoning paths and selects the answer supported by the largest share of paths.1 It replaces a single greedy trajectory with an empirical estimate:
\n\nis a sampled reasoning path and extracts its final answer. The method works when diverse valid paths converge on the same answer more often than invalid paths do.
\nIt can fail when:
\nMajority vote is a verifier built from agreement. It does not inspect whether any path is logically valid.
\nA verifier assigns a score to a complete answer or an intermediate state. Outcome reward models score the result. Process reward models score steps along the path.
\nThe PRM800K work compared outcome and process supervision on mathematical problem solving and found stronger solution selection from process supervision in its evaluated setting.2 A dense process score allows search to stop extending a branch after an early error instead of paying to finish it.
\nFor a partial trajectory , a search policy can rank expansions with:
\n\nis the verifier’s predicted value. The cost term penalizes expensive branches. The uncertainty term can preserve exploration when the verifier is unsure. The coefficients are deployment choices, not universal constants.
\nVerifier quality sets the ceiling. If the verifier rewards polished invalid reasoning, more search directs compute toward the wrong region. The generator and verifier can also share correlated errors when they come from similar training data.
\nSnell and collaborators compared test-time strategies under fixed compute and found that the best allocation depended on problem difficulty and base-model capability.3 Their compute-optimal policy used prompt difficulty to choose how much inference compute to spend, improving efficiency over a fixed best-of- baseline in the reported experiments.
\nThe result rejects a uniform long reasoning budget for every request.
\nA practical router can use:
\nEasy requests should exit early. Difficult but tractable requests may benefit from branching. Requests outside the verifier’s domain should not receive more compute merely because confidence is low.
\n![\"Inference](\"https://blog.ecitis.org/feeds/figures/test-time-compute-1.webp\")
A long chain of thought performs serial computation. Best-of- performs parallel exploration. Tree search mixes both.
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Strategy | Main benefit | Main bottleneck |
|---|---|---|
| Longer trace | More serial intermediate computation | Drift and overthinking |
| Parallel samples | Diverse candidate paths | Repeated shared errors |
| Revision | Error correction after critique | Self-critique may preserve the premise |
| Tree search | Reallocate compute among partial paths | Verifier calibration |
| Tool use | External state or exact checks | Tool latency and integration errors |
The strategies are not interchangeable at equal token counts. Parallel sampling can batch well on accelerators. A serial trace adds latency token by token. Tool calls may dominate both.
\nMeasure wall-clock latency, accelerator occupancy, and verifier cost alongside generated tokens.
\nInference scaling has diminishing returns. A model can find a correct answer, continue exploring, and replace it with a wrong one.
\nRecent work on overthinking separates extra length from useful computation. A Google DeepMind study of open reasoning models identified over-verification and over-exploration as recurring structures in long traces on simple problems.4 Another 2026 preprint reports that optimal reasoning length varies with problem difficulty and that added reasoning can abandon an earlier correct answer.5
\nThis makes stopping a first-class component:
\ngenerate a small candidate set\nscore candidates and estimate uncertainty\nif one candidate is verified with adequate margin:\n stop\nif promising branches remain:\n allocate another search round\notherwise:\n abstain, escalate, or use an external checkerThe stop condition should use calibrated evidence. A high self-reported confidence is weak if the model is miscalibrated on that task class.
\nSearch optimizes the verifier more aggressively than one-shot decoding. That makes test-time compute an online form of proxy optimization.
\nTypical failures include:
\nVerifier exploitation: candidates learn patterns that score well without solving the task.
\nLoss of diversity: early verifier preferences collapse the search around one flawed approach.
\nAnswer leakage: a benchmark-specific checker exposes information unavailable in deployment.
\nCost blindness: marginal accuracy gains consume a service budget that would help more on another request.
\nUnfaithful traces: the visible rationale satisfies a process rubric while the answer is driven by another internal computation.
\nEvaluate the complete generator-search-verifier system on adversarial cases. Evaluating the base model alone misses the mechanism used at inference.
\nAccuracy is necessary but incomplete. A test-time compute service should report:
\nPlot quality against compute across the relevant request distribution. One policy dominates another when it reaches equal or better quality at the same deployment cost.
\nTest-time compute is an inference algorithm that decides what to generate, how to judge it, where to branch, and when to stop. Extra compute pays off when those decisions are more reliable than the candidate errors they are meant to correct.
\nXuezhi Wang et al., “Self-Consistency Improves Chain of Thought Reasoning in Language Models,” ICLR, 2023. https://arxiv.org/abs/2203.11171 ↩
\nHunter Lightman et al., “Let’s Verify Step by Step,” ICLR, 2024. https://arxiv.org/abs/2305.20050 ↩
\nCharlie Snell et al., “Scaling LLM Test-Time Compute Optimally can be More Effective than Scaling Model Parameters,” ICLR, 2025. https://arxiv.org/abs/2408.03314 ↩
\nXinliang Frederick Zhang et al., “Towards Structural Understanding of LLM Overthinking,” ACL, 2026. https://deepmind.google/research/publications/203490/ ↩
\nShu Zhou et al., “When More Thinking Hurts: Overthinking in LLM Test-Time Compute Scaling,” arXiv, 2026. https://arxiv.org/abs/2604.10739 ↩
\nNext-token language modeling supervises one future token at each position. Multi-token prediction attaches several output heads to a shared representation and trains each head to predict a different future offset.
\nThe training objective provides denser supervision. At inference, those heads can propose a short continuation for verification by the main model. The mechanism connects model training and speculative execution without requiring a separate draft model.
\nGiven tokens , a conventional causal model minimizes:
\n\nWith future heads, the objective becomes:
\n\nEach head sees the same causal prefix but has a different target offset. Gloeckle and collaborators use independent output heads built from a shared model trunk and report that the added training-time overhead can be removed at deployment when only the next-token head is retained.1
\n![\"One](\"https://blog.ecitis.org/feeds/figures/multi-token-prediction-0.webp\")
A minimal design projects the final hidden state through independent linear heads. A richer head can include a small transformer block that combines the shared state with an embedding of a previously predicted future token.
\nThe choices affect:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Design | Training cost | Proposal dependence | Inference role |
|---|---|---|---|
| Independent linear heads | Low | Heads do not condition on sibling proposals | Parallel candidate tuple |
| Sequential lightweight heads | Higher | Later proposals condition on earlier ones | Autoregressive draft |
| Tree heads | Higher | Multiple alternatives per depth | Branch verification |
| Auxiliary heads removed | Training only | None at serving | Better trunk supervision |
Independent heads can disagree structurally because the offset head predicts a marginal future token without knowing which earlier proposal was selected. A verification tree can retain several combinations, but candidate count grows with branching.
\nTarget construction is easy to get wrong. For head , logit position must align with token . Tail positions without that future target must be masked from the loss.
\nNear-runnable PyTorch code:
\nimport torch\nimport torch.nn.functional as F\n\ndef multi_token_loss(head_logits, token_ids, weights):\n # head_logits[k]: [batch, sequence, vocabulary]\n total = token_ids.new_zeros((), dtype=torch.float32)\n\n for offset, (logits, weight) in enumerate(\n zip(head_logits, weights), start=1\n ):\n usable = token_ids.size(1) - offset\n if usable <= 0:\n continue\n\n predictions = logits[:, :usable].reshape(-1, logits.size(-1))\n targets = token_ids[:, offset:].reshape(-1)\n total = total + weight * F.cross_entropy(predictions, targets)\n\n return totalProduction code also masks padding, packed-document boundaries, and loss-excluded tokens. A future head must not cross from one packed document into another. Build an offset-specific validity mask from segment identifiers.
\nEvery head contributes gradients to the trunk. Large auxiliary weights can optimize distant predictions at the expense of the primary next-token distribution. Log loss and gradient norms by head.
\nUseful controls include:
\nThe multi-token prediction paper reports stronger gains for larger models and on code tasks, while finding no advantage for small models in some evaluated settings.1 Treat those results as evidence for the paper’s configurations, not a guarantee that more heads improve every model.
\nAt inference, auxiliary heads propose tokens for offsets ahead of the current prefix. The target path verifies candidates with causal attention. A simple linear chain uses one top candidate from each head. A tree uses several candidates at each depth.
\nMedusa trains multiple decoding heads and verifies a tree of candidate continuations in parallel.2 Its tree attention mask permits a node to attend to its ancestors but not to nodes on other branches.
\nFor a chain:
\nshared hidden state\n -> head for offset one proposes a\n -> head for offset two proposes b\n -> head for offset three proposes c\n -> target verifies prefix + [a, b, c]If the target rejects , candidate is invalid because its prefix is no longer the proposed chain. The runtime commits the accepted prefix and a target correction, then drafts again.
\nHeads produce a proposal distribution ; the target produces . Lossless speculative sampling accepts a proposed token with probability:
\n\nOn rejection, it samples from the normalized positive residual . This is the same correction used in speculative sampling with a separate draft model.3 Greedy verification can use token equality but preserves only greedy behavior.
\nTemperature, top-, top-, repetition penalties, and grammar masks must be reflected consistently in proposal and target probabilities. Independent heads that expose only selected token identifiers are insufficient for exact stochastic correction; the verifier needs proposal probabilities.
\nAuxiliary heads add parameters and logits. Materializing full vocabulary logits for every head can consume substantial memory bandwidth. Fused top- selection can avoid writing complete logits to global memory when the verification method needs only candidate tokens and probabilities.
\nServing options:
\nThe shared trunk avoids a second model’s KV cache, but verification candidates still require provisional target-cache positions. Roll back unaccepted suffix blocks without copying the accepted prefix.
\nTree width should be based on verification cost and acceptance, not a fixed aesthetic shape. Let node have estimated probability of being reached and verification cost contribution . Candidate selection can prioritize high while respecting kernel shape and maximum nodes.
\nCalibrate reach probability from held-out traffic. Do not interpret head softmax values as calibrated branch probabilities without checking them. Code, prose, and structured output can have different predictability.
\nCross-document targets: packed training shifts a target into the next document. Mask by segment identifier at every offset.
\nPrimary-head regression: auxiliary gradients reduce next-token quality. Track the primary objective and downstream evaluations independently.
\nHead collapse: distant heads learn frequent-token priors rather than prefix-specific futures. Measure conditional accuracy by token class and entropy.
\nVerification-mask leak: a candidate reads a sibling branch or later token. Compare tree verification logits against independent autoregressive reference runs.
\nMemory-bandwidth regression: writing head logits costs more than the saved target steps. Profile end-to-end time per committed token.
\nStatic head count: easy prompts waste available candidates or difficult prompts waste verification slots. Route using measured acceptance.
\nTokenizer or processor mismatch: head proposals bypass grammar masks or sampling transforms. Centralize logits processing and test equivalence.
\nTraining evaluation needs primary-head perplexity, per-offset loss, downstream task quality, and gradient statistics. Serving evaluation needs:
\nCompare three deployments from the same checkpoint: primary head only, auxiliary heads enabled without speculative verification, and verified multi-token decoding. This separates representation gains from serving gains.
\nMulti-token prediction is useful in two independent ways. It changes the training signal by requiring a prefix representation to predict several future offsets. It also supplies model-native proposals for speculative decoding. Each claim needs its own baseline, because better training loss does not prove faster serving and high acceptance does not prove unchanged sampling.
\nFabian Gloeckle et al., “Better & Faster Large Language Models via Multi-token Prediction,” ICML, 2024. https://arxiv.org/abs/2404.19737 ↩ ↩2
\nTianle Cai et al., “Medusa: Simple LLM Inference Acceleration Framework with Multiple Decoding Heads,” ICML, 2024. https://arxiv.org/abs/2401.10774 ↩
\nCharlie Chen et al., “Accelerating Large Language Model Decoding with Speculative Sampling,” arXiv, 2023. https://arxiv.org/abs/2302.01318 ↩
\nScaling laws fit a small equation to measurements from many training runs. The fitted curve can predict loss at an untested scale and guide the allocation of a fixed training budget. Its domain is limited by the model family, data distribution, optimizer, tokenization scheme, and measurement range used to produce it.
\nRead the equation with its conditions attached:
\n\n\nWithin a measured regime, a chosen metric often changes smoothly enough with scale to support extrapolation.
\n
![\"Scaling](\"https://blog.ecitis.org/feeds/figures/scaling-laws-regimes-0.webp\")
Kaplan and collaborators measured cross-entropy loss while varying parameter count, dataset size, and training compute. They found smooth power-law relationships across their experimental range.1
\nA simplified model-size fit is:
\n\nis parameter count, is an irreducible-loss term for the data distribution, and and are fitted constants. Similar forms can be written for data size or training compute .
\nThe equation describes diminishing returns. Each multiplicative increase in the resource reduces the reducible part of the loss by a fixed factor. The exponent controls the slope on a log-log plot.
\nThree details matter:
\nA curve is useful only with its fitting range, residuals, and held-out prediction error.
\nTraining compute can be spent on more parameters, more tokens, or both. A model with many parameters and too few training tokens may sit above the best achievable loss for its compute budget.
\nThe Chinchilla study trained a large sweep of models and found a different compute-optimal allocation from the earlier Kaplan prescription. Its fitted result called for scaling model size and training tokens together under the studied setup.2 The practical shift was from “make the model larger and stop early” toward “train a smaller model on more data” for a fixed budget.
\nA common joint form is:
\n\nThe parameter-limited term falls with . The data-limited term falls with . Compute optimality chooses a point on the budget constraint where spending more on either side would create a larger penalty on the other.
\n![\"Fixed](\"https://blog.ecitis.org/feeds/figures/scaling-laws-regimes-1.webp\")
The compute-optimal point answers a training allocation question. It does not automatically minimize deployment cost. A serving-heavy product may prefer fewer parameters because inference cost is paid repeatedly. A research model may accept a larger serving cost to reduce pretraining time. A model intended for continued training may deliberately stop before the static optimum.
\nToken count treats every token as interchangeable. Training does not.
\nDeduplication, domain mixture, code proportion, language coverage, and filtering change the mapping from raw tokens to validation loss. DeepSeek’s scaling experiments reported that fitted laws differed across datasets, warning against transferring a curve without checking the data distribution.3
\nData quality creates two distinct questions:
\nThe first supports a clean fit. The second is the real dataset-design problem. If a larger run consumes lower-quality tail data, the original curve may overpredict improvement. If curation improves with scale, it may underpredict it.
\nA scaling experiment should therefore record:
\nWithout those fields, reproducing the curve is harder than reproducing the equation.
\nAbundant-data scaling assumes the next training token can be drawn from a large supply of useful, mostly unique text. That assumption becomes weaker when compute grows faster than the stock of high-quality data.
\nMuennighoff and collaborators studied repeated-data training and found that a limited amount of repetition could retain much of the value of unique data in their experiments, while additional repetition eventually produced declining returns.4 Their scaling law adds a term for the reduced value of repeated tokens.
\nA 2026 preprint proposes SoftQ, a coupled model of parameter count and data size for repeated-data training, arguing that the additive Chinchilla form can be misspecified in this regime.5 The paper evaluates SoftQ for repeated-data training.
\nThe conceptual point is durable: once examples repeat, model size and data size can interact. A larger model may memorize repeated data differently from a smaller model, so independent parameter and data terms can miss structure in the observations.
\nPretraining loss averages prediction error across tokens. A benchmark measures a narrower behavior after prompting, post-training, tool use, or sampling.
\nSuppose two checkpoints have nearly equal validation loss. They can still differ on:
\nThe relationship between loss and a downstream metric can also change when the benchmark saturates or when post-training contributes most of the measured capability.
\nUse a hierarchy of forecasts:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Forecast | Strongest evidence |
|---|---|
| Pretraining loss | Dense checkpoint curves on held-out text |
| Domain loss | Curves on a stable domain-specific corpus |
| Benchmark score | Repeated evaluations across checkpoints and scales |
| Product quality | Task-specific traffic, tools, latency, and post-training |
Each step adds variables not captured by the pretraining curve.
\nA good scaling study runs before the largest training job, not after it. The workflow is:
\nThe fitted optimum should be treated as a region, not a single sacred coordinate. Measurement noise, hardware constraints, checkpoint reuse, and serving economics can make nearby allocations operationally better.
\nA scaling fit supports the measured relationship for one family of systems over one range. Researchers can use that fit to avoid some experimental runs. Extending it to new architectures, repeated data, post-training, test-time reasoning, or user value requires new measurements.
\nJared Kaplan et al., “Scaling Laws for Neural Language Models,” arXiv, 2020. https://arxiv.org/abs/2001.08361 ↩
\nJordan Hoffmann et al., “Training Compute-Optimal Large Language Models,” NeurIPS, 2022. https://arxiv.org/abs/2203.15556 ↩
\nDeepSeek-AI et al., “DeepSeek LLM: Scaling Open-Source Language Models with Longtermism,” arXiv, 2024. https://arxiv.org/abs/2401.02954 ↩
\nNiklas Muennighoff et al., “Scaling Data-Constrained Language Models,” NeurIPS, 2023. https://arxiv.org/abs/2305.16264 ↩
\nZhiwei Xu et al., “Data-Constrained Language Model Pretraining: Improved Regularization and Scaling Laws,” arXiv, 2026. https://arxiv.org/abs/2606.06888 ↩
\nCompression succeeds only when the deployment runtime benefits from the changed model. Removing isolated weights does not guarantee faster dense matrix multiplication. A low-rank factorization does not help if the two smaller operators launch inefficiently. Distillation can produce a smaller model, but its quality depends on the teacher signal and training distribution.
\n![\"Compression](\"https://blog.ecitis.org/feeds/figures/model-compression-techniques-0.webp\")
Choose measurable constraints before modifying the model:
\nParameter count is an intermediate metric. Hardware latency depends on shapes, sparsity support, memory traffic, and kernel launch behavior.
\nMagnitude pruning sets low-magnitude weights to zero. A binary mask produces:
\n\nSparseGPT instead formulates layer-wise pruning with approximate second-order information and reconstructs outputs while removing weights.1 The algorithmic goal is to preserve layer behavior under sparsity, but speed still requires a sparse storage format and kernels that exploit the pattern.
\nAn unstructured sparse matrix stores nonzero values plus indices. At modest sparsity, index overhead and irregular access can outweigh skipped arithmetic. Benchmark the exact matrix shapes on the target runtime.
\nPruning should be followed by recovery tuning when quality loss exceeds the budget. Keep the mask fixed during recovery unless the method explicitly supports regrowth.
\nStructured pruning removes complete channels, attention heads, feed-forward neurons, or layers. The resulting matrices remain dense and can use ordinary kernels. This makes latency benefits easier to realize, but each removal changes more computation than one isolated weight.
\nHead pruning must update:
\nDepth pruning removes whole transformer blocks. Width pruning changes hidden or feed-forward dimensions. NVIDIA’s Minitron work combines depth, width, attention, and feed-forward pruning with distillation-based retraining to derive smaller language models from a pretrained model.2
\nMeasure every candidate architecture instead of assuming proportional latency. A narrower matrix can land on a less efficient hardware tile and produce less speedup than its parameter reduction suggests.
\nKnowledge distillation trains a student against teacher outputs, often using softened class probabilities. Hinton and collaborators described transferring the ensemble or teacher function into a deployable model through this training signal.3
\nFor language models, token-level distillation can minimize:
\n\nwhere is temperature. The student can also train on hard target tokens, hidden-state matches, attention relations, or generated teacher data.
\nTeacher logits expose more information than one sampled token, but full-vocabulary logits are expensive to store. Options include online teacher inference, top-logit storage with a residual bucket, or sequence-level distillation from teacher-generated outputs. Each changes the target.
\nDistillation risks copying teacher errors and narrowing behavior to the transfer distribution. Evaluate the student on real held-out data and safety tests that were not generated by the teacher.
\nFor , a rank- approximation writes:
\n\nThe parameter count changes from to . This is smaller only when is below the break-even rank:
\n\nTruncated singular value decomposition provides a reconstruction-optimal low-rank approximation under the Frobenius norm, but minimizing weight reconstruction error does not directly minimize model loss. Recovery tuning can adapt the factors to the data distribution.
\nRuntime performance depends on both factor matrices. Very small intermediate rank can become launch-bound. A fused implementation or batching may be needed to realize latency gains.
\nLow-rank adapters such as LoRA are parameter-efficient fine-tuning mechanisms, not automatic base-model compression. Keeping the frozen base matrix plus adapters adds parameters. Compression occurs only if the deployed representation replaces or restructures the base computation.
\nPruning, factorization, and distillation interact. A useful sequence is:
\nThis is not universal. Quantization-aware training may need to participate in recovery. Unstructured sparse kernels may require pruning to a hardware-specific pattern before export.
\nChange one compression axis at a time during diagnosis. If pruning, factorization, and quantization are applied together, a quality regression cannot be localized.
\nLanguage models can tie input embeddings to the output projection or reuse parameters across layers. A generic traversal that replaces modules independently can break aliasing and duplicate storage.
\nBefore compression, build an alias map:
\nowners = {}\nfor name, parameter in model.named_parameters(remove_duplicate=False):\n owners.setdefault(id(parameter), []).append(name)\n\nshared = [names for names in owners.values() if len(names) > 1]After rewriting the graph, confirm that intended aliases remain tied and the optimizer does not update duplicate copies.
\nThe in-memory training model is not the deployment artifact. Exporters can fold constants, transpose weights, reject sparse operators, or lower factorized layers into unexpected subgraphs.
\nFor each target runtime:
\nA compressed checkpoint that falls back to CPU for one unsupported sparse operator can be slower than the dense baseline.
\nCompression error is not uniform. Pruning can damage rare features. Distillation can suppress low-probability alternatives. Low-rank approximation can remove directions that matter for a small task slice.
\nEvaluate:
\nCompare against an uncompressed checkpoint under identical decoding settings. If the compressed model needs a different sampler to recover quality, report both the model and sampler change.
\nMask drift: Pruned weights become nonzero during tuning because the optimizer updates them. Reapply the mask after updates or use masked parameterization.
\nShape mismatch: Structured pruning updates weights but not configuration, rotary tables, or tensor-parallel metadata. Load the exported model in a fresh process before declaring success.
\nTeacher leakage: Evaluation prompts or their derivatives enter distillation data. Split source groups before teacher generation.
\nRank collapse: A factorization uses one rank for every layer despite different spectra and sensitivity. Allocate rank by measured reconstruction and downstream loss.
\nNo runtime gain: The artifact is smaller but latency is unchanged. Inspect kernels, launch count, memory bandwidth, and sparse support.
\nCompression is a contract between an algorithm and a runtime. Unstructured pruning needs sparse execution, structured pruning needs valid dense shapes, distillation needs independent evaluation, and factorization needs efficient paired operators. The final evidence is an exported model that meets memory, latency, and quality budgets on its target hardware.
\nPost-training pipelines collect preferences, optimize a policy, and test whether the assistant is helpful and safe. The training signal is a proxy for intended behavior. The model must generalize that proxy to inputs, tools, and situations absent from training.
\nUse the following operational definition:
\n\n\nAn aligned model follows the intended specification when the evaluator is weak, the context is unfamiliar, and shortcuts are available.
\n
This definition turns alignment into a control problem. The system needs a specification, a way to convert that specification into supervision, an optimizer, and measurements that expose failures. Any one of those parts can be wrong while benchmark scores improve.
\n![\"Alignment](\"https://blog.ecitis.org/feeds/figures/model-alignment-control-loop-0.webp\")
The standard reinforcement learning from human feedback pipeline begins with a pretrained model, supervised instruction tuning, pairwise preference data, a reward model, and policy optimization. InstructGPT established this pipeline for instruction-following language models.1
\nFor prompt , completion , learned reward , and reference policy , the policy objective is commonly written as:
\n\nThe reward term pulls behavior toward the preference model. The KL term limits movement away from the reference policy. Neither term states the desired behavior directly. The reward model learns it from comparisons, and the comparisons reflect annotator instructions, sampling policy, prompt distribution, and labeling noise.
\nDirect Preference Optimization rewrites this constrained reward problem as a classification loss on preferred and rejected responses.2 It removes the separately trained reward model and online reinforcement learning loop, but it does not remove the proxy problem. The chosen response still represents a judgment made under a particular rubric and context.
\nThese layers can fail independently:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Layer | What it contains | Common failure |
|---|---|---|
| Intended behavior | What the system should do | Ambiguous or conflicting goals |
| Written specification | Policies, principles, examples | Gaps and underspecified edge cases |
| Supervision | Preferences, critiques, step labels | Evaluator error or shortcut features |
| Training objective | Reward or preference loss | Proxy optimization |
| Deployed policy | Behavior under new conditions | Distribution shift or strategic adaptation |
A higher reward is evidence that the policy fits the learned proxy. It is not proof that the proxy captures the intended behavior.
\n![\"Alignment](\"https://blog.ecitis.org/feeds/figures/model-alignment-control-loop-1.webp\")
Constitutional AI replaces some human harmlessness labels with model-generated critiques and preferences conditioned on written principles.3 Its supervised phase asks a model to critique and revise responses. Its reinforcement learning phase uses AI-generated preferences to train a preference model.
\nThis changes where human judgment enters the system. Humans write or approve principles rather than label every sampled answer. The principles are easier to inspect than a reward model’s weights, but their interpretation still depends on the model producing the critique.
\nDeliberative alignment moves the specification closer to inference. A reasoning model is trained to recall and apply written safety policies before producing an answer.4 This can improve decisions that require combining several policy clauses. It also creates a new object to evaluate: whether the model selected the relevant policy and applied it to the facts of the request.
\nThe two methods expose different failure surfaces:
\nWritten specifications improve inspectability. They do not guarantee faithful internal reasoning.
\nOutcome supervision rewards a final answer. Process supervision evaluates intermediate steps. On mathematical reasoning tasks, the work behind PRM800K found that a process-supervised reward model selected better solutions than an outcome-supervised reward model in the evaluated setting.5
\nThe alignment relevance is credit assignment. An outcome-only reward can reinforce a correct answer reached through an invalid or unsafe process. Step-level labels can penalize the first bad transition before later steps conceal it.
\nProcess supervision also has costs:
\nChoose process checkpoints according to risk. A coding agent can be evaluated at each file mutation or shell command. A medical assistant may need evidence checks before advice. A long-horizon agent needs stateful constraints that survive across turns.
\nHuman preference learning assumes the evaluator can recognize a better answer. That assumption weakens as models operate in domains where checking a solution is harder than producing one.
\nWeak-to-strong generalization studies an empirical proxy for this problem: a weaker model supervises a stronger model, and researchers measure whether the strong model can exceed the supervisor’s errors rather than imitate them.6 The reported results show partial recovery of stronger capabilities on some tasks, alongside failures on preference data. The setup is evidence that the question can be tested, not a solution to superhuman oversight.
\nScalable oversight methods try to restructure evaluation:
\nThe evaluator must remain independent enough to catch shared mistakes. Two models trained on similar data can agree for the same wrong reason.
\nBehavioral red teaming is weak when a model behaves differently after detecting an evaluation. Model organisms address this by deliberately training models with known hidden objectives or failure propensities, then asking auditors to recover them.7
\nThis creates a ground truth for audit research. If the experimenter knows the hidden objective, an audit can be scored on whether it identifies the cause and its behavioral traces.
\nAnthropic’s automated auditing work combines behavioral evaluations, training-data inspection, and interpretability tools against such models.7 The approach tests an entire investigation workflow rather than one probe. It also reveals a deployment lesson: a monitor should generate falsifiable hypotheses, design counterexamples, and seek causal evidence.
\nUseful causal checks include:
\nCorrelation can point to a mechanism. Intervention tests whether the mechanism carries causal weight.
\nA deployment report should separate the layers of evidence:
\nAn alignment claim needs a stated threat model and operating environment. Its evidence should connect an inspectable specification to traceable supervision, audits that expose known hidden failures, and deployment monitoring that detects behavior outside the tested regime.
\nLong Ouyang et al., “Training language models to follow instructions with human feedback,” NeurIPS, 2022. https://arxiv.org/abs/2203.02155 ↩
\nRafael Rafailov et al., “Direct Preference Optimization: Your Language Model is Secretly a Reward Model,” NeurIPS, 2023. https://arxiv.org/abs/2305.18290 ↩
\nYuntao Bai et al., “Constitutional AI: Harmlessness from AI Feedback,” Anthropic, 2022. https://www.anthropic.com/research/constitutional-ai-harmlessness-from-ai-feedback ↩
\nMelody Guan et al., “Deliberative alignment: reasoning enables safer language models,” OpenAI, 2024. https://openai.com/index/deliberative-alignment/ ↩
\nHunter Lightman et al., “Let’s Verify Step by Step,” ICLR, 2024. https://arxiv.org/abs/2305.20050 ↩
\nCollin Burns et al., “Weak-to-Strong Generalization: Eliciting Strong Capabilities With Weak Supervision,” ICML, 2024. https://openai.com/index/weak-to-strong-generalization/ ↩
\nTrenton Bricken et al., “Building and evaluating alignment auditing agents,” Anthropic, 2025. https://alignment.anthropic.com/2025/automated-auditing/ ↩ ↩2
\nAn optimizer defines both an update rule and a distributed state system. For a large transformer, moment tensors, matrix statistics, preconditioner roots, communication, and checkpoint format can consume as much engineering attention as the gradient formula.
\n![\"Optimizer](\"https://blog.ecitis.org/feeds/figures/llm-training-optimizers-0.webp\")
Adam maintains exponential moving averages of gradients and squared gradients:
\n\n\nBias-corrected estimates scale the update coordinate-wise. The original Adam paper introduced this adaptive first-order method.1
\nAdamW applies weight decay separately from the loss-gradient update:
\n\nDecoupling matters because adding an penalty to the gradient is not equivalent to weight decay under an adaptive preconditioner.2
\nEach parameter normally has full-shape first- and second-moment state. Distributed optimizers shard these states across data-parallel ranks and gather updated parameter partitions as needed. Checkpoint conversion must preserve the association among a parameter and both moments.
\nExclude parameters such as normalization scales or biases from decay only through an explicit, reviewed grouping rule:
\ndecay, no_decay = [], []\nfor name, parameter in model.named_parameters():\n if not parameter.requires_grad:\n continue\n target = no_decay if is_no_decay_parameter(name, parameter) else decay\n target.append(parameter)\n\ngroups = [\n {\"params\": decay, \"weight_decay\": weight_decay},\n {\"params\": no_decay, \"weight_decay\": 0.0},\n]Test that every trainable parameter appears once and only once.
\nFor a matrix parameter, Adafactor approximates the full second-moment accumulator using row and column statistics. This changes state from matrix-sized storage to vectors sized by its dimensions. The Adafactor paper presents sublinear auxiliary storage for large parameter matrices.3
\nThe approximation preserves less coordinate-level information than a full accumulator. It is most useful when large matrix parameters dominate. Vectors and small tensors need a different state rule because row-column factorization is not meaningful.
\nAdafactor also introduced relative-step and update-clipping choices. Libraries expose different defaults, so a configuration copied by optimizer name alone may not reproduce another implementation. Record:
\nMemory savings are not free if the training recipe silently changes several of these at once. Run an ablation that holds schedule and decay semantics constant where the implementation permits it.
\nShampoo builds statistics along tensor dimensions and applies matrix inverse roots as a preconditioner. For a matrix gradient , simplified left and right statistics accumulate forms related to:
\n\n\nThe preconditioned update uses inverse roots of and . The Shampoo paper develops this tensor-aware preconditioning while controlling dependence on the full flattened parameter dimension.4
\nMatrix roots are more expensive than elementwise square roots. Practical systems update preconditioners periodically, block large dimensions, run root computations in higher precision, or distribute them across ranks. These implementation choices define the optimizer’s real cost.
\nMonitor:
\nIf a preconditioner contains non-finite values, skipping only that parameter update can desynchronize replicas unless every rank makes the same decision.
\nMuon applies momentum to matrix gradients, then approximately orthogonalizes the update with an iterative Newton-Schulz procedure. The scalable Muon work applies it to hidden-layer matrix parameters while using AdamW for embeddings, output heads, and other parameters.5
\nThis split is part of the algorithmic contract. Matrix orthogonalization is not defined the same way for vectors, and very rectangular or partitioned matrices require careful handling.
\nA conceptual update is:
\nmomentum = update_momentum(gradient, momentum, beta)\nmatrix_update = orthogonalize_newton_schulz(momentum)\nparameter -= learning_rate * scale(parameter.shape) * matrix_updateThe iteration count, polynomial coefficients, normalization, accumulation dtype, and shape-dependent scale affect output. Pin them in checkpoints and experiment records.
\nTensor parallelism creates another question: orthogonalize each local shard or the logical global matrix. Local orthogonalization is cheaper but is a different preconditioner. The training code must state which object the optimizer sees.
\n| Optimizer | Dominant state for a matrix | Extra compute | Main systems concern |
|---|---|---|---|
| AdamW | full first and second moments | elementwise updates | state sharding and bandwidth |
| Adafactor | factored second moment, optional momentum | reductions over dimensions | implementation-specific schedule |
| Shampoo | dimension-wise covariance matrices | periodic matrix roots | blocking, precision, distribution |
| Muon | momentum plus temporary orthogonalization state | iterative matrix products | parameter selection and sharding |
This table describes structure, not a universal speed ranking. Kernel fusion, dtype, matrix shape, update frequency, and network topology determine runtime.
\nDo not compare optimizers under one shared learning rate and call the result controlled. Their preconditioners produce updates with different scales. Tune learning rate, warmup, decay, clipping, and optimizer-specific parameters on a smaller proxy that preserves architecture and data characteristics.
\nTrack the update-to-weight norm:
\n\nReport it by parameter class. Embeddings, attention projections, feed-forward matrices, and normalization parameters can behave differently. Aggregate loss can hide one group with unstable updates.
\nGradient norm clipping before optimizer state update is not equivalent to clipping the preconditioned update. Adafactor’s update clipping and external gradient clipping are different mechanisms. Muon’s orthogonalized update changes norm geometry again.
\nDocument the order:
\nunscale mixed-precision gradients\ncheck finite values\napply gradient clipping\nupdate optimizer statistics\nconstruct preconditioned update\napply decoupled weight decay\nupdate parameters\nadvance schedulerDistributed global-norm clipping requires a reduction over all shards. A local norm threshold changes with shard count.
\n![\"Optimizer](\"https://blog.ecitis.org/feeds/figures/llm-training-optimizers-1.webp\")
An optimizer checkpoint must include step counters, moments or factors, preconditioner statistics, loss-scaler state, scheduler state, and parameter-group mapping. For periodic Shampoo roots, include enough state to resume the same update cadence. For Muon, preserve momentum and the exact parameter classification.
\nRun a deterministic recovery test:
\nTopology changes require resharding. Verify on a small checkpoint before applying it to a full run.
\nChoose AdamW when a proven recipe, broad implementation support, and predictable coordinate-wise adaptation matter more than state volume. Choose Adafactor when matrix state is the binding capacity constraint and the recipe has been qualified. Evaluate Shampoo when training can amortize stronger preconditioning and the system can support matrix-statistic work. Evaluate Muon when hidden matrix updates dominate and the implementation defines parameter selection, scaling, and distributed semantics.
\nNo optimizer removes the need to inspect data, model initialization, and loss scaling. The useful comparison includes convergence per processed token, wall-clock time, peak memory, communication, recovery behavior, and final evaluation under equal data budgets.
\nMechanistic interpretability tries to explain model behavior in terms of internal computation. The frontier has moved beyond finding a neuron that correlates with a concept. Current methods decompose activations into features, trace interactions between those features, translate internal states into text, and intervene to test causal claims.
\nThese tools should not be ranked on one axis. They expose different objects.
\n![\"A](\"https://blog.ecitis.org/feeds/figures/frontier-mechanistic-interpretability-0.webp\")
Individual neurons are often polysemantic: one neuron responds to several unrelated patterns. The superposition hypothesis proposes that models encode more features than there are activation dimensions by placing sparse features in overlapping directions.
\nA sparse autoencoder learns a dictionary that reconstructs an activation from a sparse code :
\n\n\nTraining balances reconstruction with sparsity:
\n\nAnthropic’s early dictionary-learning work extracted more monosemantic features than the source neurons from a small transformer.1 The later Scaling Monosemanticity project trained sparse autoencoders on Claude 3 Sonnet and demonstrated that the approach could recover interpretable feature directions from a production-scale model.2
\nA feature label usually comes from examples that activate it, tokens it promotes, or an automated explanation. That label remains a hypothesis. Similar-looking features can differ in their downstream effects, and a single feature can have behavior that its top activating examples do not reveal.
\nUseful SAE evaluation separates:
\nA dictionary can reconstruct activations well while dividing concepts in a way that is awkward for human analysis.
\nAn SAE describes an activation at one point. A transcoder predicts the output of a model component from its input using sparse features. A cross-layer transcoder extends the idea across several layers, letting features represent computations whose natural span does not fit one layer.
\nAnthropic’s circuit-tracing work replaces opaque model components with cross-layer transcoders, then constructs attribution graphs for a specific prompt and output.3 Nodes are interpretable features. Edges estimate how one feature contributes to another feature or to the selected output logit.
\nAn attribution graph can reveal several paths that converge on one token:
\nprompt tokens\n -> contextual features\n -> intermediate computation features\n -> output-promoting features\n -> selected tokenThe graph is local to a prompt and output. It is not a complete schematic of the model. The replacement model also introduces approximation error, so an attractive graph can omit computation carried by unexplained variance.
\nValidation requires interventions. Circuit tracing uses feature ablation, activation patching, and graph-based predictions to test whether a proposed path affects the output as expected.3
\nEarly attribution graphs focused on multilayer perceptron computation. Attention adds conditional information movement between token positions.
\nAnthropic’s 2025 attention work decomposes query-key interactions in terms of feature pairs and integrates them into attribution graphs.4 The method traces why a destination feature selected a source feature, rather than stopping at the attended position.
\nAn attention pattern shows routing. It does not identify the operation performed on the routed information. A head attending to a name token could copy the name, suppress it, compare it, or use another feature stored at the same position.
\nA stronger analysis identifies:
\nThe explanation becomes mechanistic when it accounts for both routing and content.
\nNatural Language Autoencoders place a text bottleneck between an activation and its reconstruction.5 An activation verbalizer maps the target model’s activation to a natural-language explanation. An activation reconstructor maps that explanation back into activation space. The pair is trained to reconstruct activations.
\nThe training objective does not directly require explanations to be human-readable or faithful. The text is useful because it must preserve information needed for reconstruction, and the paper evaluates whether that information helps with downstream analysis.5
\nNLAs offer several practical advantages:
\nThe method also has a distinct risk: a fluent explanation can look more certain than the evidence supports. Reconstruction proves that the text transmits some activation information. It does not prove that every phrase is a faithful semantic description.
\nThe NLA paper validates case studies with independent evidence such as prompt variations, training-data inspection, other interpretability methods, and interventions.5 That triangulation should be treated as part of the method, not optional polish.
\nThe Jacobian lens asks which internal directions are disposed to affect future verbal output. Anthropic’s J-space work finds that a sparse set of these directions supports report, directed control, multi-step reasoning, and flexible reuse.6
\nThis tool differs from an SAE:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Method | Dictionary source | Primary object |
|---|---|---|
| Sparse autoencoder | Learned reconstruction features | Sparse activation content |
| Cross-layer transcoder | Learned component approximation | Feature-to-feature computation |
| Natural-language autoencoder | Learned text bottleneck | Free-form activation report |
| Jacobian lens | Average causal map to future outputs | Verbalizable workspace directions |
The methods can support one another. SAE features with strong J-space alignment may identify workspace content more precisely than single-token J-lens vectors. J-lens readouts can label what a transcoder feature reads and writes. NLA explanations can propose concepts for targeted feature or lens interventions.
\nNo single interpretability result should carry a safety decision by itself. A robust audit progresses from broad detection to narrow causal tests:
\n![\"Interpretability](\"https://blog.ecitis.org/feeds/figures/frontier-mechanistic-interpretability-1.webp\")
Agreement across methods is useful only when their errors are not identical. Two tools trained on the same activation data and scored by the same model can share blind spots.
\nThe current toolchain still leaves hard gaps.
\nCompleteness: A readable circuit can explain part of an output while missing another causal path.
\nScalability: Long agent trajectories produce many activations and candidate features.
\nRelational structure: Sparse feature lists often omit how concepts bind together.
\nAdversarial robustness: A model trained against a monitor may route cognition through representations the monitor does not capture.
\nFaithfulness: Natural-language explanations and visible reasoning can describe a plausible process without being the cause.
\nAutomation: Model-based feature labels and audit agents increase coverage but introduce another learned evaluator.
\nRecent work pairs human-readable interpretations with interventions that should change behavior when the interpretation is correct. A mechanistic claim should survive causal tests and predict failures on new inputs.
\nTrenton Bricken et al., “Towards Monosemanticity: Decomposing Language Models With Dictionary Learning,” Transformer Circuits, 2023. https://transformer-circuits.pub/2023/monosemantic-features/index.html ↩
\nAdly Templeton et al., “Scaling Monosemanticity: Extracting Interpretable Features from Claude 3 Sonnet,” Transformer Circuits, 2024. https://transformer-circuits.pub/2024/scaling-monosemanticity/index.html ↩
\nEmmanuel Ameisen et al., “Circuit Tracing: Revealing Computational Graphs in Language Models,” Transformer Circuits, 2025. https://transformer-circuits.pub/2025/attribution-graphs/methods.html ↩ ↩2
\nHarish Kamath et al., “Tracing Attention Computation Through Feature Interactions,” Transformer Circuits, 2025. https://transformer-circuits.pub/2025/attention-qk/index.html ↩
\nKit Fraser-Taliente et al., “Natural Language Autoencoders Produce Unsupervised Explanations of LLM Activations,” Transformer Circuits, 2026. https://transformer-circuits.pub/2026/nla/index.html ↩ ↩2 ↩3
\nWes Gurnee et al., “Verbalizable Representations Form a Global Workspace in Language Models,” Transformer Circuits, 2026. https://transformer-circuits.pub/2026/workspace/index.html ↩
\nDistributed AI performance depends on moving tensors at the time the computation graph needs them. Link rate matters, but topology, collective algorithm, message size, congestion, and synchronization determine how much of that rate becomes useful work.
\nNVLink, Infinity Fabric, InfiniBand, and RoCE do not occupy one interchangeable layer. NVLink and accelerator-facing Infinity Fabric build scale-up domains. InfiniBand and RoCE connect nodes across a scale-out fabric. PCIe and network adapters bridge those domains.
\n![\"AI](\"https://blog.ecitis.org/feeds/figures/ai-cluster-networking-0.webp\")
Data parallel training commonly uses reduce-scatter followed by all-gather to average gradients. Tensor parallelism adds collectives inside transformer layers. Pipeline parallelism sends activations between stages. Expert parallelism routes token representations to selected experts.
\nFor a ring all-reduce with participants and a payload of bytes per participant, each participant transfers:
\n\nThe formula shows why a bandwidth bottleneck affects large gradient buffers. It does not predict latency by itself. A performance model also needs per-step latency, effective bandwidth, and overlap with compute:
\n\nHere, is the per-step latency term and is measured application bandwidth.
\nAccelerator packages connect compute dies, memory stacks, and I/O dies through internal fabrics. AMD’s MI300X combines eight accelerator complex dies, eight HBM3 stacks, and four I/O dies through Infinity Fabric. The package provides an aggregate theoretical memory bandwidth of 5.3 TB/s.1
\nThat figure is HBM bandwidth inside one accelerator package. It is not GPU-to-GPU link bandwidth.
\nA scale-up domain gives accelerators direct peer access and collective paths without crossing a conventional data-center network. NVIDIA NVLink links GPUs to peers or NVSwitch. AMD Infinity Fabric links accelerators inside supported nodes.
\nScale-out fabrics connect many compute nodes through network interface cards and switches. InfiniBand supplies an integrated RDMA fabric. RoCE carries RDMA transport over Ethernet.
\nThe boundary can extend across racks on newer platforms, but the diagnostic distinction remains useful: first identify the package, local accelerator fabric, host I/O, and network hop involved.
\nNVLink is NVIDIA’s high-bandwidth GPU interconnect. NVSwitch provides switched connectivity so a GPU can reach peers through an NVLink fabric rather than a point-to-point-only layout.
\nFifth-generation NVLink in Blackwell systems provides up to 1,800 GB/s of aggregate bandwidth per GPU. NVIDIA’s GB300 NVL72 reference architecture uses nine NVLink switch trays, with two NVSwitch ASICs per tray, to connect 72 GPUs in one rack-scale domain.2
\nThose specifications describe a particular platform generation and topology. Do not apply them to an H100 server or a PCIe-only deployment.
\nNVLink is useful for:
\nNVSwitch does not make every pairwise transfer free. Collective libraries still choose channels, chunk sizes, trees, or rings. Contention appears when concurrent jobs or collective phases share fabric paths.
\nInfinity Fabric is AMD’s interconnect family across package and node scopes. On MI300X, it connects package components and supports an eight-accelerator node in which each accelerator has seven high-bandwidth Infinity Fabric links, forming a fully connected topology.1
\nThe topology reduces the need for intermediate accelerator hops inside that node. Collective placement still matters:
\nrank → accelerator mapping → Infinity Fabric peer path → NIC affinityIf the network interface is closest to one CPU socket or accelerator group, a poor rank map can send scale-out traffic across additional host or fabric links.
\nInspect the platform topology rather than assuming device numbering follows physical adjacency. Use the communication library’s topology dump and measure peer bandwidth for the installed firmware, driver, and link state.
\nInfiniBand defines an I/O architecture for servers, storage, and communication infrastructure. It supports send and receive messaging plus RDMA memory operations without software involvement in the data movement path.3
\nAn InfiniBand network contains:
\nNVIDIA’s QM9700 and QM9790 NDR switches expose 64 ports at 400 Gb/s per port in a one-rack-unit chassis.4 Port rate is not collective bandwidth. Encoding, protocol overhead, PCIe, host memory registration, message size, and fabric contention all affect delivered throughput.
\nInfiniBand fabrics can supply adaptive routing, virtual lanes, and in-network collective operations on supported platforms. These features need topology-aware configuration and telemetry. A nominally nonblocking topology can still hotspot if routing sends synchronized flows through the same spine links.
\nRDMA over Converged Ethernet uses RDMA semantics on Ethernet infrastructure. RoCE version one operates at the link layer and remains within an Ethernet broadcast domain. RoCE version two carries the InfiniBand transport protocol over UDP and IP, so it can cross routed networks.5
\nRoCE makes Ethernet a viable AI transport, but Ethernet loss and congestion behavior must be engineered for synchronized, high-rate flows.
\nTwo controls appear often:
\nPriority Flow Control: pauses one Ethernet priority rather than the whole link. NVIDIA’s switch documentation describes eight virtual links that can be paused independently.6
\nExplicit Congestion Notification: marks packets instead of dropping them when queues cross configured thresholds. A RoCEv2 receiver generates a congestion notification packet toward the sender, which reduces its sending rate.5
\nPFC and ECN solve different problems. PFC prevents loss for a traffic class through hop-by-hop pause. ECN provides end-to-end congestion signaling. Poor PFC design can propagate pauses and create head-of-line blocking. Poor ECN thresholds can react too late or throttle too aggressively.
\n| Question | InfiniBand | RoCEv2 |
|---|---|---|
| Link and transport | Purpose-built InfiniBand stack | RDMA transport over routed Ethernet |
| Fabric operations | Subnet management and InfiniBand routing | Ethernet routing, VLAN, QoS, ECN, and optional PFC |
| Operational reuse | Separate fabric skill set | Can share Ethernet platform and practices |
| Failure focus | Routing, link state, credit and service-level behavior | Queueing, ECN, PFC, loss, and Ethernet configuration |
The choice is operational as much as architectural. A well-instrumented RoCE fabric can outperform a poorly operated InfiniBand fabric for a workload, and the reverse is also true. Evaluate delivered collective performance and recovery behavior.
\nA node can have fast local peer links and fewer network interfaces than accelerators. Scale-out traffic must then reach a NIC through a local path.
\nConsider a topology with accelerator groups attached to different CPU sockets:
\nGPU group A ─ local fabric ─ NIC A ─ leaf switch\n │\n host interconnect\n │\nGPU group B ─ local fabric ─ NIC B ─ leaf switchBind processes so each rank uses the nearest accelerator and NIC. Crossing the host interconnect for every collective adds a bottleneck not visible in the network port rate.
\nHierarchical collectives exploit this structure:
\nThe best algorithm depends on payload size and topology. Trees reduce startup steps for some small messages. Rings make predictable use of bandwidth for large messages. Communication libraries select algorithms dynamically, but their decision needs accurate topology discovery.
\nAI communication is synchronized. Many ranks enter the same collective near the same time, creating burst patterns unlike independent storage flows.
\nCommon problems:
\nAverage link utilization can look low while short queue spikes dominate step time. Collect high-resolution queue, ECN, PFC, retransmission, and link-error counters.
\nUse a ladder:
\nA point-to-point benchmark does not validate all-reduce. An all-reduce benchmark does not validate expert all-to-all.
\nReport topology and software with results:
\naccelerators_per_node: 8\nnics_per_node: 8\nfabric: 'RoCEv2'\ncollective: 'all_reduce'\npayload_bytes: '<measured case>'\ndriver_revision: '<pinned revision>'\nfirmware_revision: '<pinned revision>'The values in this configuration are an example schema, not a recommended cluster design.
\nOne node is slow: check accelerator link state, NIC affinity, PCIe width, firmware, thermal state, and error counters.
\nPerformance drops only across racks: inspect oversubscription, routing entropy, spine utilization, and optical errors.
\nLarge messages are slow: inspect effective bandwidth, rail balance, and algorithm selection.
\nSmall messages are slow: inspect launch, synchronization, and per-step latency.
\nRoCE stalls under load: inspect PFC pause frames, ECN marks, congestion notification packets, queue occupancy, and packet loss.
\nRuns vary despite stable bandwidth: inspect competing jobs, adaptive routing, CPU scheduling, and collective synchronization.
\nModel the communication phase from workload bytes, not advertised FLOPS:
\nrequired fabric time\n = bytes transferred per step\n / measured effective bandwidthThen compare it with the compute phase and determine which communication can overlap. If an exposed collective occupies the critical path, faster compute makes the network fraction larger.
\nInclude failure capacity. A fabric that meets the target only with every link healthy has no room for maintenance, rerouting, or a failed rail.
\nCluster networking is a hierarchy. Preserve that hierarchy in topology maps, benchmarks, and alerts. A single “network bandwidth” number erases the exact boundary that must be fixed.
\nAMD ROCm documentation, “AMD Instinct MI300 series microarchitecture”. ↩ ↩2
\nNVIDIA Enterprise Reference Architecture, “NVL72 AI Factory System Hardware and Components”. ↩
\nNVIDIA, “QM9700 and QM9790 1U NDR 400Gb/s InfiniBand Switch Systems User Manual”. ↩
\nNVIDIA Cumulus Linux documentation, “RDMA over Converged Ethernet”. ↩ ↩2
\nDiffusion and flow matching define learning problems over paths between a tractable noise distribution and the data distribution. The neural network architecture can be shared, but the target, time parameterization, and sampler determine what the network predicts and how generation integrates it.
\n![\"Two](\"https://blog.ecitis.org/feeds/figures/diffusion-flow-matching-0.webp\")
A forward diffusion process gradually corrupts data into . A common Gaussian parameterization is:
\n\nTraining samples a data point, a time , and noise . A network can predict , the score , the clean sample, or a velocity parameterization derived from them. Denoising Diffusion Probabilistic Models connected this training objective to denoising score matching and a learned reverse Markov chain.1
\nThe noise schedule controls signal-to-noise ratio across time. Loss weighting determines which regions of that schedule dominate updates. These choices affect optimization even when the architecture is unchanged.
\nAt inference, generation starts from noise and applies a numerical solver. A stochastic reverse SDE injects randomness along the path. A probability-flow ODE follows a deterministic trajectory for a fixed initial noise. Sampler order and step placement trade network evaluations, truncation error, and stability.
\nFlow matching chooses a probability path and trains a vector field to transport samples along it:
\n\nThe Flow Matching paper showed that conditional vector fields can provide a simulation-free training objective and include diffusion paths as a special case.2 Training does not require solving the ODE for every update. It samples points on a conditional path and regresses the target velocity.
\nFor a simple linear interpolation between noise and data :
\n\nthe conditional velocity is . In practice, the coupling between noise and data and the selected path affect trajectory geometry. A straight conditional interpolation does not imply that the marginal vector field is trivial.
\nNoise, clean-sample, score, and velocity prediction can often be converted when and are known. They do not produce identical numerical conditioning under finite precision, imperfect networks, or weighted losses.
\nUse one canonical internal definition:
\ndef interpolate(clean, noise, alpha_t, sigma_t):\n sample = alpha_t * clean + sigma_t * noise\n velocity = alpha_t * noise - sigma_t * clean\n return sample, velocityThe exact velocity formula depends on the schedule convention. Tests should verify conversions at schedule endpoints and intermediate times.
\nA U-Net uses multiscale convolutional features, skip connections, and attention blocks. It matches image locality and provides feature maps at several resolutions. A diffusion transformer tokenizes latent patches and applies transformer blocks conditioned on time and text. Diffusion Transformers demonstrated that transformer compute can replace the conventional U-Net backbone in latent diffusion.3
\nArchitecture selection changes:
\nThe network output still represents the selected denoising or flow target.
\nPixel-space generation carries high-dimensional spatial tensors through every network evaluation. Latent diffusion uses an encoder to map images into a lower-dimensional representation, trains the generative process in that space, then decodes the result.4
\nThis introduces a separate reconstruction contract. Fine texture, text, faces, and high-frequency patterns can be limited by the autoencoder even if the denoiser is accurate. Evaluate reconstruction error independently by encoding and decoding real samples without generation.
\nLatent scaling must match training. A missing scale factor changes the effective noise distribution and can produce washed-out or saturated samples.
\nText conditioning commonly uses cross-attention from image or video tokens to text-encoder outputs. Time is embedded and injected through adaptive normalization or residual modulation. Class labels, camera parameters, masks, depth, or motion controls can use related adapters.
\nClassifier-free guidance combines conditional and unconditional predictions:
\n\nwhere denotes the chosen prediction target and is guidance strength. Guidance changes the vector field followed by the sampler. High guidance can improve prompt alignment while reducing diversity or causing saturation; the acceptable range is model- and sampler-specific.
\nBatching the conditional and unconditional passes can increase throughput but doubles some activation and conditioning work. Cache text embeddings when prompts repeat.
\nVideo tensors add frame count to spatial resolution, channel width, and batch size. Full spatiotemporal attention grows with the square of the token count. Architectures therefore factor spatial and temporal attention, use local windows, compress time in a latent autoencoder, or process temporal chunks.
\nTemporal consistency is not guaranteed by generating each frame with the same prompt. The model needs temporal operators or shared latent structure. Conditioning should preserve frame order, frame rate, aspect ratio, and camera metadata used during training.
\nA serving plan must choose:
\nTiled decoding lowers peak memory but can expose seams if receptive-field overlap and blending do not match the decoder.
\nAn ODE solver advances:
\n\nHigher-order methods evaluate the network at additional points to reduce integration error. Fewer steps reduce latency but can miss curved regions of the learned field. A solver qualified on one parameterization or schedule may be unstable on another.
\nBenchmark quality against network evaluation count, not loop iteration alone. Some iterations call the model more than once. Also report text-encoder and decoder time so denoiser optimizations are not overstated.
\n![\"A](\"https://blog.ecitis.org/feeds/figures/diffusion-flow-matching-1.webp\")
Time convention mismatch: Training uses noise-to-data time while the sampler assumes data-to-noise time. Endpoint tests catch the sign and schedule reversal.
\nTarget conversion mismatch: The model predicts velocity but guidance or solver code treats it as noise. Centralize conversions and record the checkpoint prediction type.
\nLatent scale mismatch: Encoder outputs are scaled during training but not inference. Compare training-pipeline latents with serving latents.
\nConditioning dropout mismatch: Classifier-free guidance requires an unconditional path trained with conditioning dropout. Replacing conditioning with arbitrary empty text can differ from the trained null condition.
\nVideo padding leakage: Padded frames participate in attention because the mask is wrong. Test variable-length batches against individually evaluated clips.
\nSampler benchmark bias: Quality is compared at equal step count despite different model evaluations. Compare equal evaluation budgets and wall-clock latency.
\nDiffusion and flow matching are not competing network brands. They are ways to specify a time-dependent learning target and a generative path. A production system must keep schedule, target parameterization, architecture, conditioning, latent codec, and sampler in one versioned contract.
\nProduction AI safety is a systems property. A model can refuse a prohibited request and still leak data through retrieval, call an overpowered tool, or emit malformed output that an application executes.
\nThe control plane must govern identity, data access, tool authority, output contracts, monitoring, and response. Model behavior remains one control inside that plane.
\nDraw the actual data path:
\nuser → gateway → context builder → model → tool broker → external systems\n ↓ ↓\n retrieval index audit logFor each boundary, record:
\nNIST’s Generative AI Profile organizes risk work around govern, map, measure, and manage functions and treats risk management as a lifecycle activity rather than a model-only test.1
\n![\"Safety](\"https://blog.ecitis.org/feeds/figures/ai-safety-systems-0.webp\")
A system prompt is input to a probabilistic model. It can influence behavior but cannot enforce database permissions or network access.
\nRepresent enforceable policy in code or a policy engine:
\ntype Action = {\n principal: string\n operation: 'read' | 'create' | 'update' | 'delete'\n resource: string\n attributes: Record<string, string>\n}\n\ntype PolicyDecision = {\n effect: 'allow' | 'deny' | 'require_approval'\n policyVersion: string\n reason: string\n}The prompt can tell the model not to delete records. The tool broker must deny deletion unless the authenticated principal, resource policy, and conversation approval allow it.
\nVersion policies independently from prompts. An incident review should identify the rule that allowed an action without reconstructing it from prose embedded in a model request.
\nTool definitions should map to narrow operations. A generic SQL executor or shell command carries more authority than a tool designed around one domain action.
\nPrefer:
\n{\n \"name\": \"create_refund_request\",\n \"input\": {\n \"invoice_id\": \"INV-1042\",\n \"reason_code\": \"DUPLICATE_CHARGE\"\n }\n}over:
\n{\n \"name\": \"run_command\",\n \"input\": {\n \"command\": \"refund --invoice INV-1042\"\n }\n}The values are illustrative. The narrow tool allows schema validation, resource-level authorization, idempotency, and a specific audit event.
\nCredentials should be scoped per tool service and deployment environment. Do not place a broad production credential in the model context. The model should select an operation; the broker should attach credentials after policy approval.
\nApproval must cover the action the system will execute. If the model changes a recipient, amount, repository, or destination after approval, request approval again.
\nfunction approvalFingerprint(tool: string, args: unknown, principal: string): string {\n return stableHash({ tool, args, principal })\n}The approval record should contain the fingerprint, policy version, user identity, timestamp, and rendered action summary. A generic session-wide approval grants authority to future model outputs that the user has not seen.
\nRead operations can also be sensitive. Searching personnel records or retrieving private source code requires access checks even when no state changes.
\n![\"Approval](\"https://blog.ecitis.org/feeds/figures/ai-safety-systems-1.webp\")
Prompt injection crosses a trust boundary when data is interpreted as instructions. Web pages, emails, documents, issue comments, and tool results can contain text that tells the model to ignore policy or exfiltrate context.
\nDo not rely on a delimiter to make instructions harmless. The model still reads both sides of the delimiter.
\nControls include:
\nIndirect injection becomes an incident only when the surrounding system gives the injected instruction a path to data or action. Remove that path with least privilege and approval.
\nBuild context from an explicit allowlist of fields. Passing complete records creates accidental exposure and makes later redaction harder.
\ntype TicketContext = {\n subject: string\n customerMessage: string\n publicProduct: string\n allowedPolicyExcerpts: string[]\n}Keep secrets out of prompts. If a tool needs an API credential, inject it inside the trusted tool process. Model-visible logs should redact authorization headers, session cookies, private keys, and personal data not needed for the task.
\nTenant isolation belongs in the query and storage layer. Filtering another tenant’s passages after retrieval already exposes them to rankers, caches, and traces.
\nInput validation protects services from malformed model-generated arguments. Output validation protects downstream consumers from malformed or policy-breaking model text.
\nUse a layered contract:
\ntype RefundRequest = {\n invoiceId: string\n reasonCode: 'DUPLICATE_CHARGE' | 'SERVICE_NOT_DELIVERED'\n}\n\nfunction validateRefund(request: RefundRequest, invoice: { id: string; state: string }): void {\n if (request.invoiceId !== invoice.id) throw new Error('invoice mismatch')\n if (invoice.state !== 'paid') throw new Error('invoice is not refundable')\n}A JSON Schema can prove that invoiceId is a string. It cannot prove that the invoice belongs to the principal or is refundable.
For generated code, parse before execution, run in an isolated environment, constrain network and filesystem access, set resource limits, and inspect artifacts. Text moderation does not replace a sandbox.
\nClassifiers can detect content categories, sensitive data, or policy-relevant intent. They should produce an operational route:
\nallow → normal pipeline\ntransform → redact or narrow context\nreview → human queue\nblock → safe response with reason codeMeasure false positives and false negatives on the deployed distribution. A classifier threshold is a policy choice with user and incident costs on both sides.
\nDo not let a classifier silently rewrite authority. A low-risk classification can reduce review but should not grant a tool permission that the principal lacks.
\nFor factual answers, preserve the link between claims and sources:
\nCitation presence alone is not grounding. Validate that the cited passage supports the claim and that the user can access the source.
\nFor actions, provenance means the chain from user request through model proposal, policy decision, approval, tool call, and verified result.
\nSafe failure is explicit:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Failure | System response |
|---|---|
| Retrieval unavailable | State that evidence could not be loaded |
| Policy service unavailable | Deny sensitive actions |
| Approval expired | Request a new approval |
| Output invalid | Repair within a bounded retry policy or stop |
| Tool result ambiguous | Do not claim success |
| Audit sink unavailable | Apply the declared fail-open or fail-closed policy |
A model-generated statement of success is not a tool postcondition. Read the authoritative system state before telling the user that an external action completed.
\nSingle-turn refusal tests cover only model behavior. System tests should exercise:
\nRecord the layer that blocked each test. A prompt-only defense that passes today can regress with a model update. An authorization denial should remain stable.
\nNIST recommends documented test plans, independent assessment where appropriate, incident disclosure processes, and ongoing monitoring for generative AI systems.1 Translate those controls into executable release gates and incident runbooks.
\nAudit records need enough detail for reconstruction:
\n{\n \"request_id\": \"req_91\",\n \"principal\": \"user_24\",\n \"policy_version\": \"tools-12\",\n \"tool\": \"create_refund_request\",\n \"decision\": \"require_approval\",\n \"approval_id\": \"approval_77\",\n \"result\": \"created\"\n}Identifiers and versions are illustrative.
\nDo not log full prompts by default when they contain private documents. Store encrypted artifacts with limited retention and access, or log hashes plus selected redacted fields. Test redaction on tool errors because exception text often includes request bodies.
\nAn AI incident runbook needs system controls:
\nChanging the system prompt is appropriate only when the failure was actually instructional. A cross-tenant retrieval bug needs a query and authorization fix.
\nSafety improves when authority is explicit and independently enforceable. The model proposes. Policy decides. Tools verify. Audit records preserve the evidence.
\nA context window is a capacity limit, not a guarantee that every supplied token affects the answer equally. Long-context systems combine positional representation, attention computation, device memory, distributed execution, data composition, and evaluation.
\nExtending one layer does not extend the others. A position encoding can represent a distant index while the cache does not fit. An exact attention kernel can process the sequence while the model fails to retrieve a fact placed in its middle.
\nTransformer attention without position is permutation-equivariant. Position methods change token representations or attention scores.
\nRotary position embedding applies a position-dependent rotation to query and key pairs. Their dot product then contains relative-position structure.1 For one two-dimensional feature pair:
\n\nThe model is trained over a range of phases determined by position and frequency . Extrapolating beyond the training range can expose phase patterns not learned during training.
\nALiBi takes a different route. It adds a head-specific linear penalty proportional to query-key distance rather than adding a positional embedding to token states.2 Its authors trained a -billion-parameter model at length and evaluated length ; they report matching the perplexity of a sinusoidal baseline trained at the longer length while using less training memory and time.2
\n![\"Long-context](\"https://blog.ecitis.org/feeds/figures/long-context-models-0.webp\")
Position interpolation compresses a longer inference range into coordinates observed during training. It avoids raw extrapolation but reduces angular resolution between nearby positions. Frequency-aware methods scale dimensions differently because high-frequency and low-frequency rotary pairs behave differently.
\nLongRoPE searches non-uniform interpolation factors and uses progressive extension. The paper reports extending models to thousand tokens with fine-tuning at lengths up to thousand tokens, then readjusting at thousand tokens to recover short-context behavior.3
\nThose figures describe the evaluated method, not a universal recipe. Extension factors depend on the base model, original training length, data, and fine-tuning setup. A configuration that loads successfully can still degrade short-context perplexity or retrieval.
\nStore position policy with the model artifact:
\nposition:\n type: rope\n original_max_positions: ${TRAINING_LIMIT}\n scaling:\n method: ${METHOD}\n factor: ${FACTOR}\n parameters_digest: ${DIGEST}\nevaluation:\n short_context_suite: ${SHORT_SUITE}\n long_context_suite: ${LONG_SUITE}Placeholders force values to come from the trained artifact rather than a copied deployment snippet.
\nExact self-attention score work grows with the product of query and key lengths. FlashAttention avoids materializing the complete score matrix but does not remove the arithmetic of dense attention.4
\nInference also retains the key-value cache. For layers, key-value heads, head dimension , sequence length , and scalar width :
\n\nThe cache grows linearly with sequence length. Prefix caching avoids recomputation across repeated prefixes but does not make a unique long sequence free. Quantized cache and grouped-query attention reduce bytes per token; both require model and kernel support.
\nBefore admitting a long request, estimate weight memory, cache reservation, temporary attention workspace, communication buffers, and allocator headroom. Token limits that ignore concurrent requests produce late out-of-memory failures.
\nWhen one device cannot hold sequence state, context parallelism partitions tokens across devices. Ring Attention rotates key-value blocks around a device ring and computes blockwise attention while communication overlaps with local work.5 Online softmax combines partial results without assembling the full score matrix on one device.
\nFor each local query block, a worker:
\nThe method preserves dense attention but adds communication proportional to the circulated state. Topology and link bandwidth become part of context-length capacity.
\nSparse methods avoid evaluating every token pair. Sliding windows preserve local structure but remove direct long-range edges. Global tokens, vertical stripes, and selected blocks restore some long-range access.
\nMInference identifies several sparse patterns per attention head and constructs dynamic sparse indices during prefill.6 Such methods accelerate a pattern observed in model attention; they do not preserve exact dense attention by definition.
\nValidate sparse kernels on tasks requiring distant dependencies, not only language-model loss. A local window can score well on locally predictable text while dropping a document-level constraint.
\nRetrieval selects a smaller evidence set before generation. Its cost shifts to indexing, query construction, ranking, and provenance. Long context and retrieval are complementary:
\nChunking is a semantic decision. Fixed token windows can split tables, code definitions, and cross-references. Structure-aware chunking keeps those units intact, while overlap preserves boundary context at the cost of duplicate tokens.
\nLiu and collaborators varied the position of relevant information within long inputs and observed that performance can be highest when relevant information is near the beginning or end and lower when it is in the middle.7 Their result motivates position sweeps rather than one fixed evidence placement.
\nA useful evaluation matrix crosses:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Axis | Values to cover |
|---|---|
| Evidence position | beginning, interior positions, end |
| Distractor count | low through deployment maximum |
| Evidence type | prose, table, code, cross-document link |
| Required operation | retrieval, aggregation, comparison, exact copy |
| Output contract | free text and structured result |
Every test should record tokenized length, evidence offsets, truncation, retrieved chunk identifiers, and model position configuration. Otherwise a failure cannot be assigned to retrieval, prompt construction, model use, or runtime truncation.
\nSilent truncation: the tokenizer or server drops tokens before model execution. Return accepted input length and truncation status in response metadata.
\nPosition-config mismatch: weights were tuned with one RoPE policy but served with another. Hash the position configuration into the engine identity.
\nCache admission failure: the request fits the advertised window alone but not under concurrency. Reserve cache before prefill.
\nMiddle-position regression: aggregate benchmark scores hide positional weakness. Report accuracy by evidence offset.
\nSparse-index error: a required block is omitted by an indexing heuristic. Maintain a dense reference path for reduced test cases.
\nRetrieval dilution: adding lower-ranked chunks moves useful evidence farther apart and adds distractors. Evaluate answer quality as the retrieved-token budget changes.
\nUse position extension when the model must represent indices beyond training and can be fine-tuned and re-evaluated. Use optimized dense attention when exact all-to-all access is required. Use sparse attention when model quality survives a restricted edge pattern. Use context parallelism when exact attention state exceeds one device. Use retrieval when only a subset of an external corpus is relevant to each request.
\nThese decisions compose. A production system can retrieve documents, serve an extended-RoPE model, run tiled attention, shard context across devices, and page its cache. Each layer needs a separate measurement and failure boundary.
\nLong context becomes useful only when evidence survives tokenization, placement, attention, memory admission, and decoding. The maximum accepted token count measures just the first of those requirements.
\nJianlin Su et al., “RoFormer: Enhanced Transformer with Rotary Position Embedding,” Neurocomputing, 2024. https://arxiv.org/abs/2104.09864 ↩
\nOfir Press, Noah A. Smith, and Mike Lewis, “Train Short, Test Long: Attention with Linear Biases Enables Input Length Extrapolation,” ICLR, 2022. https://arxiv.org/abs/2108.12409 ↩ ↩2
\nYiran Ding et al., “LongRoPE: Extending LLM Context Window Beyond 2 Million Tokens,” ICML, 2024. https://arxiv.org/abs/2402.13753 ↩
\nTri Dao et al., “FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness,” NeurIPS, 2022. https://arxiv.org/abs/2205.14135 ↩
\nHao Liu et al., “Ring Attention with Blockwise Transformers for Near-Infinite Context,” ICLR, 2024. https://arxiv.org/abs/2310.01889 ↩
\nHuiqiang Jiang et al., “MInference 1.0: Accelerating Pre-filling for Long-Context LLMs via Dynamic Sparse Attention,” NeurIPS, 2024. https://arxiv.org/abs/2407.02490 ↩
\nNelson F. Liu et al., “Lost in the Middle: How Language Models Use Long Contexts,” TACL, 2024. https://arxiv.org/abs/2307.03172 ↩
\nSynthetic data is a software artifact with lineage. A production pipeline must be able to answer which seed, prompt template, generator, sampling configuration, validator, and policy produced every accepted record. Without that chain, a high-scoring training run cannot be reproduced or audited.
\n![\"Synthetic](\"https://blog.ecitis.org/feeds/figures/synthetic-data-pipelines-0.webp\")
Generation should fill a documented coverage gap. Start with a taxonomy of task, language, domain, difficulty, input form, and expected output form. Assign each candidate to that taxonomy before accepting it.
\nA record envelope can preserve the minimum lineage:
\n{\n \"record_id\": \"content-addressed-id\",\n \"seed_id\": \"source-record-id\",\n \"task\": \"tool_argument_generation\",\n \"generator\": {\n \"model\": \"pinned-model-revision\",\n \"template\": \"template-content-hash\",\n \"sampling\": \"serialized-sampling-config\"\n },\n \"candidate\": {\n \"prompt\": \"generated prompt\",\n \"response\": \"generated response\"\n },\n \"validation\": [],\n \"decision\": \"pending\"\n}Do not use an editable model alias or prompt filename as provenance. Store immutable revisions and content hashes.
\nSelf-Instruct starts from seed tasks, generates new instructions and instances, filters invalid or similar outputs, then uses accepted examples for instruction tuning.1 The mechanism amplifies a seed distribution. It does not create an unbiased sample of every task users will request.
\nSeed preparation should include:
\nSplit by source group before generation. If variants of one seed land in training and evaluation, the evaluation measures template transfer rather than independent generalization.
\nPrompt templates can request variations in task structure, constraints, domain, or reasoning requirement. Sampling adds lexical and solution diversity. Both can also produce invalid examples.
\nGenerate multiple candidates per seed only when a validator can distinguish them. Otherwise the pipeline increases volume without evidence of quality. Preserve rejected candidates and reasons so generator changes can be compared on the same acceptance criteria.
\nStructured tasks should use structured generation:
\nfrom dataclasses import dataclass\n\n@dataclass\nclass Candidate:\n instruction: str\n input: str\n output: str\n assumptions: list[str]\n source_ids: list[str]A schema verifies form, not truth. It prevents missing fields and malformed types from entering later stages.
\nA generator grading its own answer repeats correlated errors. Prefer validators that obtain evidence through a different mechanism.
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Task | Strong validator | Weak validator |
|---|---|---|
| Code generation | compile, tests, static analysis | generator self-rating |
| Structured extraction | schema plus comparison to source | fluent explanation |
| Mathematics | symbolic check or alternate derivation | answer-format match |
| Retrieval question | entailment against cited passages | uncited judge score |
| Tool calls | schema plus sandbox execution | syntactic JSON only |
Execution validators need containment. Run generated code with resource limits, no ambient credentials, restricted networking, and disposable storage. Record exit status and test output, but sanitize untrusted content before displaying it in internal tools.
\nFor open-ended responses, use a rubric with observable failure labels such as unsupported claim, missing constraint, contradiction, unsafe instruction, or non-answer. Calibrate model-based judges against a human-reviewed sample and recheck calibration when the generator or domain changes.
\nExact hashing removes byte-identical records. Normalized hashing can ignore formatting, case, or boilerplate. Semantic similarity catches paraphrases, but thresholds depend on the embedding model and domain.
\nDeduplication has two distinct objectives:
\nThe second objective needs lineage-aware checks. A generated prompt can be lexically distant from its seed while preserving the same answer structure. Group descendants with their seed during split assignment.
\nStore cluster identifiers and representative records. Deleting duplicates without a manifest makes future dataset diffs difficult to explain.
\nDifficulty labels produced only by a generator are unstable. Prefer signals tied to the task:
\nDo not equate longer chain-of-thought text with harder reasoning. A verbose candidate can contain redundant or fabricated steps. If reasoning traces are used for training, validate the final answer and inspect step consistency with tools where the domain permits it.
\nA synthetic pipeline can train on solutions without exposing raw reasoning at inference. Separate outcome supervision, concise rationales, tool traces, and hidden scratch work as distinct fields. The serving format should not inherit the generator’s internal trace by accident.
\nFor tool use, a compact trace is often more useful:
\nrequest\ntool schema selected\nvalidated arguments\ntool result reference\nfinal answer grounded in resultThis structure is auditable and maps to runtime behavior.
\nTraining repeatedly on model-generated distributions can reduce coverage of low-probability events and propagate generator errors. A synthetic corpus therefore needs real-data anchors, independent evaluation, and explicit mixture weights. Synthetic examples should address measured gaps rather than replace the entire observed distribution.
\nTrack acceptance and performance by source type. If synthetic data improves aggregate accuracy while reducing performance on a real-data slice, the aggregate result is insufficient.
\nThe evaluation set must not be generated by the same templates, seeds, and model revision used for training. Include:
\nFLAN work showed that scaling instruction-finetuning tasks and using chain-of-thought data can improve model behavior across evaluation families.2 That result supports task diversity as a training variable. It does not validate any arbitrary synthetic dataset, so each pipeline still needs its own ablations.
\nRun mixture ablations rather than comparing only no-synthetic versus all-synthetic. Change one factor at a time: seed source, generator revision, filtering stage, or mixture weight.
\nA dataset release should contain:
\nTreat validator changes like code changes. Rebuild from immutable candidates, diff accepted record IDs, and investigate large movements. A judge prompt edit can alter the training distribution even when generation is unchanged.
\nValidator leakage: The generator learns the tests or rubric and produces outputs tailored to them. Keep hidden checks and rotate surface forms without changing the criterion.
\nHomogeneous style: One generator and template create repeated syntax. Measure lexical and structural diversity, then introduce source or template diversity with unchanged validation.
\nFalse authority: Candidates include citations that look valid but do not support the claim. Fetch the cited primary source and verify entailment, or reject the citation.
\nSplit contamination: Derived examples cross seed-group boundaries. Assign the split at the ancestor seed and inherit it through every transformation.
\nSilent policy drift: A hosted generator changes behind an alias. Pin a revision when possible and retain probe outputs that identify behavior changes.
\nSynthetic data quality comes from the rejection path as much as the generator. The durable pipeline preserves provenance, validates with independent evidence, deduplicates by lineage, anchors evaluation in real data, and makes every accepted record reproducible.
\nAn evaluation is a measurement procedure, not a prompt file. Its result depends on the dataset, harness, model configuration, scorer, aggregation, and statistical analysis. Changing any one of them changes the object being measured.
\nThis matters for language-model systems because the model is only one component. Retrieval, tools, policy prompts, sampling parameters, and output parsers can determine whether the same model succeeds or fails.
\nStart with the release decision:
\ndecision: replace current support-answering model\npopulation: authenticated English support questions\nconstraints:\n - no regression on policy compliance\n - bounded p95 response latency\n - bounded cost per resolved conversation\noutcomes:\n - correct resolution\n - unsupported claim rate\n - escalation rateThe numeric thresholds are product choices and therefore omitted from this example. A benchmark score that does not connect to the decision is diagnostic evidence, not a release gate.
\nHELM argues for broad scenario coverage and simultaneous measurement of accuracy, robustness, calibration, fairness, bias, toxicity, and efficiency rather than a single model score.1 The exact dimensions should follow the deployed task.
\nRandom production samples reproduce the traffic distribution but can miss rare, costly failures. Handwritten challenge sets cover known hazards but distort prevalence. Use both and report them separately.
\nA case should contain:
\ntype EvalCase = {\n id: string\n input: unknown\n expected?: unknown\n rubric?: string\n tags: string[]\n source: 'production' | 'expert' | 'incident' | 'synthetic'\n provenance: string\n createdAt: string\n}Tags enable slices such as language, tool, document type, ambiguity, policy class, and input length. Provenance supports contamination audits and rights review.
\nFreeze a release suite. Add new incident cases to a forward-looking suite so repeated tuning does not quietly overfit the current gate.
\n![\"Evaluation](\"https://blog.ecitis.org/feeds/figures/llm-evaluation-0.webp\")
The harness includes every transformation between a case and its score:
\nRecord the rendered request rather than only the prompt template. A misplaced separator, reordered choice list, or truncated tool result can alter the outcome.
\n{\n \"case_id\": \"billing-policy-017\",\n \"suite_revision\": \"support-v4\",\n \"model\": \"candidate-build\",\n \"prompt_sha256\": \"…\",\n \"toolset_revision\": \"support-tools-v7\",\n \"retrieval_revision\": \"kb-2026-05-18\",\n \"sampler\": { \"temperature\": 0 },\n \"raw_output_uri\": \"artifact://run/case/output\"\n}Version names above are illustrative.
\nUse deterministic checks when the task has an executable contract:
\nDeterministic scorers expose why a case failed and can be rerun without model variance. They do not measure open-ended quality, but they should handle every property that can be specified mechanically.
\nFor partial-credit tasks, define components:
\n\nWeights encode a product judgment. Publish them with the results and report component scores so one weighted total does not hide a safety regression.
\nHuman ratings are not ground truth by default. Raters need:
\nMeasure agreement and inspect disagreements. Low agreement can indicate an ambiguous rubric, insufficient evidence, or a task with legitimate preference variation.
\nPairwise comparison is often easier than an absolute scale: show two outputs for the same input and ask which better satisfies the rubric. Randomize left and right positions, then include ties when the difference is not material.
\nModel-based scoring enables larger evaluation sets, but it introduces a second model whose behavior must be validated.
\nThe MT-Bench and Chatbot Arena paper compared model judges with human preferences and documented position, verbosity, and self-enhancement biases.2 A judge can therefore reward presentation features unrelated to task correctness.
\nMitigations are measurable:
\nscore(A, B) + score(B, A) → stable preference or disagreementDo not ask a judge for hidden chain-of-thought. Request a short evidence field tied to rubric criteria, then audit whether that evidence matches the outputs.
\nJudge agreement with humans should be reported on the target task, not borrowed from another benchmark. A judge calibrated for concise customer support answers may fail on mathematical proofs or code patches.
\n![\"Order](\"https://blog.ecitis.org/feeds/figures/llm-evaluation-1.webp\")
Benchmark contamination occurs when evaluation material or close derivatives enter training, fine-tuning, retrieval corpora, prompt libraries, or manual development loops. A high score can then measure recall of the benchmark rather than task generalization.
\nContamination is not limited to exact duplicates. Paraphrased questions, published solutions, answer keys, and benchmark-specific explanations can leak the intended mapping.
\nMitigations include:
\nBlack-box detection is uncertain. The Min-K% Prob method tests whether a text contains unusually low-probability tokens and was evaluated for pretraining-data detection on a time-split benchmark.3 It is evidence, not proof of membership. A current evaluation should describe the audit performed and residual uncertainty.
\nDynamic cases reduce exposure. Generate them from controlled templates with executable answers, then validate the generator. Do not call generated cases uncontaminated merely because their final strings are new; the underlying task pattern may still be familiar.
\nA score without uncertainty encourages false precision. For a binary metric with independent cases and empirical success rate , a simple standard error estimate is:
\n\nBootstrap intervals are more flexible for non-linear metrics and sliced data. For model comparisons, use paired resampling because both models run on the same cases.
\nReport:
\nDo not remove timeouts from the denominator unless the release decision also ignores timeouts.
\nOffline cases are controlled and replayable. Production metrics observe the real distribution and real users. Neither replaces the other.
\nUseful system metrics include:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Layer | Measurements |
|---|---|
| Request | eligible volume, language, intent, input length |
| Model | latency, token usage, refusal, malformed output |
| Retrieval | empty results, evidence coverage, stale index |
| Tools | call success, invalid arguments, approval, rollback |
| Outcome | resolution, correction, escalation, abandonment |
| Safety | policy blocks, confirmed incidents, reviewer reversals |
User clicks and thumbs ratings are behavior signals, not direct correctness labels. A user can accept a plausible wrong answer or downvote a correct refusal. Combine behavioral metrics with audited samples.
\nFor online experiments, define guardrails before launch and preserve assignment logs. Model changes can alter cost, latency, and escalation while leaving average answer ratings unchanged.
\nDrift can occur in inputs, retrieved knowledge, tool behavior, policy, or user expectations. Track slice proportions and score distributions over time.
\nTrigger a review when:
\nAn evaluation suite is versioned software. Changes need review, changelogs, reproducible artifacts, and migration notes.
\nCorrect evidence absent: retrieval failure.
\nCorrect evidence present, answer unsupported: generation or instruction failure.
\nValid action selected with wrong arguments: tool-planning or schema failure.
\nCorrect output marked wrong: scorer or rubric failure.
\nOffline pass with production regression: population, harness, or outcome mismatch.
\nStore raw inputs, outputs, tool traces, scorer decisions, and policy versions so these categories can be tested rather than guessed.
\nA useful report states:
\nThe report should make rerunning the evaluation possible. A leaderboard number without cases, harness, and scoring details cannot support a production decision.
\nLiang et al., “Holistic Evaluation of Language Models,” Transactions on Machine Learning Research, 2023. ↩
\nZheng et al., “Judging LLM-as-a-Judge with MT-Bench and Chatbot Arena,” NeurIPS Datasets and Benchmarks, 2023. ↩
\nShi et al., “Detecting Pretraining Data from Large Language Models,” ICLR, 2024. ↩
\nAn on-device multimodal model is a scheduling problem over shared memory. Camera buffers, audio capture, encoders, language-model weights, KV cache, and UI surfaces compete for the same physical resources. A model that fits at rest can still fail when an encoder and decoder reach peak allocation together.
\n![\"A](\"https://blog.ecitis.org/feeds/figures/on-device-multimodal-ai-0.webp\")
A useful budget separates persistent and transient allocations:
\n\nWeight-file size is not peak memory. Runtimes can unpack weights, allocate graph plans, retain caches, and copy buffers between CPU and accelerator address spaces. The operating system also needs headroom for the camera, microphone, display compositor, and the rest of the application.
\nInstrument resident memory and accelerator allocations around each phase:
\nload language model\nload vision encoder\nencode image\nrelease vision workspace\nappend visual tokens\nload or activate audio encoder\nencode audio window\nrelease audio workspace\ndecode textSerial encoder scheduling lowers peak concurrency when the application does not need simultaneous frame and audio processing. The cost is latency. Measure the user-visible critical path before selecting concurrency.
\nA vision encoder maps image patches or feature maps into embeddings. An adapter projects those embeddings into the language model’s hidden space. A speech encoder performs a related conversion over acoustic frames. The language model then consumes an interleaved token sequence containing text and modality embeddings.
\nGemma 3n provides a concrete mobile architecture: it combines text with image, video, and audio inputs, uses a MobileNet-V5 vision encoder, and derives its audio encoder from Universal Speech Model work.1 Google’s implementation reports one audio token per milliseconds and offers image input resolutions of , , and pixels.1 Those are model-specific interface facts, not defaults for all multimodal systems.
\nMedia preprocessing must match training:
\nAn apparently plausible response does not prove preprocessing is correct. Validate embeddings or logits against a reference runtime with fixed media fixtures.
\nThe language model sees encoder outputs as tokens. More image tiles, video frames, or audio windows extend the prefill sequence. KV cache memory for an autoregressive decoder grows with retained sequence length:
\n\nHere is cached layer count, is sequence length, is the cached key-value width, and is bytes per stored element. Grouped-query or multi-query attention changes by sharing key-value heads. Quantized cache storage changes but adds conversion and accuracy considerations.
\nGemma 3n documents KV cache sharing in which middle-layer key and value representations are shared with upper layers to reduce prefill work.1 That is an architectural optimization built into the model. A runtime cannot apply it to an arbitrary checkpoint without matching training and graph structure.
\nSet modality budgets before preprocessing:
\ndata class RequestBudget(\n val maxImageTokens: Int,\n val maxAudioTokens: Int,\n val maxTextTokens: Int,\n val maxOutputTokens: Int,\n)\n\nfun validate(b: RequestBudget, contextLimit: Int) {\n require(\n b.maxImageTokens +\n b.maxAudioTokens +\n b.maxTextTokens +\n b.maxOutputTokens <= contextLimit\n )\n}The application should reject or downsample input before allocating an oversized cache.
\nVideo is not one large image. It is a sequence of frames with temporal redundancy. Feeding every captured frame wastes encoder work and context. Define a policy based on the task:
\nRetain timestamps and orientation metadata. If visual tokens from multiple frames are concatenated without temporal markers, the language model cannot reliably infer capture order from pixels alone.
\nCamera images often arrive in a hardware-native pixel format. Converting full-resolution frames on the CPU can become the bottleneck before inference begins. Prefer runtime-supported texture or buffer paths, and crop or resize before expensive format conversion when the APIs permit it.
\nAudio capture produces a continuous stream while language-model decoding is bursty. A bounded ring buffer separates the two schedules. The encoder consumes windows with overlap or streaming state, then emits tokens or transcript segments.
\nGoogle describes the Gemma 3n audio encoder as streaming-capable, while its launch implementation accepts clips up to seconds.1 That limit belongs to the released implementation. Long-form support requires the runtime and model training needed to preserve streaming state.
\nFor a speech request, track:
\nVoice activity detection saves encoder and language-model work, but a false endpoint can cut a word or reset context. Keep the raw audio window needed to reproduce failures, subject to the product’s privacy policy.
\nMobile systems may expose CPU, GPU, neural accelerator, or vendor delegate paths. One model can span them, but every boundary risks a copy or synchronization. A placement plan should use measured operator coverage:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Subgraph | Placement question |
|---|---|
| Vision encoder | Does the delegate support its convolution and attention blocks without fallback? |
| Audio frontend | Is feature extraction cheaper on vector CPU code than through accelerator dispatch? |
| Language prefill | Which backend sustains the matrix shapes produced by media tokens? |
| Token decode | Which backend gives low latency at a small batch? |
An unsupported operator in the middle of an accelerator graph can force partitioning and transfers. Inspect the compiled delegate graph rather than relying on an API call that reports delegate initialization.
\nWeight quantization reduces resident model memory. Activation quantization can reduce bandwidth and accelerator requirements. It can also alter small embedding differences at modality adapters or attention logits.
\nEvaluate text-only, image-only, audio-only, and interleaved inputs separately. Include:
\nCompare task metrics and intermediate outputs where possible. A single language benchmark cannot qualify a multimodal quantization.
\nShort benchmark runs do not show sustained device behavior. Heat can reduce clock frequency and make a formerly valid real-time policy fall behind. Run capture, encoding, and decoding together for the expected session length. Record throughput, latency, temperature or platform thermal state, and battery or power telemetry exposed by the device.
\nDegradation should be explicit:
\nGemma 3n uses MatFormer nesting and per-layer embeddings so its released variants can operate with active memory footprints associated with smaller nested models.2 That capability depends on its architecture. Other models need separate checkpoints or different elastic mechanisms.
\nLocal inference does not prove that media stays local. Crash reporters, analytics payloads, debug logging, model downloads, and remote fallbacks can transmit derived or raw data. Document every boundary and make fallback behavior visible to the user.
\nEncrypt cached media if it must persist. Prefer ephemeral buffers. Strip prompt and media content from default logs. Verify that application lifecycle transitions release microphone and camera access. Test airplane-mode operation if offline behavior is a requirement.
\nOn-device multimodal design starts with a peak-memory timeline and a token budget. Encoders compress media into language-model inputs, but those inputs still consume prefill time and KV cache. The reliable implementation schedules encoders deliberately, validates preprocessing against a reference, measures delegate coverage, and reduces work predictably under thermal or memory pressure.
\nA retrieval system has a narrower job than a language model: given a query, return evidence that satisfies an information need. That boundary makes retrieval measurable. Documents can be judged for relevance before generation is introduced, and failures can be assigned to indexing, candidate generation, ranking, context construction, or answer synthesis.
\nBasic retrieval-augmented generation often collapses those stages into one embedding search. Production retrieval needs more structure because identifiers, exact phrases, concepts, freshness, access control, and document quality are different ranking signals.
\nChunking defines the unit the ranker can return. A chunk that spans unrelated sections produces an embedding with mixed semantics. A chunk that is too narrow can omit the qualifier needed to interpret a match.
\nUse structural boundaries before token counts:
\ntype Passage = {\n id: string\n documentId: string\n headingPath: string[]\n body: string\n updatedAt: string\n acl: string[]\n}\n\nfunction passageText(passage: Passage): string {\n return [...passage.headingPath, passage.body].join('\\n')\n}The heading path gives a dense encoder and lexical index the local subject. The document identifier supports deduplication after ranking. The access-control field allows filtering before any passage enters the candidate set.
\nStore provenance that survives every stage:
\nWithout a revision identifier, an answer citation can point at content that changed after retrieval.
\nBM25 ranks documents using query term frequency, inverse document frequency, and length normalization. A common form is:
\n\nHere, is the frequency of term in document . The parameters and control term saturation and length normalization. They are tuning parameters, not universal constants.
\nLexical retrieval is valuable for error codes, function names, chemical symbols, product identifiers, and quoted policy language. An embedding model can place semantically related text nearby while missing the exact token sequence that establishes relevance.
\nNormalize carefully. Lowercasing may suit prose but can damage case-sensitive identifiers. Stemming can improve recall for natural language and corrupt source-code terms. Maintain field-specific analyzers instead of applying one text pipeline to every field.
\nA bi-encoder maps the query and passage independently:
\n\nThe index retrieves passages with high cosine similarity or inner product. Independent encoding makes corpus vectors reusable, which is why dense retrieval works as a candidate generator.
\nDense retrieval inherits the encoder’s training distribution. The BEIR benchmark evaluated lexical, sparse, dense, late-interaction, and reranking systems across 18 datasets; its results found BM25 to be a robust baseline and showed that reranking and late interaction performed best on average in zero-shot settings, with higher computational cost.1
\nThat result argues against replacing lexical search by default. It supports evaluating multiple retriever families on the target corpus.
\nLexical and dense scores are usually not calibrated to the same range. Adding raw scores allows whichever system has the wider numeric distribution to dominate.
\nReciprocal Rank Fusion combines positions instead:
\n\nThe original RRF study compared fusion methods and reported that reciprocal rank fusion outperformed the tested Condorcet and individual learning-to-rank approaches.2 The constant controls how sharply the formula rewards the top positions and should be selected on validation queries.
\ntype Ranked = { id: string; rank: number }\n\nfunction rrf(lists: Ranked[][], rankConstant: number): Map<string, number> {\n const scores = new Map<string, number>()\n for (const list of lists) {\n for (const hit of list) {\n scores.set(hit.id, (scores.get(hit.id) ?? 0) + 1 / (rankConstant + hit.rank))\n }\n }\n return scores\n}The candidate depth for each ranker is an operational control. A deeper pool raises recall and increases fusion, filtering, and reranking work.
\n![\"Candidate](\"https://blog.ecitis.org/feeds/figures/retrieval-systems-0.webp\")
A cross-encoder reads the query and candidate passage together. Joint attention can inspect exact query-passage interactions that a bi-encoder compresses into separate vectors.
\nThe architecture separates jobs:
\nTraining data must resemble the candidate distribution at inference. HYRR trains rerankers on candidates from a hybrid lexical and dense retriever and reports robustness across first-stage retrieval systems on supervised and zero-shot passage tasks.3
\nReranking every document defeats the purpose. Its latency should scale with the candidate pool, not corpus size. Batch query-passage pairs on accelerators and log queue time separately from model execution.
\nLate-interaction systems encode query and document tokens independently, then aggregate token-level similarities. They occupy a point between bi-encoders and cross-encoders:
\nThis architecture is useful when a single passage contains several concepts and relevance depends on multiple local matches. It also complicates index storage and serving. Measure end-to-end latency at realistic corpus size rather than comparing model forward passes alone.
\nQuery rewriting can expand acronyms, resolve conversational references, or create alternate lexical forms. It can also remove a rare identifier that carried the user’s actual intent.
\nPreserve the original query as one branch:
\noriginal query ───────────────› lexical retrieval\n ├── normalized query ──› dense retrieval\n └── generated variant ─› optional retrieval branchHyDE generates a hypothetical document, embeds it, and retrieves nearby real documents. The paper explicitly notes that the generated document is unreal and may contain false details; the corpus search provides the grounding step.4 A generated query or hypothetical document must never be presented as evidence.
\nMetadata filtering is part of retrieval correctness. Tenant, repository, geography, retention class, and authorization constraints should restrict candidates before content reaches the model.
\nDo not retrieve globally and remove unauthorized passages after reranking. That design leaks protected content into ranker inputs, traces, caches, and timing behavior.
\nFreshness is also domain-specific. A recent changelog can outrank an older overview for a current-version query. A historical audit may require the opposite. Encode freshness as an explicit feature controlled by query intent rather than a global recency boost.
\nFor a query with a set of relevant passages, common metrics answer different questions:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Metric | Question |
|---|---|
| Recall at | Did the candidate set contain relevant evidence? |
| Precision at | How much of the returned set was relevant? |
| Mean reciprocal rank | How early was the first relevant result? |
| nDCG at | Did graded relevance appear in a useful order? |
For binary relevance:
\n\nUse passage-level labels for candidate and reranker evaluation, then add answer-level evaluation separately. If answer quality falls while retrieval metrics remain stable, inspect context ordering, citation binding, and generation.
\nEvaluation queries should be grouped by failure-sensitive slices:
\nReport confidence intervals or paired tests when comparing rankers. A single aggregate can hide a regression on exact-match queries behind a gain on semantic questions.
\nThe top-ranked passages are not automatically the best prompt. Near-duplicate chunks waste tokens. Several passages from one document can crowd out independent evidence. The relevant span can be buried inside a long passage.
\nA context builder should:
\nLong context does not remove this requirement. The Lost in the Middle study found that model performance can change with the position of relevant information and often declines when evidence appears in the middle of a long input.5
\n![\"Context](\"https://blog.ecitis.org/feeds/figures/retrieval-systems-1.webp\")
Trace each stage with the query and corpus versions needed for replay:
\n{\n \"query_id\": \"q_7f3\",\n \"index_revision\": \"docs-2026-04-26\",\n \"lexical_ms\": 12,\n \"dense_ms\": 19,\n \"fusion_candidates\": 80,\n \"rerank_ms\": 37,\n \"selected_passages\": 6\n}The values above illustrate a trace schema, not a performance target.
\nMonitor:
\nRelevant passage absent from all candidates: inspect parsing, analyzers, embeddings, filters, and candidate depth.
\nRelevant passage retrieved but ranked low: inspect fusion, reranker training distribution, and query features.
\nRelevant passage ranks high but is omitted from the prompt: inspect deduplication and context-budget logic.
\nEvidence appears in the prompt but the answer is wrong: inspect ordering, answer instructions, citation binding, and model capability.
\nOffline relevance improves while production outcomes fall: inspect query distribution drift, latency, permissions, and the difference between relevance labels and the user outcome.
\nA retrieval stack earns complexity only when each added stage moves a defined metric on representative queries. Hybrid retrieval, reranking, and context construction are separable controls. That separation makes the system faster to debug and harder to fool with one attractive aggregate score.
\nThakur et al., “BEIR: A Heterogeneous Benchmark for Zero-shot Evaluation of Information Retrieval Models,” NeurIPS Datasets and Benchmarks, 2021. ↩
\nCormack, Clarke, and Buettcher, “Reciprocal Rank Fusion Outperforms Condorcet and Individual Rank Learning Methods,” SIGIR, 2009. ↩
\nLu et al., “HYRR: Hybrid Infused Reranking for Passage Retrieval,” 2022. ↩
\nGao et al., “Precise Zero-Shot Dense Retrieval without Relevance Labels,” ACL, 2023. ↩
\nLiu et al., “Lost in the Middle: How Language Models Use Long Contexts,” Transactions of the Association for Computational Linguistics, 2024. ↩
\nLarge-model training is a placement problem before it is an optimizer problem. Parameters, optimizer state, gradients, activations, and temporary buffers must fit across devices. The selected placement also determines which bytes cross links on every step.
\n![\"What](\"https://blog.ecitis.org/feeds/figures/distributed-llm-training-0.webp\")
For parameter count , bytes per parameter , gradient bytes , and optimizer-state bytes , persistent training state is approximately:
\n\nActivations, communication buffers, allocator fragmentation, and kernel workspaces sit on top. Mixed precision does not imply that every term uses the same dtype. Many training stacks retain higher-precision master weights or optimizer statistics.
\nParallelism changes which terms each rank owns. It also introduces communication. A valid strategy must satisfy both device capacity and step-time constraints.
\nEach data-parallel rank holds the model and processes a different microbatch. Gradients are combined, commonly with all-reduce. With global batch , data-parallel degree , and local batch :
\n\nThe arithmetic per sample is unchanged. Communication scales with gradient state rather than activation size. This makes data parallelism attractive while a full training replica fits.
\nGradient accumulation decouples microbatch size from the optimizer batch. It reduces activation residency per forward pass but does not reduce the parameter or optimizer footprint.
\nFully sharded data parallel methods partition parameters, gradients, and optimizer state across the data-parallel group, gathering parameter shards when a layer executes and discarding or resharding them afterward. ZeRO introduced staged partitioning of optimizer state, gradients, and parameters to remove data-parallel memory redundancy.1
\nFailure modes include:
\nTensor parallelism splits a matrix multiplication across devices. For a linear layer , column partitioning divides by output features:
\n\nEach rank computes . The result is sharded along its feature dimension. A later row-parallel layer can consume those shards and reduce partial outputs. Megatron-LM arranged column- and row-parallel transformer operators to limit synchronization points while preserving dense matrix multiplications.2
\nTensor parallelism reduces per-rank parameter and compute load, but introduces collectives inside every transformer layer. It belongs within the fastest network domain available. Crossing a slow inter-node boundary for each layer can dominate step time.
\nSequence parallelism complements tensor parallelism by sharding operations whose activations would otherwise remain replicated across the sequence axis. It targets activation memory, not just parameter memory.
\nCheck tensor-parallel configurations for:
\nPipeline parallelism assigns consecutive layer ranges to stages. A minibatch is divided into microbatches so stages can work concurrently. GPipe formalized this approach with microbatch pipelining and rematerialization for large networks.3
\nAn all-forward-then-all-backward schedule has simple dependencies but retains activations for many microbatches. A one-forward-one-backward schedule starts backward work earlier and reduces the number of live activations. Interleaved schedules assign multiple model chunks to a physical stage to reduce idle periods, at the cost of more transfers and scheduling complexity.
\nPipeline efficiency depends on balance. Equal layer counts do not imply equal stage times because embedding, attention, mixture-of-experts, and output layers have different compute and memory profiles. Measure stage latency and move whole blocks or split points based on traces.
\nThe pipeline boundary transmits activations in the forward direction and their gradients in the reverse direction. A boundary at a wide hidden representation consumes more bandwidth than one after a compact projection.
\nOperational failures include a last stage slowed by vocabulary projection, microbatch count too small to fill the pipeline, activation checkpointing that recomputes across a communication boundary, and batches with different sequence lengths producing stage imbalance.
\n![\"Pipeline](\"https://blog.ecitis.org/feeds/figures/distributed-llm-training-1.webp\")
A mixture-of-experts layer routes each token to selected expert networks. Expert parallelism places different experts on different ranks. Tokens are exchanged so each expert receives its assigned inputs, then returned to their original sequence positions.
\nSwitch Transformers demonstrated sparse expert routing in which only selected parameters execute for a token.4 The memory benefit is conditional capacity: total parameters can grow without executing every expert for every token. The systems cost is token dispatch, usually implemented with all-to-all communication.
\nLoad balance is not guaranteed. A router can send too many tokens to a subset of experts. Capacity limits, auxiliary balancing losses, token dropping policies, and expert replication change quality and throughput. Each must be logged, not hidden behind an average utilization number.
\nMeasure per expert:
\nProduction training combines dimensions. Let , , , and denote data, tensor, pipeline, and expert parallel degrees. The world size is often factored as:
\n\nThis equation is a process-grid description, not proof that a configuration is efficient. Some implementations share or nest groups differently.
\nMap frequent, latency-sensitive collectives to fast links. Tensor-parallel collectives occur inside layers, so they usually remain within a tightly connected node. Data-parallel reductions occur on gradients and can span nodes with bucketed overlap. Pipeline traffic is point-to-point between adjacent stages. Expert dispatch is all-to-all and needs special attention to oversubscribed network fabrics.
\nOne reasonable placement order is:
\nThe order is a design procedure, not a universal optimum. Profile the actual architecture and cluster.
\nA distributed checkpoint is not merely a set of files. It records how tensors are partitioned. Changing the tensor-parallel degree requires resharding matrix dimensions. Changing pipeline degree moves layer ownership. Expert changes alter expert identifiers and routing state. Optimizer state must follow the same transformations as its parameter.
\nStore:
\nTest restore under the same topology before testing topology conversion. Compare loss on a fixed batch before and after restoration.
\nparallelism:\n data: ${DATA_PARALLEL_DEGREE}\n tensor: ${TENSOR_PARALLEL_DEGREE}\n pipeline: ${PIPELINE_PARALLEL_DEGREE}\n expert: ${EXPERT_PARALLEL_DEGREE}\n\nschedule:\n microbatches: ${MICROBATCH_COUNT}\n activation_checkpointing: selective\n\ncheckpoint:\n format: distributed\n save_rng_state: true\n save_data_position: trueConfiguration validation should reject incompatible hidden widths, attention heads, expert counts, and world sizes before processes initialize.
\nCollective duration alone does not show the performance cost. Communication overlapped with useful compute is cheaper than an equally long collective on the critical path. Use a timeline and calculate exposed communication:
\n\nAlso report tokens processed per unit time, model FLOP utilization under a documented accounting convention, peak allocated memory per rank, and straggler spread. An aggregate average can conceal one stage that limits the complete pipeline.
\nDistributed training succeeds when partitioning, scheduling, and topology agree. Data parallelism distributes samples, tensor parallelism distributes operators, pipeline parallelism distributes layers, and expert parallelism distributes conditional modules. Their communication patterns are different enough that treating them as interchangeable memory switches leads to slow or unstable runs.
\nZeRO: Memory Optimizations Toward Training Trillion Parameter Models. ↩
\nMegatron-LM: Training Multi-Billion Parameter Language Models Using Model Parallelism. ↩
\nGPipe: Efficient Training of Giant Neural Networks Using Pipeline Parallelism. ↩
\nSwitch Transformers: Scaling to Trillion Parameter Models with Simple and Efficient Sparsity. ↩
\nAttention is often introduced as three matrix operations: form , apply softmax, then multiply by . That description omits the storage hierarchy. A conventional implementation writes the score matrix to high-bandwidth memory, reads it for softmax, writes probabilities, and reads them again for the value product.
\nFlashAttention computes exact attention while avoiding materialization of the full score matrix. Its central optimization is data movement: tile operands into on-chip memory, update softmax statistics online, and write only the final output.1
\nFor query and key sequence lengths and , the score matrix has entries:
\n\nEven when arithmetic fits the accelerator, storing and rereading and creates off-chip traffic proportional to their size. The original FlashAttention paper frames the algorithm as IO-aware and analyzes reads and writes across GPU memory levels.1
\n![\"Attention](\"https://blog.ecitis.org/feeds/figures/modern-attention-kernels-0.webp\")
Softmax appears to require an entire row because its denominator includes every key:
\n\nThe computation can be updated block by block. For a row, keep running maximum , running normalization sum , and an unnormalized output accumulator . Given a new score tile with maximum :
\n\n\n\nAfter the final key tile, output . Rescaling by the new maximum preserves numerical stability. No approximation is introduced by the tiling rule.
\nA simplified forward kernel loops over query tiles and key-value tiles:
\nfor each Q tile:\n load Q into on-chip memory\n initialize row maxima, sums, output accumulators\n\n for each K,V tile allowed by the mask:\n load K and V\n compute score tile\n apply scale and mask\n update online softmax state\n accumulate weighted V\n\n normalize and write outputTile shapes depend on head dimension, element type, register pressure, on-chip memory, and accelerator generation. Larger tiles increase reuse but can reduce occupancy when each program consumes too many registers.
\nCausal attention skips tiles wholly above the diagonal and masks the intersecting boundary tile. Local attention changes the visited tile range. Arbitrary sparse masks need an index structure that tells the kernel which blocks exist.
\nSaving the full probability matrix would reintroduce quadratic storage. FlashAttention saves compact normalization statistics and recomputes score tiles during backpropagation.1 It spends arithmetic to avoid memory traffic and activation storage.
\nThis trade is useful only when recomputation is cheaper than writing and reading the intermediate. Profiling must include the whole layer because fused dropout, bias, and masking can change the balance.
\nFlashAttention-2 changes work partitioning to improve parallelism and reduce non-matrix-multiplication work.2 It parallelizes across sequence length when batch size and head count do not expose enough thread blocks, and adjusts how work is shared within a thread block.2
\nThe lesson is broader than a version comparison. An asymptotically efficient algorithm can leave hardware idle if its grid has too few independent programs. Kernel selection needs batch, head count, sequence length, and head dimension.
\nPrefill has many query positions and many key positions. Tiled matrix multiplication works well. Decode often has one query position per sequence and a long cache. It cannot reuse query work across a large query tile.
\nDecode attention therefore focuses on:
\nCalling both implementations FlashAttention hides this shape difference. Record kernel choice separately for prefill and decode.
\nPagedAttention stores cache blocks in non-contiguous physical memory and resolves them through a per-sequence block table. The vLLM paper reports near-zero cache waste and flexible cache sharing from this design.3
\nA paged decode kernel maps logical token position to:
\nlogical block = position / block_size\noffset = position % block_size\nphysical = block_table[sequence, logical_block]\naddress = cache_base + physical * block_stride + offset * token_strideThe extra loads and address arithmetic buy dynamic allocation. Performance depends on block-table locality, block layout, and vectorized loads from physical pages.
\nPaged attention and FlashAttention solve related but distinct problems:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Technique | Primary target | Key mechanism |
|---|---|---|
| FlashAttention | Score-matrix IO | Tiling and online softmax |
| PagedAttention | Dynamic KV allocation | Logical-to-physical block mapping |
| Grouped-query attention | KV cache and projection size | Share KV heads across query groups |
| Sparse attention | Number of attended pairs | Visit selected score blocks |
A serving engine can combine them: tiled prefill, paged decode, grouped-query cache layout, and sparse visitation for long contexts.
\nFused kernels reorder floating-point operations. Validate against a reference implementation across:
\nUse absolute and relative error tolerances tied to output precision. Also compare gradients for training kernels and sampled outputs for inference pipelines.
\nRegister spilling: a larger tile silently moves local values to off-chip memory. Inspect compiler resource reports and achieved occupancy.
\nMask boundary errors: the fast path reads future tokens or padding on partial tiles. Test every boundary around tile and page sizes.
\nIncorrect online rescaling: output accumulators are not rescaled when a later tile raises the row maximum. Compare adversarial logits where the largest score appears late.
\nPage-table mismatch: allocator and kernel disagree about block stride or layout version. Encode layout identity in engine metadata.
\nWrong kernel for decode: a prefill-optimized kernel launches too little useful work for single-query attention. Profile by phase and shape.
\nMeasure wall time, achieved bandwidth, arithmetic utilization, kernel launches, and temporary bytes. Sweep the real shape space rather than one square sequence:
\nWarm kernels, pin clocks where the environment allows it, and report medians plus tail behavior. End-to-end token latency remains the deciding metric because a fast attention kernel can expose another bottleneck in projections, collectives, sampling, or cache allocation.
\nModern attention kernels are memory-system programs expressed through tensor algebra. Their speed comes from deciding what never reaches off-chip memory, what is recomputed, and how logical sequence state maps onto physical storage.
\nTri Dao et al., “FlashAttention: Fast and Memory-Efficient Exact Attention with IO-Awareness,” NeurIPS, 2022. https://arxiv.org/abs/2205.14135 ↩ ↩2 ↩3
\nTri Dao, “FlashAttention-2: Faster Attention with Better Parallelism and Work Partitioning,” ICLR, 2024. https://arxiv.org/abs/2307.08691 ↩ ↩2
\nWoosuk Kwon et al., “Efficient Memory Management for Large Language Model Serving with PagedAttention,” SOSP, 2023. https://arxiv.org/abs/2309.06180 ↩
\nAutoregressive decoding normally invokes the target model once for each output token. Speculative decoding asks a cheaper draft process to propose several tokens, then evaluates those positions together with the target model.
\nThe target model remains authoritative. A correct acceptance rule preserves its output distribution; speculation changes the execution schedule, not the distribution being sampled. Independent work by Leviathan, Kalman, and Matias and by Chen and collaborators established this lossless sampling construction.12
\nLet be the draft probability for a proposed token and the target probability at the same position. The verifier accepts draft token with:
\n\nIf the token is rejected, the correction distribution is proportional to:
\n\nNormalizing and sampling from this residual corrects the draft’s over-allocation of probability. If every proposal is accepted, the verifier can also sample an additional target token from the final verified position.12
\nThis is not the same as accepting whenever the target model’s argmax matches the draft. Greedy matching can preserve greedy output, but it does not implement sampling from the target distribution.
\n![\"Draft](\"https://blog.ecitis.org/feeds/figures/speculative-decoding-0.webp\")
Suppose the draft model proposes tokens. The target receives the original prefix plus those candidates and returns logits for each proposed position in one forward pass. Causal masking prevents a position from reading later candidates, so each target distribution matches the distribution that ordinary autoregressive decoding would compute at that prefix.
\nThe execution loop is:
\nwhile not finished:\n proposals, q_probs = draft(prefix, draft_length)\n p_probs = target(prefix + proposals)\n\n accepted = []\n for token, q, p in zip(proposals, q_probs, p_probs):\n if uniform() <= min(1.0, p[token] / q[token]):\n accepted.append(token)\n else:\n accepted.append(sample(normalize(maximum(p - q, 0))))\n break\n\n if len(accepted) == len(proposals):\n accepted.append(sample(p_probs.after_last_candidate))\n\n prefix.extend(accepted)Real implementations must use the exact distributions after temperature, top-, top-, penalties, and any token masks. Applying a transform to only one model invalidates the acceptance ratio.
\nSpeculation trades draft work and a wider target pass for fewer sequential target invocations. The useful quantity is not draft accuracy alone. Measure accepted output tokens per verification pass.
\nLet be target verification cost for a candidate span, draft cost, and expected committed tokens. A simple average cost is:
\n\nThe best draft length depends on batch size, prompt length, target architecture, draft architecture, and workload. Longer spans expose more parallel target work but risk wasting later candidates after an early rejection.
\nAn adaptive controller can choose draft length from recent acceptance:
\nfunction nextDraftLength(emaAcceptance: number, current: number) {\n if (emaAcceptance > highThreshold) return Math.min(current + step, maximum)\n if (emaAcceptance < lowThreshold) return Math.max(current - step, minimum)\n return current\n}Thresholds must come from serving measurements. Hard-coded values copied from another model pair do not transfer reliably.
\nA draft model must be cheaper and sufficiently aligned with the target. It also needs compatible tokenization. Different vocabularies require a mapping scheme and make probability correction more complex.
\nEvaluate candidates on:
\nA small model on the same accelerator can compete with the target for memory bandwidth. A draft on another device adds communication and synchronization. The fastest isolated draft is not necessarily the best colocated draft.
\nBoth models need state for the accepted prefix. Draft tokens beyond the rejection point must be rolled back. The target cache can retain verified accepted positions, while rejected suffix blocks become free.
\nPaged caches simplify rollback when each speculative span receives provisional blocks. Commit accepted positions, truncate the final partial block, and release later blocks. Avoid copying the entire cache for each attempt.
\nContinuous batching adds divergence. Requests accept different counts, so their logical sequence lengths change by different amounts after one verification iteration. The scheduler must update block tables and sampling state per request before forming the next batch.
\nMismatched temperature: draft and target probabilities refer to different transformed distributions.
\nPenalties applied at different prefixes: repetition or presence penalties see speculative tokens on one side but not the other.
\nGrammar masks applied only to the target: the draft assigns mass to illegal tokens, reducing acceptance and complicating residual sampling.
\nRounded probabilities: low-precision acceptance ratios introduce bias. Keep probability arithmetic at a precision validated against a non-speculative sampler.
\nRandom-number reuse: batched rollback changes random-number consumption. Counter-based generators indexed by request and logical sample step make replay easier.
\nThe draft need not be a separate autoregressive model. Multiple heads can propose future tokens from the target’s hidden state. Medusa adds decoding heads and verifies a tree of candidates, avoiding a separate draft model.3 Tree verification trades more candidate positions for a greater chance that one path matches the target.
\nThe verifier must construct a causal mask that represents the tree. Tokens on one branch cannot attend to siblings. Cache positions also need branch-specific ownership until a path is accepted.
\nReport latency distributions and acceptance together:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Metric | Diagnostic value |
|---|---|
| Accepted tokens per target pass | Direct measure of sequential work removed |
| Rejection position histogram | Detects spans that are too long |
| Draft time per proposed token | Captures draft bottlenecks |
| Verification time by candidate count | Reveals target-kernel scaling |
| Rollback bytes and blocks | Finds cache churn |
| Acceptance by request class | Supports adaptive routing |
Compare against the same target model, sampling configuration, and scheduler without speculation. Verify distributional equivalence with seeded tests over many prompts, then run task-level quality evaluation to catch integration errors.
\nSpeculative decoding wins when cheap proposals align with the target and the hardware can verify several positions more efficiently than it can execute the same number of sequential decode steps. Its acceptance mathematics is exact; its systems benefit is empirical.
\nYaniv Leviathan, Matan Kalman, and Yossi Matias, “Fast Inference from Transformers via Speculative Decoding,” ICML, 2023. https://arxiv.org/abs/2211.17192 ↩ ↩2
\nCharlie Chen et al., “Accelerating Large Language Model Decoding with Speculative Sampling,” arXiv, 2023. https://arxiv.org/abs/2302.01318 ↩ ↩2
\nTianle Cai et al., “Medusa: Simple LLM Inference Acceleration Framework with Multiple Decoding Heads,” ICML, 2024. https://arxiv.org/abs/2401.10774 ↩
\nModel Context Protocol is a stateful protocol for connecting an AI host to servers that expose context and actions. Its useful abstraction is not a universal tool API. It is a boundary: the host retains the conversation and policy decisions, while each client maintains an isolated connection to one server.1
\nThat distinction determines where permissions, user consent, context selection, and model calls belong. A server describes what it offers. The host decides what enters the model context and which action requests are allowed to execute.
\nAn MCP host creates clients, coordinates model integration, controls connection permissions, and aggregates context. Each client owns a stateful session with one server. A server exposes focused capabilities without receiving the host’s complete conversation or the state of other servers.1
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Process | Owns | Must not assume |
|---|---|---|
| Host | Conversation, user consent, policy, model orchestration | That a server is safe because it speaks MCP |
| Client | Protocol session, message correlation, capability state | That an undeclared method is supported |
| Server | Tools, resources, prompts, server-side access checks | That a tool call proves user intent |
This split prevents a calendar server from silently reading repository context supplied by a source-control server. Cross-server data movement is a host decision, not a protocol side effect.
\nMCP messages use JSON-RPC. A request carries an id and expects either a result or an error. A notification has no id and receives no response. A response must contain a result or an error, never both.2
{\n \"jsonrpc\": \"2.0\",\n \"id\": \"req-42\",\n \"method\": \"tools/call\",\n \"params\": {\n \"name\": \"read_invoice\",\n \"arguments\": { \"invoice_id\": \"INV-1042\" }\n }\n}The id is a correlation key. It is not an authorization token, idempotency key, or tracing policy. A host that retries a side-effecting request must define idempotency above the protocol or include an application-level key in the tool input.
MCP’s current base specification does not support JSON-RPC batching. Each request, notification, and response travels as its own protocol message.3
\n![\"MCP](\"https://blog.ecitis.org/feeds/figures/mcp-first-principles-0.webp\")
Initialization must be the first client-server interaction. The client proposes a protocol version and declares client capabilities. The server returns its selected version and server capabilities. The client then sends notifications/initialized before normal operation.4
{\n \"jsonrpc\": \"2.0\",\n \"id\": 1,\n \"method\": \"initialize\",\n \"params\": {\n \"protocolVersion\": \"2025-06-18\",\n \"capabilities\": {\n \"roots\": { \"listChanged\": true },\n \"sampling\": {},\n \"elicitation\": {}\n },\n \"clientInfo\": {\n \"name\": \"research-workbench\",\n \"version\": \"1.0.0\"\n }\n }\n}The version and example fields above follow the published lifecycle example.4 If the server selects a version the client does not support, the client should disconnect. For HTTP transport, later requests carry the negotiated version in the MCP-Protocol-Version header.5
Capabilities are executable protocol state, not descriptive metadata. A server may call client sampling only when the client advertised sampling. A server may emit resource update notifications only when it advertised the relevant resource subscription support. Method dispatch should check negotiated state before parsing business arguments.
type Session = {\n phase: 'new' | 'operating' | 'closed'\n protocolVersion?: string\n serverCapabilities?: {\n tools?: { listChanged?: boolean }\n resources?: { subscribe?: boolean; listChanged?: boolean }\n }\n}\n\nfunction assertToolCallAllowed(session: Session): void {\n if (session.phase !== 'operating' || !session.serverCapabilities?.tools) {\n throw new Error('tools/call was not negotiated')\n }\n}The server primitives have different control semantics. Prompts are user-controlled templates, resources are application-controlled context, and tools are model-controlled actions.6
\nA resource has a URI and content. It suits files, schemas, records, logs, or generated views that a client may inspect and selectively place in context. Servers must validate resource URIs and should enforce access controls on sensitive resources.7
\nResources are not passive just because they are read-only. Retrieved text can contain instructions aimed at the model. The host should attach provenance and treat resource content as untrusted data.
\nPrompts package messages and arguments for explicit user selection. They work well for named tasks such as code review or incident summarization. A prompt does not override host policy. It supplies content for the host to inspect and render.
\nA tool definition combines a stable name, description, and input schema. Tool results can return text, images, embedded resources, resource links, and structured content. The protocol revision published on 18 June 2025 added structured tool output.3
\n{\n \"name\": \"create_change_request\",\n \"description\": \"Create a draft change request in the selected repository\",\n \"inputSchema\": {\n \"type\": \"object\",\n \"properties\": {\n \"repository\": { \"type\": \"string\" },\n \"title\": { \"type\": \"string\", \"minLength\": 1 },\n \"body\": { \"type\": \"string\", \"minLength\": 1 }\n },\n \"required\": [\"repository\", \"title\", \"body\"],\n \"additionalProperties\": false\n }\n}The schema constrains shape, not authority. A valid repository string can still point at a repository the user did not authorize.
\nMCP defines standard input and output transport for local process connections and Streamable HTTP for remote connections.5 Transport choice changes the threat model.
\nWith standard input and output, the host launches a process and exchanges newline-delimited JSON-RPC messages. Credentials should come from the environment rather than the HTTP authorization flow.8 The host must still control executable paths, environment variables, inherited file descriptors, and working directories.
\nWith Streamable HTTP, the server exposes an MCP endpoint that accepts POST and may support GET for server-sent events. Implementations must validate the Origin header to defend against DNS rebinding, bind local servers to loopback rather than all interfaces, and add authentication when appropriate.5
Authorization is optional at the protocol level. When an HTTP server protects resources, the MCP authorization specification treats it as an OAuth resource server. The client acts as an OAuth client, and a separate authorization server issues tokens.8
\nThe discovery path is deliberate:
\nThe client must include the OAuth resource parameter in authorization and token requests. The server must validate that the token was issued for itself.8 This audience binding prevents a token meant for one MCP server from becoming a bearer credential accepted by another.
Public clients must use Proof Key for Code Exchange. Authorization endpoints must use HTTPS, while redirect URIs must use HTTPS or localhost. Redirect URI matching must be exact, and clients should bind the flow with state.8
An MCP server that calls an upstream API is a separate OAuth client to that API. It must not forward the token received from the MCP client. The upstream token has a different audience and should be acquired through a separate authorization relationship.8
\nMCP client -- token audience: files.example --› Files MCP server\nFiles MCP server -- separate token audience: storage-api --› Storage APIForwarding the first token erases the resource boundary and creates a confused-deputy path.
\nOAuth answers which client can call a server on behalf of which resource owner. It does not answer whether a model-generated action is appropriate in the current conversation.
\nTool execution needs a second control plane:
\ntype Decision = 'allow' | 'deny' | 'require_user'\n\nfunction authorizeTool(input: {\n tool: string\n arguments: unknown\n user: { id: string; roles: string[] }\n conversationId: string\n}): Decision {\n if (input.tool === 'read_invoice') return 'allow'\n if (input.tool === 'create_refund') return 'require_user'\n return 'deny'\n}The host should show the actual target and material arguments before approval. A button labeled “Allow tool” provides less information than “Create a refund for invoice INV-1042.” Servers must also apply their own authorization because a client can call them without using a model.
\nProtocol errors and tool errors belong to different layers. Malformed JSON-RPC, unknown methods, and invalid protocol state should produce JSON-RPC errors. A valid tool invocation that fails in its domain should return a tool result marked as an error so the model can reason about the failure.
\nOperational safeguards include:
\nRetries should be method-aware. Listing tools is naturally repeatable. Creating a record is not repeatable unless the tool contract includes an idempotency mechanism.
\nAn interoperable implementation begins with protocol correctness:
\nA deployable implementation adds security controls:
\nMCP standardizes the wire conversation. It does not remove the need for access control, policy, validation, or user-visible consent. Those controls remain with the host and each resource-owning server.
\nModel Context Protocol, Architecture, protocol revision 2025-06-18. ↩ ↩2
\nModel Context Protocol, Base Protocol overview, protocol revision 2025-06-18. ↩
\nModel Context Protocol, key changes in protocol revision 2025-06-18. ↩ ↩2
\nModel Context Protocol, Lifecycle, protocol revision 2025-06-18. ↩ ↩2
\nModel Context Protocol, Transports, protocol revision 2025-06-18. ↩ ↩2 ↩3
\nModel Context Protocol, Server Features overview, protocol revision 2025-06-18. ↩
\nModel Context Protocol, Resources, protocol revision 2025-06-18. ↩
\nPrompting a model to return JSON asks a probabilistic decoder to imitate a grammar. Constrained decoding changes the operation: before sampling, the runtime masks tokens that cannot extend any valid document in the target language.
\nThe result can guarantee syntax without guaranteeing truth. A schema can force an integer field, but it cannot prove that the integer was computed from the source text.
\nJSON Schema, a regular expression, or a context-free grammar is not applied directly to model logits. The serving system compiles the constraint into a recognizer with runtime state.
\nAt generation step , let be the vocabulary and be the tokens accepted from grammar state . Masked logits are:
\n\nSampling then uses the normalized distribution over legal tokens. Willard and Louf formulate guided generation as transitions in a finite-state machine and build an index over the model vocabulary.1 Context-free constraints require stack state because nesting cannot be represented by a finite-state machine alone.
\n![\"Grammar](\"https://blog.ecitis.org/feeds/figures/structured-generation-0.webp\")
A tokenizer can encode punctuation together with adjacent text. A token might contain a quote, property characters, and a colon. Another token can contain a byte prefix that is invalid alone but valid when followed by later bytes.
\nThe matcher must answer a prefix question: does the token’s byte sequence keep at least one valid completion reachable? Checking only complete terminals rejects useful multi-character tokens. Checking decoded Unicode strings can mishandle byte-level tokenizers.
\nA robust engine:
\nXGrammar separates context-independent grammar components from context-dependent components and overlaps grammar processing with GPU execution.2 Its design addresses the cost of walking grammar stacks across a large vocabulary.2
\nJSON grammar guarantees balanced delimiters, quoted keys, and valid scalar syntax. A schema adds semantic structure:
\n{\n \"type\": \"object\",\n \"properties\": {\n \"status\": { \"enum\": [\"ok\", \"error\"] },\n \"retryable\": { \"type\": \"boolean\" },\n \"code\": { \"type\": \"integer\", \"minimum\": 0 }\n },\n \"required\": [\"status\", \"retryable\"],\n \"additionalProperties\": false\n}Compilation must define which schema features are supported. Object property ordering, numeric bounds, string patterns, recursive references, unions, and additionalProperties each require different machinery. A provider that accepts a schema but ignores unsupported keywords supplies weaker guarantees than the input document suggests.
Publish a supported subset and reject unsupported constraints at request validation. Silent downgrade turns a type contract into a prompt hint.
\nNaively testing every vocabulary token at every step repeats work. Production engines reduce that cost through:
\nThe mask still has to reach the sampling kernel. Copying a dense vocabulary-sized mask from host memory per sequence and per step can dominate short structured outputs. Bitsets, cached device masks, and batch grouping by grammar state reduce transfer.
\nBatching introduces divergence. Two requests using the same schema can occupy different parse states, so their legal sets differ. The sampler must apply per-sequence masks even when the model forward pass is batched.
\nJSON permits whitespace in many positions. Leaving all whitespace paths open expands grammar state and lets the model spend tokens formatting. A canonical mode can constrain separators and indentation, but it changes the accepted language.
\nDefine canonicalization as an API option:
\ntype StructuredOutputOptions = {\n schema: object\n whitespace: 'compact' | 'model'\n rejectUnsupportedKeywords: true\n maxOutputTokens: number\n}Compact output reduces token use. Model-controlled whitespace preserves stylistic freedom. Neither choice changes field semantics.
\nGrammar terminals rarely align with model tokens. DOMINO uses token-aligned finite-state machines so a token can span several grammar terminals without forcing a token boundary after each terminal.3 This avoids rejecting a token merely because it packages punctuation, whitespace, and property text together.
\nSynCode precomputes a finite lookahead table for grammar terminals and uses it to construct masks for context-free grammars.4 Two properties need separate tests:
\nAn unsound masker can emit invalid output. An incomplete masker can force low-probability tokenization paths even when the intended text is valid. Boundary fixtures should include escaped text, punctuation merged with names, and byte sequences split across tokens.
\nConstrained output should still terminate at an ordinary validator:
\nimport json\nfrom jsonschema import Draft202012Validator\n\ndef validate_generated_payload(raw_text, schema):\n payload = json.loads(raw_text)\n validator = Draft202012Validator(schema)\n errors = sorted(\n validator.iter_errors(payload),\n key=lambda error: list(error.absolute_path),\n )\n if errors:\n formatted = [\n {\n \"path\": list(error.absolute_path),\n \"message\": error.message,\n }\n for error in errors\n ]\n raise ValueError(formatted)\n return payloadInstall jsonschema and supply the same schema compiled by the generation engine. This second validation catches engine defects and documents the trust boundary. Domain checks follow it and can query authoritative identifiers or enforce cross-field rules.
Compile user-supplied schemas before reserving model capacity. Cache compiled state by canonical schema bytes, tokenizer revision, grammar compiler version, and whitespace policy.
\nSet separate limits for schema bytes, recursive depth, grammar states, and compile time. Returning a validation error before inference keeps malformed schemas out of the model queue.
\nExpose the compilation result:
\ntype CompiledConstraint = {\n digest: string\n compilerVersion: string\n tokenizerRevision: string\n supportedKeywords: readonly string[]\n ignoredKeywords: readonly never[]\n}The never[] type expresses the strict policy: unsupported keywords cause rejection. If compatibility requires permissive handling, name that mode explicitly and return every ignored keyword.
Apply three validation layers after decoding:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Layer | Detects | Example |
|---|---|---|
| Parser | Invalid JSON bytes | Unclosed string |
| Schema validator | Wrong shape or local constraint | Missing required field |
| Domain validator | Cross-field and external rules | Unknown database identifier |
Constrained decoding should make parser failure unreachable under supported conditions. Schema validation remains useful as a defense against implementation bugs and unsupported keywords. Domain validation is mandatory before side effects.
\nFor tool calls, treat model output as untrusted input even when it matches the schema. Resolve authorization from server-side identity. Do not allow a generated account identifier or file path to expand permissions.
\nA recursive grammar can generate an unbounded document. The model still needs a token budget. If the budget ends before an accepting state, the result is structurally incomplete.
\nThe runtime should distinguish:
\nReturning partial bytes as ordinary JSON hides the failure. Return an explicit structured-generation status outside the generated payload.
\nEmpty legal set: the recognizer or tokenizer integration has reached a state with no accepted token. Log the grammar state, recent token bytes, tokenizer revision, and schema digest.
\nSchema explosion: a large union or deeply recursive schema creates expensive state sets. Enforce compilation limits before model execution.
\nCache poisoning: a compiled-grammar cache uses an incomplete key. Include compiler version, tokenizer identity, schema bytes, and generation options.
\nUnsupported keyword drift: a library upgrade changes which constraints are enforced. Pin compiler versions and run conformance fixtures.
\nUnicode mismatch: validation operates on characters while masking operates on token bytes. Use one explicit byte-to-text policy and test invalid sequences.
\nGenerate tests from the constraint rather than collecting a few successful prompts:
\nFor each case, assert parser validity, schema validity, accepted-state termination, and deterministic failure classification. Separately evaluate factual accuracy. Grammar conformance and task quality are different metrics.
\nStructured generation is reliable when the contract is precise: a documented schema subset, a tokenizer-aware recognizer, state-specific masks, and post-generation domain validation. Prompt wording alone provides none of those guarantees.
\nBrandon T. Willard and Rémi Louf, “Efficient Guided Generation for Large Language Models,” arXiv, 2023. https://arxiv.org/abs/2307.09702 ↩
\nYixin Dong et al., “XGrammar: Flexible and Efficient Structured Generation Engine for Large Language Models,” arXiv, 2024. https://arxiv.org/abs/2411.15100 ↩ ↩2
\nLuca Beurer-Kellner, Marc Fischer, and Martin Vechev, “Guiding LLMs The Right Way: Fast, Non-Invasive Constrained Generation,” ICML, 2024. https://arxiv.org/abs/2403.06988 ↩
\nSuresh G. K. et al., “SynCode: LLM Generation with Grammar Augmentation,” arXiv, 2024. https://arxiv.org/abs/2403.01632 ↩
\ntorch.compile is not a single compiler pass. It is a guarded path from a live Python program to reusable machine code. TorchDynamo captures tensor operations from Python frames, AOTAutograd constructs forward and backward graphs, and TorchInductor lowers those graphs into device code. On supported GPUs, Inductor uses Triton as a code-generation building block.1
![\"Compilation](\"https://blog.ecitis.org/feeds/figures/torch-compile-internals-0.webp\")
Dynamo hooks Python frame evaluation and symbolically executes bytecode. Tensor operations become nodes in an FX graph. Python values that affect execution become assumptions. A guard records each assumption needed to reuse the graph, including tensor shape, dtype, device, object identity, or a global value.2
\nThis distinction matters. Dynamo does not prove that a function has one universal tensor graph. It records one graph for one set of observed conditions, then emits checks that decide whether later calls fit that specialization.
\nimport torch\n\ndef normalize_or_zero(x, enabled):\n if enabled:\n return x / x.norm()\n return torch.zeros_like(x)\n\ncompiled = torch.compile(normalize_or_zero)Here, enabled is a Python boolean. Dynamo can specialize on its value and cache separate graphs for the branches. A tensor-dependent condition is different:
def branch_on_data(x):\n if x.sum() > 0:\n return x.sin()\n return x.cos()The branch requires a tensor value that is available only after execution. PyTorch documents tensor-dependent control flow and direct scalar extraction with .item() as common graph-break causes.3
At a graph break, Dynamo compiles the graph captured so far, returns to ordinary Python for the unsupported operation, then resumes tracing. Correctness is preserved, but fusion cannot cross the boundary. A break inside a transformer block can therefore cost more than one in preprocessing because the former separates operators that exchange large intermediate tensors.
\nUse the compiler logs before rewriting code:
\nTORCH_LOGS=\"graph_breaks,guards,recompiles\" python train.pyfullgraph=True converts the first graph break into an error and requires one captured graph. PyTorch recommends it when the goal is to find and remove breaks in a performance-critical region.4
@torch.compile(fullgraph=True)\ndef block(x, weight, bias):\n return torch.nn.functional.gelu(x @ weight + bias)Do not force file I/O, metrics emission, or data decoding into that function. Mark a problematic helper with torch.compiler.disable, or place compilation around the numerical core. The boundary should express the part of the program whose inputs, side effects, and shapes are stable.
Eager autograd records operations while the forward pass runs. AOTAutograd instead traces a functional forward graph and constructs a corresponding backward graph ahead of execution. This gives the compiler visibility into saved tensors, recomputation choices, and backward operators. PyTorch describes AOTAutograd as the component that captures backpropagation for acceleration by Inductor.1
\nSuppose a forward graph computes:
\n\nThe backward needs values derived from the matrix product and activation. A partitioner decides what the forward should save versus what the backward can recompute. Saving reduces arithmetic and increases live memory. Recomputation makes the opposite trade. This is why a compiled training step can have a different memory profile from eager execution while retaining the same differentiation result.
\nMutation and aliasing complicate this graph. AOTAutograd functionalizes many in-place operations into functional equivalents, then tracks the mutations that must be reflected at the boundary. Custom operators need correct aliasing and mutation declarations; a wrong schema can turn a local implementation mistake into a compiler-wide correctness problem.
\nInductor receives ATen-level graphs after decomposition. It reasons about iteration domains, dependencies, device placement, layouts, and reuse. Elementwise chains are strong fusion candidates because their loop domains align.
\nAn eager expression such as:
\ny = torch.nn.functional.gelu(x @ weight + bias)\nz = y * scale + residualcan launch separate kernels for bias addition, activation, multiplication, and residual addition around a matrix multiplication. Inductor can select a matrix-multiplication template and fuse compatible pointwise epilogues, or generate a separate fused pointwise kernel when the template boundary prevents full fusion. The useful question is not the number of FX nodes. It is how many times large tensors are written to and read from device memory.
\nFusion is constrained by:
\nOn GPUs, Triton code expresses blocked loads, arithmetic, and stores. On CPUs, Inductor emits C++ with vectorized loops. Backend choice changes the generated code, but Dynamo guards and graph partitioning remain part of the contract.
\nStatic dimensions give Inductor concrete loop bounds and specialization opportunities. Variable sequence lengths can trigger recompilation when a guard fails. PyTorch first assumes static shapes under dynamic=None, then can retry with dynamic dimensions after a shape-driven recompilation.2
There are three operational responses:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Workload property | Compiler policy | Cost |
|---|---|---|
| Few stable shapes | Specialize and cache | More kernels, stronger specialization |
| Broad bounded shapes | Mark selected dimensions dynamic | Fewer recompiles, more general code |
| Unbounded irregular shapes | Bucket or pad before compilation | Extra padding work, predictable cache |
Do not set every dimension dynamic as a reflex. Batch and sequence axes often vary; head width and vocabulary partition usually do not. Encode the variability that exists in production traces.
\nThe default mode balances compile time and runtime work. reduce-overhead uses CUDA graphs where applicable to reduce Python and launch overhead. max-autotune benchmarks candidate matrix-multiplication or convolution implementations and enables CUDA graphs on supported GPU paths.5
compiled_step = torch.compile(\n train_step,\n mode=\"max-autotune\",\n dynamic=None,\n)Warm-up measurements must be separated from steady-state measurements. Compilation and autotuning run on early calls, and a new shape or guard value can cause later recompilation. Measure:
\nPyTorch exposes backend ablations that isolate the failing stage.6
\n# Dynamo capture only\ntorch.compile(fn, backend=\"eager\")\n\n# Add AOTAutograd\ntorch.compile(fn, backend=\"aot_eager\")\n\n# Run the complete default stack\ntorch.compile(fn, backend=\"inductor\")If eager capture fails, inspect Python semantics and graph breaks. If aot_eager fails, inspect autograd, functionalization, mutation, and custom-operator schemas. If only Inductor fails, preserve the FX graph and generated debug trace, then reduce the operator pattern.
Accuracy testing should compare outputs and gradients across representative dtypes and shapes. Compiler speed is irrelevant if a custom kernel mishandles non-contiguous inputs or a low-precision reduction exceeds the application tolerance.
\nCompile the numerical step rather than the surrounding service loop. Establish shape buckets from observed traffic. Warm each bucket before accepting latency-sensitive work. Record guard failures and recompiles. Keep an eager fallback for unsupported paths, but alert when it is used. Pin the PyTorch and driver environment used for performance qualification because generated kernels and compiler behavior are environment-dependent.
\ntorch.compile works best when the program exposes stable tensor regions with explicit boundaries. Dynamo supplies guarded capture, AOTAutograd supplies differentiable graphs, and Inductor supplies loop-level optimization. Performance work consists of preserving those regions, controlling specialization, and verifying the generated execution rather than treating the decorator as a universal switch.
PyTorch compiler troubleshooting: guards and recompilation. ↩ ↩2
\nPyTorch compiler troubleshooting: data-dependent operations. ↩
\nAn LLM request contains two workloads with different shapes. Prefill evaluates all prompt tokens and produces the first output token. Decode repeatedly evaluates one new position while reading the accumulated key-value cache.
\nColocating both phases is operationally simple. It also couples their batching, parallelism, and latency. Disaggregated serving assigns prefill and decode to different worker pools, transfers the cache between them, and scales each pool against its own service objective. DistServe formalized this design around time to first token and time per output token.1
\nPrefill exposes matrix dimensions large enough to use compute units efficiently. Decode uses small per-request matrix dimensions and repeatedly streams model weights and cache state. A shared worker must compromise between large prompt batches and decode cadence.
\nDisaggregation permits separate plans:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Decision | Prefill pool | Decode pool |
|---|---|---|
| Primary latency | Time to first token | Time per output token |
| Batching unit | Prompt tokens or chunks | Active sequences |
| Parallelism | Favor prompt throughput | Favor low collective overhead |
| Capacity signal | Queued prompt tokens | Active sequences and live KV bytes |
| Scale trigger | Predicted prefill queue time | Predicted inter-token delay |
DistServe reports that phase separation removes prefill-decode interference and allows different resource and parallelism choices for each phase.1 The paper’s evaluation found up to higher request rate or tighter service objectives than its baselines, with more than of requests meeting the specified constraints.1
\n![\"Prefill](\"https://blog.ecitis.org/feeds/figures/disaggregated-llm-serving-0.webp\")
After prefill, decode cannot start until the required keys and values are available. For cache size , effective link bandwidth , and fixed transfer overhead , a lower-bound model is:
\n\nThis is a planning bound, not a latency prediction. Contention, serialization, topology, registration, and synchronization increase elapsed time.
\nA transfer protocol needs:
\nDo not send a monolithic opaque tensor if the runtime stores paged blocks. Transfer complete blocks directly and preserve logical block order in metadata. This avoids repacking into a contiguous buffer.
\nWaiting for all layers to finish before beginning transfer leaves the link idle during prefill. Layerwise or blockwise streaming overlaps later prefill work with earlier cache movement:
\nprefill layer l\n -> record completion event\n -> enqueue KV blocks for layer l\n -> transport waits on event\n -> destination records receive completion\n -> decode waits before first read of layer lCorrectness depends on event ordering. A destination-visible pointer does not prove that the corresponding device writes have completed.
\nBackpressure is also required. If the destination cannot reserve blocks, the source should not compute a cache that has nowhere to land. Reserve destination capacity before admitting prefill, or allow an explicit spill path with its own latency budget.
\nThe router now controls a distributed pipeline. A useful estimate for candidate prefill worker and decode worker is:
\n\nThe terms represent prefill queue, prefill execution, transfer, and decode admission. Each estimate must use current topology and cache reservations.
\nRouting on queue length alone is weak because a queued long prompt carries more work than a queued short prompt. Count scheduled prompt tokens and use profiled execution curves. For decode, active sequence count also misses context length and cache pressure.
\nA prefill worker may already hold a reusable prefix. A decode worker may hold the previous turn of a conversation. Routing should compare reuse savings with queue and transfer costs.
\nUse explicit estimates:
\ntype PlacementCost = {\n queueMs: number\n computeMs: number\n transferMs: number\n recomputeMs: number\n capacityRisk: number\n}Keeping the terms visible prevents a cache-hit heuristic from silently overriding latency objectives.
\nTensor parallelism reduces per-device weight and compute, but each layer introduces collectives. Pipeline parallelism partitions layers and introduces pipeline scheduling. Prefill can amortize communication over larger token matrices. Decode executes collectives at every token step.
\nDistServe searches phase-specific parallelism and places communicating prefill and decode instances according to cluster bandwidth.1 Treat the selected topology as part of the deployment artifact. A scheduler cannot compensate for a prefill-decode pair split across a congested or oversubscribed path.
\nSplitwise profiles prompt and token generation separately, then assigns them to machine pools selected for each phase.2 Its architecture includes mixed machines that can absorb imbalances rather than leaving a saturated phase blocked behind an idle pool.2 This matters because a fixed prefill-to-decode ratio assumes a stable workload mix.
\nMooncake treats the cache as the center of a disaggregated architecture. It separates cache storage and transfer from compute scheduling, with a distributed cache that can reuse state across requests and workers.3 P/D-Serve focuses on fine-grained organization and dynamic adjustment of prefill and decode instances.4
\nThese systems expose separate controls:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Control | Question |
|---|---|
| Phase placement | Which worker executes prompt or token work? |
| Cache placement | Where do completed blocks remain available? |
| Elasticity | How does the pool ratio change with traffic? |
Do not conflate them in one autoscaler. A phase replica count can change without moving warm cache. A cache tier can become full while compute workers remain underutilized.
\nA near-runnable planner can turn sampled requests into initial offered-work estimates:
\nfrom dataclasses import dataclass\n\n@dataclass(frozen=True)\nclass Request:\n prompt_tokens: int\n output_tokens: int\n\ndef offered_work(requests, prefill_ms, decode_ms):\n prefill = sum(prefill_ms(r.prompt_tokens) for r in requests)\n decode = sum(\n decode_ms(r.prompt_tokens, r.output_tokens)\n for r in requests\n )\n return prefill, decodeThe functions must come from profiles on the intended hardware. Replace aggregate work with a queue simulation before deployment because service objectives depend on burst arrivals. Add measured transfer time to each prefill completion and enforce destination cache reservations.
\nDestination allocation failure: prefill finishes, but decode has no cache pages. Reserve before execution and release the reservation on cancellation.
\nOrphaned transfers: the client disconnects while cache movement is in flight. Propagate cancellation through router, source, transport, and destination; make cleanup idempotent.
\nVersion skew: pools run different model revisions or cache formats. Reject handoff on an exact layout identifier.
\nLink saturation: more prefill replicas increase offered transfer traffic without increasing decode capacity. Autoscaling must include link utilization and transfer queue time.
\nDecode starvation: routing admits more completed prefills than decode can drain. Apply pipeline admission control at the request boundary.
\nReplica hotspots: prefix-aware routing concentrates traffic. Bound affinity and fall back when predicted queue delay exceeds recomputation savings.
\nDisaggregation adds a networked state transfer, another admission boundary, and more failure states. It is not automatically faster. Keep phases colocated when transfer time consumes the expected interference savings, traffic is too small to fill separate pools, the topology lacks a predictable device-to-device path, or operational simplicity matters more than independent scaling.
\nBenchmark both designs with the same arrival trace and service objectives. Compare goodput, not raw tokens per second: count requests that satisfy both first-token and inter-token latency. That is the metric DistServe uses to connect resource planning to user-visible constraints.1
\nBefore production traffic:
\nDisaggregated serving is a scheduling architecture, not a socket between two model servers. Its value comes from independent phase control. Its cost is that cache placement, transport, and admission become part of inference correctness.
\nYinmin Zhong et al., “DistServe: Disaggregating Prefill and Decoding for Goodput-optimized Large Language Model Serving,” OSDI, 2024. https://arxiv.org/abs/2401.09670 ↩ ↩2 ↩3 ↩4 ↩5
\nPratyush Patel et al., “Splitwise: Efficient Generative LLM Inference Using Phase Splitting,” ISCA, 2024. https://arxiv.org/abs/2311.18677 ↩ ↩2
\nRuoyu Qin et al., “Mooncake: A KVCache-centric Disaggregated Architecture for LLM Serving,” FAST, 2025. https://arxiv.org/abs/2407.00079 ↩
\nYuhang Jin et al., “P/D-Serve: Serving Disaggregated Large Language Model at Scale,” arXiv, 2024. https://arxiv.org/abs/2408.08147 ↩
\nAutoregressive inference repeatedly evaluates attention over an expanding prefix. Recomputing every key and value projection at every step would repeat work for tokens that have not changed. A key-value cache stores those projections, then appends the projections for each new token.
\nThat optimization moves the serving limit. Model weights are mostly static, but cache allocation follows request arrivals, prompt lengths, generation lengths, beam branches, cancellations, and shared prefixes. The cache is therefore both a tensor and a dynamic memory-management problem.
\nFor a transformer layer, attention projects hidden states into queries, keys, and values:
\n\nDuring decode, the current query attends to cached keys and values:
\n\nOnly the current query is transient. Keys and values remain live because later tokens can attend to them.
\nFor a decoder with layers, key-value heads, head dimension , sequence length , and bytes per scalar, cache storage per sequence is:
\n\nThe leading factor accounts for separate key and value tensors. This formula exposes the useful levers: context length, cache precision, layer count, and key-value head count. Multi-query attention shares one key-value head across query heads; grouped-query attention uses more than one but fewer than full multi-head attention.1
\nPrefill processes a prompt as a token matrix. Each layer writes a run of key and value vectors, while attention consumes the prompt prefix. Decode appends a narrow slice and reads the existing cache.
\nThe distinction matters for kernel design:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Phase | Cache operation | Typical pressure |
|---|---|---|
| Prefill | Bulk allocation and writes | Compute, allocation latency |
| Decode | Append one position, read all prior positions | Memory bandwidth, cache capacity |
| Cancellation | Release every block owned by a request | Allocator synchronization |
| Prefix reuse | Map a new request to existing blocks | Reference counting, routing |
A serving scheduler must reserve enough blocks before admitting work. If it admits from token limits alone, a burst of long generations can exhaust cache pages after requests have begun streaming.
\n![\"Logical](\"https://blog.ecitis.org/feeds/figures/kv-cache-memory-systems-0.webp\")
A simple allocator reserves one contiguous region per sequence at its maximum configured length. That approach creates internal fragmentation when generation ends early. It also creates external fragmentation as variable-sized regions are allocated and freed.
\nPagedAttention applies operating-system paging to the cache. Logical token blocks map through a block table to non-contiguous physical blocks. vLLM’s original paper reports near-zero cache waste and supports cache sharing within and across requests; its evaluation measured between two and four times the throughput of the compared systems at comparable latency.2
\nThe attention kernel cannot assume that adjacent logical tokens are adjacent in memory. It resolves each logical block through the block table. That indirection is the price of flexible allocation.
\nSmall blocks reduce waste in the final, partially filled page. They increase block-table entries, allocation operations, and address translation inside the kernel. Large blocks reduce metadata but strand more capacity at sequence tails.
\nChoose block size with workload traces, not model shape alone. Record the distribution of prompt lengths, output lengths, cancellations, and prefix reuse. Then replay those traces against candidate block sizes and measure:
\nTwo requests can share cached blocks only when the token sequence and every cache-relevant model input match. Text equality is insufficient because tokenization settings, adapter selection, multimodal embeddings, position assignment, and model revision can change the resulting states.
\nA practical cache key includes:
\ntype PrefixKey = {\n modelRevision: string\n adapterId: string | null\n tokenIds: readonly number[]\n positionPolicy: string\n multimodalDigest: string | null\n}Hash blocks incrementally so a request can reuse the longest matching prefix. Store parent hashes to prevent a block with identical local tokens from matching under a different preceding context.
\nReference counts protect shared blocks. Copy-on-write handles divergence: requests share completed prefix blocks, while each allocates private blocks for generated continuations. The vLLM paper uses this mechanism for parallel sampling and beam search.2
\nEvicting a cache entry does not lose model weights or user data, but it turns the next hit into recomputation. A least-recently-used policy treats every block equally even though recomputation cost rises with the number of prefix tokens that must be replayed.
\nA cost-aware score can combine:
\n\nThe terms are estimates derived from observed traffic. Keep them separate in telemetry. A high hit rate can still save little compute if hits cover short prefixes.
\nCache-aware routing introduces another constraint. Sending a request to the least-loaded replica can discard a large local prefix hit. Sending every matching prefix to one replica can create a hotspot. Route using predicted queue time plus predicted prefill time after reuse.
\nQuantizing the cache reduces bytes per scalar in the storage formula. It also adds scale metadata and dequantization work to attention. Keys and values can require different calibration because their distributions differ by layer and head.
\nValidation must include generation quality and kernel performance. A cache format that halves tensor payload does not halve total latency if dequantization prevents a fused attention path. Measure:
\nGPU memory is not the only possible cache tier. A serving system can move inactive blocks to host memory, local storage, or another worker, then restore them when a request resumes. The decision compares transfer time with recomputation time.
\nPrompt Cache defines reusable prompt modules and preserves their positional accuracy when reusing attention state across prompts.3 CacheGen targets network transfer: it encodes key-value tensors into a compressed bitstream conditioned on their distribution, then adapts compression to available bandwidth.4
\nTiering needs an explicit state machine:
\ntype BlockState =\n | { kind: 'device'; gpu: number; address: bigint }\n | { kind: 'moving'; operationId: string; destination: 'host' | 'remote' }\n | { kind: 'host'; bufferId: string }\n | { kind: 'remote'; objectKey: string; checksum: string }\n | { kind: 'evicted' }Only one transition may own a block at a time. Cancellation during transfer must release both the source reference and any completed destination allocation. A checksum catches truncated or stale payloads, while model and layout identifiers prevent restoring cache produced by incompatible weights.
\nA near-runnable capacity calculator follows directly from the storage equation:
\ndef kv_bytes(layers, sequence, kv_heads, head_dim, bytes_per_scalar):\n return 2 * layers * sequence * kv_heads * head_dim * bytes_per_scalar\n\ndef concurrent_capacity(free_bytes, reserve_fraction, per_sequence_bytes):\n usable = int(free_bytes * reserve_fraction)\n return usable // per_sequence_bytesFeed it values from the deployed model configuration and runtime telemetry. The result is not admission control by itself; workspaces, allocator metadata, partial pages, and transfer buffers also consume memory.
\nChoose restore or recomputation using measured queue, transfer, decoding, and prefill curves. Report bytes restored, tokens recovered, tokens recomputed, and time saved. A high hit count is misleading if most restored prefixes are short.
\nAdmission overcommit: requests begin with enough memory for their prompts but no reserve for output growth. Reject or queue before prefill using a configurable output reservation.
\nLeaked references: cancellation bypasses a decrement path, leaving shared blocks permanently live. Audit ownership transitions and reconcile allocator totals.
\nHash collisions or incomplete keys: unrelated states share a block. Use a collision-resistant digest and include every state-changing input.
\nEviction storms: a working set slightly larger than capacity repeatedly recomputes prefixes. Track evicted-token recomputation, not just eviction count.
\nTail-page waste: a nominally paged allocator still wastes capacity if blocks are too large for the output-length distribution. Report occupancy inside allocated blocks.
\nThe minimum dashboard needs physical blocks free, reserved, active, shared, and evictable; cache hit tokens; recomputed tokens; allocation latency; and request aborts caused by cache pressure. Those measurements turn KV capacity from an opaque out-of-memory event into a schedulable resource.
\nNoam Shazeer, “Fast Transformer Decoding: One Write-Head is All You Need,” arXiv, 2019. https://arxiv.org/abs/1911.02150 ↩
\nWoosuk Kwon et al., “Efficient Memory Management for Large Language Model Serving with PagedAttention,” SOSP, 2023. https://arxiv.org/abs/2309.06180 ↩ ↩2
\nIn Gim et al., “Prompt Cache: Modular Attention Reuse for Low-Latency Inference,” MLSys, 2024. https://arxiv.org/abs/2311.04934 ↩
\nYuhan Liu et al., “CacheGen: KV Cache Compression and Streaming for Fast Large Language Model Serving,” SIGCOMM, 2024. https://arxiv.org/abs/2310.07240 ↩
\nThe AI hardware landscape is undergoing a transformation. While NVIDIA maintains its grip on approximately 86-92% of the AI accelerator market, a constellation of alternatives has emerged, each with distinct architectural philosophies and target workloads. This diversification matters for engineers who need to optimize for cost, latency, throughput, or specific model architectures.
\nNVIDIA’s dominance in AI accelerators stems from a decade of CUDA ecosystem development and first-mover advantage in deep learning. The company’s H100 and newer Blackwell GPUs remain the default choice for most organizations. However, several factors are driving diversification:
\nSupply constraints: Morgan Stanley analysts reported in November 2024 that all of NVIDIA’s 2025 chip production was already sold out. Organizations unable to secure H100/H200 allocations must look elsewhere.
\nCost pressure: Inference costs can exceed training costs by 15x over a model’s lifetime, according to OpenAI’s 2024 figures. At $6.98-7.57 per H100 GPU-hour on major cloud providers, inference-heavy workloads demand alternatives.
\nArchitectural mismatch: GPUs are general-purpose parallel processors. Workloads with predictable memory access patterns or specific numerical precision requirements can benefit from purpose-built silicon.
\nVendor lock-in concerns: Major cloud providers and AI labs are developing custom chips. JPMorgan projects that custom chips from Google, Amazon, Meta, and OpenAI will account for 45% of the AI chip market by 2028, up from 37% in 2024.
\nThe result is a market where engineers can choose hardware optimized for their specific constraints rather than defaulting to NVIDIA.
\nGoogle’s Tensor Processing Units represent the most mature alternative to NVIDIA GPUs for large-scale AI workloads. Unlike GPUs, TPUs are application-specific integrated circuits built around systolic arrays optimized for matrix multiplication.
\nAt the core of every TPU sits a Matrix Multiply Unit (MXU) composed of multiply-accumulate units arranged in a systolic array. The term “systolic” refers to the rhythmic data flow through the structure, analogous to blood pumping through the heart. This architecture exploits a fundamental property of matrix multiplication: it requires O(n^3) compute for O(n^2) bytes of data, making it compute-bound rather than memory-bound when hardware is designed correctly.
\n![\"Weight-Stationary](\"https://blog.ecitis.org/feeds/figures/ai-hardware-landscape-0.webp\")
The weight-stationary dataflow pattern works as follows: engineers preload the weights of matrix B into the individual multiply-accumulate units arranged in a grid. Matrix A’s activation values enter from the left edge and flow horizontally across the array. Each MAC unit multiplies its stored weight by the incoming activation, adds the result to a partial sum arriving from above, and passes both the activation (horizontally) and updated partial sum (vertically) to neighboring units. This arrangement eliminates intermediate memory writes for the entire matrix multiplication.
\nThe original TPU v1 contained a 256x256 array of 8-bit multiply-accumulate units, yielding 65,536 MACs. Because a TPU runs at 700MHz, a TPU can compute 92 TOPS in the matrix unit. During execution of this massive matrix multiply, all intermediate results pass directly between 64K ALUs without any memory access, reducing power consumption substantially compared to architectures that require memory round-trips.
\nThe pipelining characteristics matter for understanding performance. Systolic arrays are heavily pipelined: given that the array is 256 units wide, it takes 256 cycles from when the first element enters until it exits. Twice that many cycles for all data to flow through. However, at peak utilization, all 65,536 processors operate simultaneously.
\nThe systolic array’s weakness emerges with dynamic or irregular computation patterns. Because data flows through the grid on a fixed schedule, the architecture struggles with conditional execution, sparse matrices (unless using SparseCore), and operations that require random access patterns. This inflexibility trades generality for extreme efficiency on its target workload: dense matrix multiplication with predictable access patterns.
\nTPUs were codesigned with the XLA (Accelerated Linear Algebra) compiler to achieve their performance characteristics. The compilation process involves several stages:
\nLazy Evaluation and Graph Tracing: Operations are not executed immediately. Instead, PyTorch/XLA or JAX records operations in an intermediate representation (IR) graph. This process is called “tracing.”
\nHLO Generation: When results are needed (printing a tensor, saving a checkpoint, or at an explicit synchronization point), the accumulated IR graph converts into HLO (High-Level Opcodes), a representation specific to the XLA compiler.
\nXLA Optimization: The XLA compiler performs operator fusion, memory layout optimization, and parallelization, then compiles to machine code for the target device. Compiled graphs are cached, so subsequent executions with the same computation graph and input shapes reuse the optimized binary.
\nFor multi-chip scaling, Google’s answer is to make the XLA compiler responsible for coordinating communication between chips. With parallelism dimensions specified by researchers (DP, FSDP, TP, number of slices), the XLA compiler inserts the appropriate hierarchical collectives for the TPU topology. The GSPMD system (Xu et al., 2021) enables large-scale training with minimal code changes.
\nA simple JAX example demonstrates the programming model:
\nimport jax\nimport jax.numpy as jnp\n\ndef multiply(x, y):\n return jnp.einsum('bf,fd->db', x, y)\n\n# XLA compiles this function and caches the result\ny = jax.jit(multiply)(jnp.ones((128, 256)), jnp.ones((256, 16), dtype=jnp.bfloat16))By default, matrix multiplication in JAX on TPUs uses bfloat16 with float32 accumulation. This can be controlled with the precision argument on relevant functions (matmul, dot, einsum).
TPU interconnect topology directly impacts collective operation performance.
\n2D Torus (TPU v2, v3, v5e, v6e): Each chip connects to its four nearest neighbors (north, south, east, west). The links wrap around at boundaries, creating a donut-shaped logical topology that eliminates edge chips with fewer connections. A 16x16 grid of 256 TPUs provides uniform bandwidth and latency regardless of which two chips communicate.
\n3D Torus (TPU v4, v5p, v7): Each chip connects to six neighbors along three axes. A TPU rack consists of 64 TPUs connected in a 4x4x4 configuration. The composition resembles a Rubik’s Cube, with each TPU chip having 6 ICI (Inter-Chip Interconnect) links in ±X, ±Y, ±Z directions. TPU v5p achieved approximately 4.45 exaflops across 8,960-chip pods using 16x20x28 superpod configurations.
\nThe 3D torus increases bisection bandwidth compared to 2D, which matters for all-to-all communication patterns. Google’s Optical Circuit Switches (OCS) enable flexible topology configuration, including twisted torus variants with better bisection properties. Twisting the torus brings the largest benefit for tensor parallel (TP) operations since there are multiple all-gather and reduce-scatter operations per layer.
\nUnlike all-reduce used in backpropagation, which maps well to 2D and 3D tori, all-to-all patterns strain bisection bandwidth. The twisted torus can reduce the worst-case number of hops, improving all-to-all collective throughput.
\nInside the MXU, multiplications occur in bfloat16 format while accumulations use full FP32 precision. This design choice has significant implications.
\nBfloat16 uses one sign bit, eight exponent bits, and seven mantissa bits. Because it has the same exponent size as float32, it exhibits identical behavior for underflows, overflows, and other numeric instabilities during training. Unlike FP16, which typically requires loss scaling, BF16 comes close to being a drop-in replacement for FP32.
\nThe wide dynamic range makes BF16 highly resistant to overflow and underflow, at the cost of reduced precision from the 7-bit mantissa. This tradeoff works well for neural network training where the exact value matters less than staying within a reasonable range.
\nOne caveat: while BF16’s stability helps pre-training, its low precision can cause rounding errors that accumulate. Modern RL frameworks using different engines for training and inference may see subtle differences in their implementation lead to different rounding errors, creating training-inference mismatch (arXiv
.26788).\nCheckpoints from TPU training can be deployed on other hardware platforms (CPU or GPU inference) without extensive manual conversions.
\nTPU v5e targets cost-sensitive inference and smaller training workloads:
\nTPU v5p is designed for large-scale training:
\nTrillium (TPU v6e), generally available since late 2024, represents an architectural inflection point:
\nIronwood (TPU v7) reached general availability in Q4 2025 with 4,614 TFLOPS peak performance.
\nMLPerf 4.1 training benchmarks show Trillium delivers up to 1.8x better performance-per-dollar compared to TPU v5p and 99% scaling efficiency across data-center networks using Cloud TPU multislice technology, outperforming the 94% scaling efficiency of v5p clusters within a single ICI domain.
\nBERT training completes 2.8x faster on TPUs than on A100 GPUs, while T5-3B model training finishes in 12 hours versus 31 hours on comparable GPU infrastructure. MLPerf results show TPU v5e leading in 8 of 9 training categories.
\nFor inference, MLPerf 5.0 shows Trillium delivering 3.5x throughput improvement for queries/second on Stable Diffusion XL compared to TPU v5e. The cost to generate 1000 images is 22 cents on Trillium, 35% less than v5e.
\nGoogle’s TPU v5e reaches similar throughput to H100 by using more chips at lower per-chip speed. Eight TPU v5e chips generate approximately 2,175 tokens/sec on Llama2-70B at a cost of $11/hour, whereas 8 H100 GPUs cost an order of magnitude more.
\nOne computer vision startup reported switching from 128 H100s to TPU v6e and reducing their monthly inference bill from 89K. Midjourney reportedly moved from NVIDIA A100/H100 clusters to TPU v6e pods, dropping monthly spend from approximately 700K.
\nCerebras takes the opposite approach from multi-chip systems: instead of connecting many small chips, they build single chips the size of entire silicon wafers.
\nThe WSE-3, powering the CS-3 system, occupies 46,225 mm^2 of silicon, roughly 57 times larger than NVIDIA’s H100 (826 mm^2). Built on TSMC 5nm, it contains:
\nBuilding a wafer-scale chip requires solving the yield problem that killed previous attempts at wafer-scale integration. The WSE-3 has a die area of 462 cm^2, resulting in higher defect probability than smaller dies where yields typically exceed 90%.
\nCerebras addresses this through several mechanisms:
\nFine-grained cores: Each WSE-3 core occupies 0.05mm^2, while an H100 SM core is 6mm^2. The smaller the core, the better fault tolerance becomes.
\nRedundant mesh routing: A mesh topology improves resilience against manufacturing defects. Cerebras includes redundant links and cores across the wafer. When defective regions are detected, the hardware driver performs a remapping process, reconfiguring the interconnect to bypass faulty areas and preserve a virtually intact two-dimensional mesh topology. This process hides defects from developers, who program the system as if it were built on an ideal mesh network.
\nIntelligent sparing: Unlike previous approaches requiring massive redundancy overhead, the architecture achieves high yield with approximately 1% spare cores through intelligent routing that leverages nearby cores to replace defective units.
\nDistributed power delivery: The system incorporates over 300 voltage regulation modules distributed across the wafer’s surface, providing redundancy in power delivery and allowing independent regulation for each reticle.
\nIn April 2021, Cerebras announced 100% claimed yield for the WSE-2, achieved by designing a system where any manufacturing defect can be bypassed.
\nThe Cerebras architecture uses fine-grained dataflow compute cores where all computation is triggered by data arrival. The fabric transports both data and associative control directly in hardware. Once cores receive data, the hardware triggers a lookup of instructions to execute.
\nThis addresses the memory wall problem endemic to traditional GPU clusters. The WSE keeps 44 GB of memory directly on the same die as compute cores, eliminating the bottleneck of shuttling data between HBM and compute units. At the system level, bandwidth reaches 20 PB/s.
\nFor models exceeding on-chip capacity, Cerebras developed weight streaming execution. Rather than fitting the entire model on-chip, this mode loads the neural network one layer at a time.
\nCerebras stores all model weights externally in MemoryX units and streams weights onto the CS-3 as needed to compute each layer. The weights are never stored on the system, not even temporarily. As weights stream through, the CS-3 performs computation using the underlying dataflow mechanisms. Each individual weight triggers computation as an AXPY operation. Once complete, the weight is discarded and hardware moves to the next element.
\nMemoryX configurations scale from 24TB and 36TB for enterprise customers to 120TB and 1,200TB for hyperscalers. This allows a single CS-3 system to train models up to 24 trillion parameters.
\nThe Cerebras compiler extracts the operation graph from code and aligns operations with compatible kernels in the Cerebras Software Platform. Each matched kernel corresponds to a layer in the network’s dataflow graph.
\nCerebras developed MACH (Multiple-Architecture Compiler for Advanced Computing Hardware) specifically for massively-parallel, spatial, dataflow architectures. Additionally, research has introduced SPADA, a spatial dataflow architecture programming language with a rigorous dataflow semantics framework defining routing correctness, data races, and deadlocks. SPADA enables developers to express complex parallel patterns in 6-8x less code than CSL with near-ideal weak scaling.
\nCerebras reports inference performance of 2,100 tokens/second on Llama 3.2 70B, 16x faster than GPU solutions and 68x faster than hyperscale clouds as measured by Artificial Analysis. For Llama 3.1-405B, Cerebras Inference generates 969 output tokens per second at 128K full context length and 16-bit precision.
\nFor Llama 4 Scout, Cerebras achieves over 2,600 tokens per second, 19x faster than the fastest GPU solutions per Artificial Analysis verification.
\nCerebras benchmarked the CS-3 at over 21x faster inference than NVIDIA’s Blackwell B200 GPU running Llama 3 70B with 1024 input and 4096 output segment lengths. Using SemiAnalysis benchmarks, CS-3 is 32% lower cost than B200 while delivering results 21x faster, accounting for both capex and opex including energy costs.
\nA full cluster of 2048 CS-3s delivers 256 exaflops of AI compute and can train Llama2-70B from scratch in less than a day.
\nWafer-scale architecture excels when model weights fit in on-chip memory and memory bandwidth dominates performance. Large language model inference, where the same weights are reused across many tokens, is a natural fit. The WSE-3 was recognized by TIME Magazine as a Best Invention of 2024.
\nThe tradeoff is flexibility. You cannot incrementally add compute; you either use the full wafer or you do not.
\nGroq builds hardware specifically for inference, not training. Their Language Processing Unit (LPU) takes a fundamentally different architectural approach from both GPUs and other accelerators.
\nGroq’s LPU architecture is built on a central premise: deterministic execution enables optimizations impossible on dynamically scheduled systems. The LPU can achieve deterministic execution by avoiding traditional reactive hardware components (branch predictors, arbiters, reordering buffers, caches) and having all execution explicitly controlled by the compiler.
\nThe LPU is a VLIW-like (Very Long Instruction Word) pipeline that processes one instruction stream at a time. Unlike GPUs with many cores and thread contexts, Groq feeds AI model tokens through a single, wide pipeline of functional units, executing all operations in lock-step with no kernel switching. Every clock cycle performs useful work.
\nThe compiler pre-computes the entire execution graph, including inter-chip communication patterns, down to individual clock cycles. This static scheduling eliminates non-determinism. If Groq’s compiler says a task will take 28.5 milliseconds, it takes exactly 28.5 milliseconds, every time. This predictability is valuable for real-time systems where tail latency is a critical metric.
\nGroq’s initial name for their ASIC was the Tensor Streaming Processor (TSP), later rebranded as the LPU. The TSP features a functionally sliced microarchitecture where memory units are interleaved with vector and matrix computation units.
\nUnlike systolic arrays where data flows through a fixed grid, tensor streaming processors use a “data-stream” design where tensors flow through functional units in a more flexible pattern. This enables tensor parallelism where individual operations distribute across multiple LPUs so single forward passes complete faster, rather than processing more requests in parallel.
\nThe first-generation TSP yields computational density exceeding 1 TeraOp/s per square mm of silicon for its 25x29mm 14nm chip operating at 900 MHz nominal clock frequency. The second-generation LPU v2 will use Samsung’s 4nm process node.
\nThe LPU uses SRAM as primary weight storage, not cache, with approximately 230 MB per chip. This is fundamentally different from GPU architectures that use HBM.
\nSRAM is up to 100x faster than the HBM found in GPUs. This direct access allows compute units to pull in weights at full speed. There are no caches to miss, no external memory delays to manage. The Groq compiler can plan the exact execution path of every instruction before the chip runs.
\nThe tradeoff: no useful models fit on a single chip. Groq systems connect hundreds of LPUs with tensor parallelism. For the Mixtral model, Groq connects 8 racks of 9 servers each with 8 chips per server, totaling 576 chips to serve one model instance. The significant cost of SRAM and its lower capacity compared to DRAM present obstacles.
\nGroq’s architecture is optimized for “Batch Size 1.” Because memory bandwidth is so high and overhead so low, the LPU processes a single user’s request with maximum efficiency without waiting for other requests.
\nOn GPUs, achieving ultra-low latency requires batch size 1, which makes the GPU expensive per token because most processing power sits idle waiting for memory. The LPU achieves 300-500 tokens per second while keeping its internal pipeline nearly 100% full at batch size 1.
\nThis design choice means Groq is not competitive architecturally for throughput-optimized scenarios where batching many requests together amortizes memory access costs. Groq targets latency-critical applications.
\nArtificial Analysis independently benchmarked Groq serving Llama 3.3 70B at 1,665 output tokens per second using speculative decoding, a 6x improvement over their previous 250 T/s endpoint without speculative decoding.
\nSpeculative decoding uses a smaller “draft model” (e.g., Llama 8B) to rapidly guess subsequent tokens, which the primary model then verifies. Verification is faster than generation. Groq implemented this without compromising response quality per independent evaluations.
\nOther benchmarks:
\nGroq offers Llama-3.3-70B-Specdec at 0.99 per million output tokens.
\nGroq is inference-only. You cannot train or fine-tune models on LPUs. The initial capital expenditure for a Groq rack is high due to requiring hundreds of chips per model instance. However, the company claims near-100% compute utilization during inference results in lower energy cost per token than GPUs.
\nIn December 2025, NVIDIA agreed to purchase assets from Groq for approximately $20 billion in what Groq described as a non-exclusive licensing deal.
\nApple’s M-series chips offer a different value proposition: running AI workloads on hardware that millions of people already own.
\nEach M-series chip includes a dedicated Neural Engine for accelerating machine learning operations. The M4 Neural Engine performs 38 trillion operations per second (TOPS), 60x faster than the first Neural Engine in A11 Bionic. For comparison, M1’s Neural Engine achieved 11 TOPS, while M2 and M3 reached 15.8 TOPS.
\nThe Neural Engine’s design favors specialized convolutional and quantized operations. Large transformer-based LLMs depend heavily on dense matrix multiplications more efficiently handled by GPUs or CPUs, which is why full LLM execution solely on the Neural Engine remains aspirational in 2025, with current deployments relying on hybrid CPU/GPU/ANE orchestration.
\nApple’s AMX (Advanced Matrix Extensions) supports fixed matrix dimensions (e.g., 4x4 or 8x8) for operations. The M4 standardized ARM SME (Scalable Matrix Extension). Core ML blends CPU, GPU, and ANE to create hybrid execution plans exploiting all available engines on a given device.
\nUnlike GPUs, there is no public framework for directly programming the Neural Engine. Developers use Core ML, which handles hardware scheduling transparently.
\nM-series processors use unified memory where CPU, GPU, and Neural Engine share the same pool of high-bandwidth memory. There is no separate “system RAM” and “GPU VRAM.” This eliminates the PCIe bottleneck that limits GPU memory capacity in traditional systems.
\nGraphics resources, textures, images, and geometry data can be shared between CPU and GPU with no overhead since there’s no need to copy data across a PCIe bus. Every component in the SoC has direct access to RAM: Media Engine, Neural Engine, video encode/decode units. Code passes a pointer to data in memory and the hardware unit processes data in place.
\nThe M4 Max provides up to 128 GB of unified memory with 546 GB/s bandwidth. The M3 Ultra in Mac Studio configurations offers up to 192 GB. This enables running models that would require multiple GPUs on conventional hardware:
\nMPS (Metal Performance Shaders) is an abstraction layer translating standard GPU operations into optimized Metal instructions. It enables frameworks like PyTorch and JAX to run on Apple Silicon with minimal code changes.
\nMLX, Apple’s machine learning framework, was designed specifically for Apple Silicon. The key difference is how they handle memory:
\nMPS: Treats the GPU as a separate device following the traditional CUDA model. While it benefits from unified memory eliminating physical data copies, the programming model still conceptually separates CPU and GPU memory spaces.
\nMLX: Natively exploits unified memory at the framework level. Operations can run on CPU or GPU without data movement between memory pools. The framework exposes this capability directly in its API design.
\nBenchmarks show MLX achieves the highest sustained generation throughput for LLM inference on Apple Silicon. In comparative testing, MLX was found to be 3x faster than PyTorch MPS on the same M1-Pro GPU.
\nThe M5 chip (October 2025) provides 19-27% performance improvement over M4 due to increased memory bandwidth (153 GB/s versus 120 GB/s). MLX now takes advantage of Neural Accelerators in M5, which provide dedicated matrix-multiplication operations yielding up to 4x speedup compared to M4 baseline for time-to-first-token.
\nPower consumption provides Apple Silicon’s clearest advantage:
\nResearch introducing “intelligence per watt” as a metric shows 5.3x improvement from 2023-2025, driven by both algorithmic advances and accelerator improvements. Benchmarks show ResNet-50 runs about 3x slower on Apple Silicon than RTX 4090, but with over 80% lower energy consumption.
\nThe M3 Max can generate 30-40 tokens per second with quantized Llama 7B while remaining silent and energy efficient.
\nFor edge deployment, mobile inference, or power-constrained environments, Apple Silicon efficiency matters. The tradeoff is absolute performance: NVIDIA cards remain faster for raw throughput. But for engineers who need local, private inference without dedicated GPU hardware, Apple Silicon provides an accessible path.
\nAMD’s Instinct accelerators offer the most direct competition to NVIDIA in the data center GPU market, though with a significant software ecosystem gap.
\nAMD maintains two distinct GPU architectures:
\nCDNA (Compute DNA): Designed for datacenters, AI, and HPC. Compared to its predecessor GCN, CDNA removed all hardware related to graphics acceleration (graphics caches, tessellation hardware, ROPs, display engine) and added dedicated matrix compute hardware. CDNA has had tensor-like functional units since 2020, with increased throughput and number format support added in CDNA 2 (2021) and CDNA 3 (2023).
\nRDNA (Radeon DNA): Consumer and workstation GPUs with some AI acceleration. RDNA 3 includes Wave MMA (matrix multiply-accumulate) instructions supporting FP16, BF16, INT8, and INT4 data types, improving inference performance compared to RDNA 2. However, RDNA’s AI acceleration is limited compared to CDNA’s dedicated matrix cores.
\nThe CDNA 4 architecture (MI350 series, 2025) adds native FP6 and FP4 support. AMD doubled FP8/BF16 throughput and fine-tuned chiplet designs for larger GPU clusters. FP6 processes at twice the rate of FP8 on AMD architecture, unlike NVIDIA where FP6 processes at the same rate as FP8. MI350 offers up to 288 GB HBM3e memory per GPU.
\nAMD announced UDNA, which will unify RDNA and CDNA into one microarchitecture, ending the split that began in 2019.
\nAMD MI300X (CDNA 3):
\nNVIDIA H100 (Hopper):
\nRaw instruction throughput significantly favors MI300X: at times 5x faster than H100, at worst roughly 40% faster for INT32, FP32, FP16, and INT8 compute.
\nHowever, real-world training shows different results. For BF16, H100 and H200 achieve roughly 720 TFLOP/s against their marketed 989.5 TFLOP/s, while MI300X reaches only 620 TFLOP/s compared to marketed 1,307 TFLOP/s. Despite higher marketed specs, MI300X is 14% slower than H100/H200 in practice for training workloads (SemiAnalysis benchmark, December 2024).
\nMI300X has better memory bandwidth (5.3 TB/s vs 3.35 TB/s for H100) and 192 GB vs 80 GB capacity, but H100 exhibits 57% lower memory latency.
\nFor inference, MI300X delivers 40% lower latency for memory-bound Llama2-70B inference and 2.7x faster time to first token for Qwen models. MI300X performs better than H100 SXM at small and large batch sizes (1, 2, 4, 256, 512, 1024) but worse at medium batch sizes.
\nCost comparison: MI300X processes 1 million tokens at 14.06, creating a 21% cost advantage for AMD.
\nROCm (Radeon Open Compute) is AMD’s answer to CUDA. HIP (Heterogeneous-compute Interface for Portability) is a C++ runtime API and kernel language enabling platform-independent GPU programs that run on both AMD and NVIDIA GPUs.
\nHIP intentionally reuses existing torch.cuda interfaces:
cuda = torch.device('cuda') # Default HIP device\ncuda0 = torch.device('cuda:0') # 'rocm' or 'hip' are not valid, use 'cuda'\n\n# Detecting HIP vs CUDA at runtime\nif torch.cuda.is_available() and torch.version.hip:\n # HIP-specific code\nelif torch.cuda.is_available() and torch.version.cuda:\n # CUDA-specific codeAMD provides HIPIFY tools for translating CUDA code:
\nOn NVIDIA GPUs, HIP is a thin layer over CUDA, so the two code types interoperate on nvcc platforms. Setting HIP_PLATFORM=amd makes hipcc call the clang compiler and ROCclr runtime; HIP_PLATFORM=nvidia makes hipcc call nvcc.
HIP 7.0 (second half of 2025) will align HIP C++ more closely with CUDA semantics, refine error handling, and streamline header structures to reduce effort maintaining portable codebases.
\nPerformance benchmarks in 2025 show CUDA typically outperforms ROCm by 10-30% in compute-intensive workloads, though ROCm has narrowed the gap.
\nEach MI300X has up to seven Infinity Fabric links, each with 16 lanes. Fourth-generation Infinity Fabric supports up to 32 Gbps per lane, yielding 128 GB/s bidirectional bandwidth per link.
\nThe ThinkSystem SR685a V3 includes 8x MI300X GPUs fully interconnected using Infinity Fabric, providing 128 GB/s bandwidth between each of the 8 GPUs for a total of 896 GB/s. Aggregated theoretical bandwidth per GPU reaches 336 GB/s; practical execution yields 310-330 GB/s.
\nxGMI (External Global Memory Interconnect) enables efficient peer-to-peer GPU communication. AMD’s Infinity Fabric links up to eight MI300X or MI355X GPUs in a fully connected mesh.
\nFor cluster scaling, AMD’s high-speed accelerator network consists of GPUs connected via Infinity Fabric mesh for low-latency inter-GPU communication. The backend scale-out network uses PCIe 5.0 NICs with RoCEv2, scaling clusters while minimizing congestion. ND MI300X v5 deployments on Azure scale to thousands of GPUs with 3.2 Tb/s interconnect bandwidth per VM.
\nFifth-generation Infinity Fabric will connect CPUs, GPUs, and accelerators from node to rack scale, forming the backbone of “Helios” rack deployments.
\nAMD holds approximately 7% of the AI GPU market.
\nIntel pursues AI acceleration through two product lines: Gaudi for data center training and inference, and Arc for workstation and consumer applications.
\nThe Gaudi 3, manufactured on TSMC 5nm, uses a different architecture from GPUs:
\nIntel claims Gaudi 3 delivers 50% better average inference performance and 40% better power efficiency than NVIDIA H100 at lower cost. Dell’s AI platform with Gaudi 3 reports 70% better price-performance for Llama 3 80B inference throughput versus H100.
\nGaudi 3 entered volume production in Q3 2024 and is available through OEM systems and IBM Cloud.
\nIntel’s Arc GPUs target workstation AI inference rather than data center training. The Arc Pro B-Series, launched in May 2025:
\nThe oneAPI programming model provides a unified interface across Intel CPUs, GPUs, and accelerators. The oneDNN library and PyTorch 2.7 optimizations support inference on Intel Core Ultra processors and Arc GPUs. The Arc A770 (16 GB) can run Llama2 7B and Llama3 models locally.
\nSeveral companies are developing alternative AI accelerator architectures.
\nSambaNova’s Reconfigurable Dataflow Processing Unit (RDPU) emphasizes software-defined hardware. Their SN40L RDU supports up to 5 trillion parameters in a single system node. The company achieved 129 tokens/second on 405B-parameter models and was named “Most Respected Private Semiconductor Company” at the 2024 GSA Awards.
\nGraphcore’s Intelligence Processing Unit (IPU) emphasizes fine-grained parallelism and in-processor memory. The architecture keeps more of the model on-chip to reduce memory bottlenecks. SoftBank acquired Graphcore in July 2024.
\nLed by chip architect Jim Keller, Tenstorrent designs RISC-V based AI chips. The company raised over 2.6+ billion valuation, with investors including Samsung, Bezos Expeditions, LG Electronics, Hyundai, and Fidelity. Tenstorrent plans to release a new AI processor every two years and has launched Grayskull and Wormhole chips.
\nHardware selection depends on workload characteristics, scale, and constraints.
\nLarge-scale training (100B+ parameters): Google TPUs or NVIDIA H100/H200 remain the practical choices. TPUs offer cost advantages for organizations willing to adopt JAX; NVIDIA provides the most mature ecosystem.
\nMedium-scale training: AMD MI300X provides a cost-effective alternative if your workloads align with ROCm’s supported configurations. Intel Gaudi 3 offers competitive price-performance for supported model architectures.
\nExperimentation and research: Cloud TPU access through Google Cloud, or NVIDIA GPUs through various providers, offer flexibility without capital commitment.
\nLatency-critical inference: Groq’s LPU delivers unmatched speed for supported models. Cerebras CS-3 offers 21x faster inference than Blackwell B200. If your application requires sub-second response times at scale, evaluate both.
\nCost-optimized inference: TPU v5e and Trillium provide strong price-performance for batch inference. Organizations report 60-70% cost reductions migrating from NVIDIA to TPUs.
\nLarge model inference: Cerebras CS-3 handles models that exceed typical GPU memory. The MI300X’s 192 GB HBM enables single-GPU deployment of 70B parameter models.
\nEdge and local inference: Apple Silicon with MLX provides the most accessible path for on-device inference. Intel Arc and Gaudi enable Windows-based local deployment.
\nJAX/TPU:
\nimport jax\nimport jax.numpy as jnp\n\n@jax.jit\ndef matmul(x, y):\n return jnp.matmul(x, y)\n\n# Runs on TPU if available, compiles via XLA\nresult = matmul(jnp.ones((1024, 1024)), jnp.ones((1024, 1024)))PyTorch/ROCm (AMD):
\nimport torch\n\n# Same code as CUDA, HIP translates automatically\ndevice = torch.device('cuda') # Not 'rocm' or 'hip'\nx = torch.randn(1024, 1024, device=device)\ny = torch.randn(1024, 1024, device=device)\nresult = torch.matmul(x, y)\n\n# Check which backend at runtime\nif torch.version.hip:\n print(\"Running on AMD via HIP\")MLX (Apple Silicon):
\nimport mlx.core as mx\n\n# Operations seamlessly use CPU or GPU via unified memory\nx = mx.random.normal((1024, 1024))\ny = mx.random.normal((1024, 1024))\nresult = mx.matmul(x, y)\nmx.eval(result) # Explicit evaluationGPU cloud pricing in 2025:
\nFor most organizations, rental makes more sense than purchase given hardware obsolescence risk and 6-12 month procurement timelines. Hidden costs include data egress fees, storage, and idle time; many teams waste 30-50% of budget on provisioned but unused capacity.
\nThe AI hardware market is fragmenting. NVIDIA’s dominance will likely persist for training workloads requiring maximum flexibility, but specialized inference hardware, cloud TPUs, and alternative architectures are capturing significant workloads. Engineers who understand these options can optimize for their specific constraints rather than defaulting to the most expensive general-purpose solution.
\nAMD’s ROCm platform has matured into a viable alternative for machine learning workloads. With ROCm 7.2 now shipping production-ready support for PyTorch, vLLM, and distributed training on both Linux and Windows, the AMD GPU ecosystem deserves serious consideration for both inference and training deployments. The October 2025 announcement of AMD’s strategic partnership with OpenAI to deploy 6 gigawatts of AMD GPUs signals a significant shift in the AI infrastructure landscape.1
\nThis guide covers everything you need to deploy ML workloads on AMD hardware: the software stack, hardware options, framework support, and practical code examples.
\nROCm (Radeon Open Compute) is AMD’s open-source GPU computing platform. Unlike NVIDIA’s proprietary CUDA ecosystem, ROCm is built on open standards and released under permissive licenses. The stack comprises several layers, from kernel drivers through high-level frameworks.
\n![\"ROCm](\"https://blog.ecitis.org/feeds/figures/amd-rocm-ml-0.webp\")
amdgpu Kernel Driver: The Linux kernel module that communicates with AMD GPUs. This ships with most Linux distributions and handles memory management, command submission, and interrupt handling.
\nHSA Runtime (ROCr): The Heterogeneous System Architecture runtime provides low-level GPU access. Applications rarely interact with this layer directly; it serves as the foundation for higher-level runtimes.
\nHIP Runtime: The primary programming interface for AMD GPUs. HIP provides a CUDA-like API that can target both AMD and NVIDIA hardware from the same source code.
\nROCm Libraries: Optimized implementations of common operations:
\nFramework Integrations: PyTorch, TensorFlow, and JAX all have ROCm backends. These frameworks use MIOpen and rocBLAS under the hood for GPU-accelerated operations.
\nROCm supports both data center accelerators and consumer graphics cards, though with different levels of optimization and testing.
\n![\"Data](\"https://blog.ecitis.org/feeds/figures/amd-rocm-ml-1.webp\")
MI355X: AMD’s current flagship for AI workloads, launched Q3 2025. Built on the CDNA 4 architecture with 256 Compute Units and 288 GB of HBM3e memory at 8 TB/s bandwidth. The MI355X delivers 10.1 PFLOPS at FP8 and 20.1 PFLOPS at FP4/FP6. In benchmarks, the MI355X matches or exceeds NVIDIA B200 systems at high concurrency levels (32-64) for Llama3.1-405B inference.2 The 1400W TDP reflects its position as a high-performance training and inference accelerator.
\nMI350X: The lower-power variant of the MI350 series with the same 288 GB HBM3e and 8 TB/s bandwidth. Both MI350 models feature MXFP6 and MXFP4 datatype support for efficient inference.3
\nMI325X: The 256 GB HBM3e variant of the MI300 series with 6.0 TB/s bandwidth. In MLPerf benchmarks, systems built around the MI325X matched the performance of NVIDIA H200 on Llama fine-tuning tasks.4
\nMI300X: With 192 GB of HBM3 memory and 5.3 TB/s bandwidth, the MI300X remains widely deployed. In MLPerf inference benchmarks, Mango LLMBoost achieved 103,182 tokens per second on 32x MI300X for Llama2-70B, outperforming the previous best result of 82,749 TPS on NVIDIA H100.5
\nMI400 Series (H2 2026): The upcoming CDNA 5 architecture will deliver 432 GB of HBM4 memory at 19.6 TB/s bandwidth, with 40 PFLOPS at FP4. The MI455X targets training and inference, while the MI430X serves HPC workloads. The first 1 GW deployment at OpenAI begins H2 2026 using MI450 GPUs.6
\nMI250/MI250X: Previous generation CDNA 2 accelerators with 128 GB HBM2e. Still supported by ROCm 7.2 and available at lower cost on the secondary market.
\nRX 9070 XT/RX 9070 (RDNA 4): The latest consumer architecture with 16 GB GDDR6 at 640 GB/s bandwidth. The RX 9070 XT delivers 48.7 TFLOPS FP32 and up to 1557 TOPS INT4 with sparsity. Each compute unit includes dedicated AI accelerators, marking AMD’s first consumer GPU with tensor cores for machine learning. ROCm 7.2 supports these cards on both Linux and Windows. In Stable Diffusion XL FP16 testing, the RX 9070 XT is 83% faster than the RX 7800 XT. You can run up to 24B parameter LLM models at practical quantization levels.7
\nRX 7900 XTX/XT (RDNA 3): Consumer cards with up to 24 GB GDDR6. ROCm support is mature; these cards work well for local LLM inference and development. The ROCm llama.cpp builds target gfx1100/gfx1101 architectures.8
\nRadeon AI PRO R9700: Professional card with 32 GB VRAM for larger models without quantization. The R9700 targets AI development workflows that exceed the 16 GB consumer cards.9
\nRadeon PRO W7900: Professional card with 48 GB VRAM. Useful for running larger quantized models locally without the cost of data center hardware.
\nData center MI350/MI355X: Production LLM inference and training, frontier model workloads requiring 288 GB memory per GPU.
\nData center MI300X/MI325X: Production LLM inference, distributed training, memory-bound workloads requiring 192-256 GB VRAM pools.
\nConsumer RDNA 4 (RX 9070 series): Local development, small model fine-tuning, inference with quantized models up to 24B parameters. Native Windows support via ROCm 7.2.
\nConsumer RDNA 3 (RX 7900 series): Local development, inference with quantized models. 24 GB VRAM on the XTX model.
\nHIP (Heterogeneous-compute Interface for Portability) provides a CUDA-like programming model that can compile for both AMD and NVIDIA GPUs. Most CUDA code can be ported with minimal modifications.
\nHIP is a C++ runtime API and kernel language. When targeting AMD GPUs, HIP code compiles to native AMD GPU binaries. When targeting NVIDIA, HIP wraps CUDA operations with thin inline functions, adding negligible overhead.10
\n// HIP kernel - nearly identical to CUDA\n__global__ void vectorAdd(float *a, float *b, float *c, int n) {\n int i = blockIdx.x * blockDim.x + threadIdx.x;\n if (i < n) {\n c[i] = a[i] + b[i];\n }\n}\n\nint main() {\n float *d_a, *d_b, *d_c;\n\n // Memory allocation - same as CUDA\n hipMalloc(&d_a, size);\n hipMalloc(&d_b, size);\n hipMalloc(&d_c, size);\n\n // Kernel launch - same syntax\n vectorAdd<<<blocks, threads>>>(d_a, d_b, d_c, n);\n\n hipDeviceSynchronize();\n hipFree(d_a);\n return 0;\n}ROCm includes two tools for converting CUDA code to HIP:
\nhipify-clang: Uses the Clang compiler to parse CUDA code and perform semantic translation. This approach handles complex code patterns and produces high-quality output. Recommended for large projects.11
\nhipify-perl: Pattern-matching based translation that does not require a working CUDA installation. Faster but less robust than hipify-clang.
\n# Convert a CUDA file to HIP\nhipify-clang cuda_kernel.cu -o hip_kernel.cpp\n\n# Or use the Perl-based tool\nhipify-perl cuda_kernel.cu > hip_kernel.cppWhen porting the HACC physics code (approximately 15,000 lines), AMD reported that 95% of the code converted automatically with hipify-perl.12
\nMost CUDA runtime API calls have direct HIP equivalents:
\ncudaMalloc → hipMalloccudaMemcpy → hipMemcpycudaDeviceSynchronize → hipDeviceSynchronizecudaStream_t → hipStream_tDevice code keywords map directly:
\n__global__, __device__, __shared__ work unchangedthreadIdx, blockIdx, blockDim have hip prefixes available but original names also workWarp Size: NVIDIA GPUs use 32-thread warps; AMD uses 64-thread wavefronts. Code that hardcodes warpSize = 32 will break. Use the runtime query instead:
// Portable warp/wavefront size\nint warpSize;\nhipDeviceGetAttribute(&warpSize, hipDeviceAttributeWarpSize, device);CUDA-Specific Intrinsics: Some CUDA intrinsics lack direct HIP equivalents. Tensor core operations (wmma) require translation to AMD’s matrix core instructions.
\nLibrary Calls: ROCm provides equivalent libraries for most CUDA libraries:
\nFunction signatures differ slightly; wrapper headers can ease the transition.
\nROCm 7.2 is a unified release supporting both Linux and Windows. On Linux, it officially supports Ubuntu 22.04/24.04, RHEL 9.x/10.x, SLES 15 SP7, Debian 13, and Oracle Linux 10. Consumer Radeon GPUs (RX 7000/9000 series) and Ryzen AI APUs are supported on Ubuntu 24.04, RHEL 10.1, and Windows 11.13
\n# Download the installer package\nwget https://repo.radeon.com/amdgpu-install/7.2/ubuntu/noble/amdgpu-install_7.2.70200-1_all.deb\n\n# Install the package manager\nsudo apt install ./amdgpu-install_7.2.70200-1_all.deb\n\n# Update package lists\nsudo apt update\n\n# Install ROCm\nsudo apt install rocm\n\n# Add user to required groups\nsudo usermod -a -G render,video $LOGNAME\n\n# Reboot to load the new kernel modules\nsudo reboot# Download for jammy\nwget https://repo.radeon.com/amdgpu-install/7.2/ubuntu/jammy/amdgpu-install_7.2.70200-1_all.deb\n\nsudo apt install ./amdgpu-install_7.2.70200-1_all.deb\nsudo apt update\nsudo apt install python3-setuptools python3-wheel\nsudo usermod -a -G render,video $LOGNAME\nsudo apt install rocm\nsudo reboot# Install the repo\nsudo dnf install https://repo.radeon.com/amdgpu-install/7.2/el/9.6/amdgpu-install-7.2.70200-1.el9.noarch.rpm\n\n# Clean cache\nsudo dnf clean all\n\n# Install EPEL for dependencies\nwget https://dl.fedoraproject.org/pub/epel/epel-release-latest-9.noarch.rpm\nsudo rpm -ivh epel-release-latest-9.noarch.rpm\n\n# Enable CRB repository\nsudo dnf install dnf-plugin-config-manager\nsudo crb enable\n\n# Install dependencies and ROCm\nsudo dnf install python3-setuptools python3-wheel\nsudo usermod -a -G render,video $LOGNAME\nsudo dnf install rocm\nsudo rebootROCm 7.2 includes Windows support for consumer GPUs. PyTorch runs natively on RX 7000/9000 series without WSL2.14
\n# Install AMD Adrenalin 26.1.1 or later (includes ROCm components)\n# Download from https://www.amd.com/en/support\n\n# Install PyTorch for ROCm on Windows\npip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/rocm7.2ComfyUI is now integrated with ROCm and can be installed via the Adrenalin driver package for Windows users.15
\n# Check GPU detection\nrocminfo\n\n# Verify OpenCL\nclinfo\n\n# Check GPU status\namd-smi\n\n# List available GPUs\nrocm-smi --showidExpected output from rocminfo should list your GPU agent with details like:
Agent 2\n Name: gfx942\n Marketing Name: AMD Instinct MI300X\n Vendor Name: AMD\n ...PyTorch has mature ROCm support. AMD publishes validated Docker images and pip wheels for each ROCm release. ROCm support is upstreamed into the official PyTorch repository, and development is aligned with stable PyTorch releases.16
\nOption 1: Docker (Recommended)
\nDocker provides the most reliable setup, avoiding dependency conflicts:
\n# Pull the official ROCm PyTorch image\ndocker pull rocm/pytorch:rocm7.2_ubuntu24.04_py3.12_pytorch_2.9.1\n\n# Run with GPU access\ndocker run -it --device=/dev/kfd --device=/dev/dri \\\n --group-add video --shm-size=16g \\\n rocm/pytorch:rocm7.2_ubuntu24.04_py3.12_pytorch_2.9.1Option 2: pip Installation
\nFor native installation, use the ROCm-specific wheel:
\n# Create a virtual environment\npython3 -m venv rocm-env\nsource rocm-env/bin/activate\n\n# Install PyTorch for ROCm\npip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/rocm7.2As of PyTorch 2.9, wheel variant support simplifies installation; the correct backend is selected automatically based on detected hardware. ROCm 7.2 supports PyTorch 2.9.1 on both Linux and Windows.17
\nimport torch\n\n# Check if ROCm is available (uses CUDA API naming)\nprint(f\"ROCm available: {torch.cuda.is_available()}\")\nprint(f\"Device count: {torch.cuda.device_count()}\")\nprint(f\"Device name: {torch.cuda.get_device_name(0)}\")\n\n# Run a simple operation\nx = torch.randn(1000, 1000, device='cuda')\ny = torch.matmul(x, x.T)\nprint(f\"Result shape: {y.shape}\")Note that PyTorch uses cuda in its API even when running on AMD GPUs. This maintains compatibility with existing code.
Environment Variables: Some operations require specific settings:
\n# Enable HIP extension for certain operations\nexport PYTORCH_ROCM_ARCH=\"gfx942\" # Set your GPU architecture\n\n# For debugging memory issues\nexport PYTORCH_HIP_ALLOC_CONF=\"garbage_collection_threshold:0.9\"FlashAttention: ROCm includes FlashAttention v2 and v3 implementations. FlashAttention v3 is integrated for AMD GPUs in recent PyTorch ROCm builds.18
\nMixed Precision: AMP (Automatic Mixed Precision) works on ROCm:
\nfrom torch.cuda.amp import autocast, GradScaler\n\nscaler = GradScaler()\n\nwith autocast():\n output = model(input)\n loss = criterion(output, target)\n\nscaler.scale(loss).backward()\nscaler.step(optimizer)\nscaler.update()vLLM is the leading high-throughput LLM inference engine. As of January 2026, ROCm is a first-class platform in the vLLM ecosystem. In mid-November 2025, only 37% of vLLM test groups passed on AMD CI. As of mid-January 2026, 93% of vLLM AMD test groups succeed with daily regression maintenance.19
\nInstallation via Docker:
\nAs of January 6, 2026, users no longer need to build from source. Pre-built official ROCm-enabled vLLM Docker images are available on Docker Hub.20
\n# Official ROCm vLLM image\ndocker pull rocm/vllm-dev:rocm7.2_mi350_ubuntu24.04_py3.12_vllm\n\ndocker run -it --device=/dev/kfd --device=/dev/dri \\\n --group-add video --shm-size=32g \\\n -p 8000:8000 \\\n rocm/vllm-dev:rocm7.2_mi350_ubuntu24.04_py3.12_vllmRunning a Model:
\nfrom vllm import LLM, SamplingParams\n\n# Load model\nllm = LLM(model=\"meta-llama/Llama-3.1-8B-Instruct\")\n\n# Generate\nprompts = [\"Explain quantum computing in simple terms:\"]\nsampling = SamplingParams(temperature=0.7, max_tokens=256)\noutputs = llm.generate(prompts, sampling)\n\nfor output in outputs:\n print(output.outputs[0].text)OpenAI-Compatible Server:
\npython -m vllm.entrypoints.openai.api_server \\\n --model meta-llama/Llama-3.1-70B-Instruct \\\n --tensor-parallel-size 8 \\\n --port 8000ROCm-Specific Optimizations:
\nvLLM V1 on ROCm includes AITER (AI Tensor Engine for ROCm) kernels optimized for MI300X, MI325X, MI350X, and MI355X GPUs. FP8 and FP4 quantization reduces memory usage by 2-4x with minimal accuracy loss. Performance on Llama 3 MXFP4 has improved through AITER optimizations and kernel fusion.21
\nKnown Issue: There is a regression with AITER for MoE models such as Mixtral and DeepSeek-R1. For these models, use the previous release rocm/vllm:rocm7.0.0_vllm_0.11.1_20251103 for better performance.22
llama.cpp provides efficient CPU and GPU inference for GGUF-quantized models. ROCm support is available through the HIP backend.
\nBuilding from Source:
\n# Clone the repository\ngit clone https://github.com/ggerganov/llama.cpp\ncd llama.cpp\n\n# Build with HIP support\ncmake -B build -DGGML_HIP=ON -DAMDGPU_TARGETS=\"gfx942\" -DCMAKE_BUILD_TYPE=Release\ncmake --build build --config Release -j $(nproc)Replace gfx942 with your GPU architecture:
gfx950gfx942gfx90agfx1201gfx1100gfx1101Using Pre-built Binaries:
\nAMD maintains ROCm-optimized llama.cpp releases:
\n# Download from AMD's llama.cpp fork\nwget https://github.com/ROCm/llama.cpp/releases/download/b6652.amd0/llama-b6652-bin-ubuntu-hip-gfx942.tar.gz\ntar -xzf llama-b6652-bin-ubuntu-hip-gfx942.tar.gzRunning Inference:
\n./llama-cli -m models/llama-3-8b-instruct-q4_k_m.gguf \\\n -p \"What is machine learning?\" \\\n -n 256 \\\n -ngl 99 # Offload all layers to GPUPerformance Notes:
\nAMD benchmarks show the MI300X achieving up to 213% higher inference throughput versus the H100 on Llama-3.1-70B-Q4_K_M with flash attention enabled at 4096 prompt size.23
\nTGI supports AMD Instinct MI210, MI250, and MI300 series GPUs.
\nDocker Deployment:
\ndocker run --device /dev/kfd --device /dev/dri \\\n --shm-size 1g -p 8080:80 \\\n -v $PWD/data:/data \\\n ghcr.io/huggingface/text-generation-inference:3.3.5-rocm \\\n --model-id meta-llama/Llama-3.1-8B-InstructConfiguration for Large Models:
\nUse tensor parallelism for models exceeding single-GPU memory:
\ndocker run --device /dev/kfd --device /dev/dri \\\n --shm-size 16g -p 8080:80 \\\n -v $PWD/data:/data \\\n ghcr.io/huggingface/text-generation-inference:3.3.5-rocm \\\n --model-id meta-llama/Llama-3.1-70B-Instruct \\\n --num-shard 8TGI on ROCm includes a custom Paged Attention kernel enabled by default. For configurations outside the supported parameters (bf16/fp16, block size 16, head size 128, max 16k context), it falls back to PagedAttention v2.24
\nBenchmark data from independent testing provides useful guidance for hardware selection.
\nThe MI355X’s 8 TB/s memory bandwidth exceeds the B200’s 8 TB/s and substantially outpaces the H100’s 3.35 TB/s. The MI300X at 5.3 TB/s remains competitive with the H200’s 4.8 TB/s. For memory-bound LLM inference at low batch sizes, this translates to lower latency.25
\nIn benchmarks with Llama3.1-405B, the MI355X delivers up to 2x higher throughput compared to competitive options. At high concurrency levels (32-64), the MI355X with ATOM matches or exceeds B200 systems running SGLang. The MI355X demonstrated a 10% time-to-solution advantage in the MLPerf LoRA fine-tuning benchmark.26
\nFor models requiring multi-GPU deployment, AMD’s large VRAM pools allow single-GPU inference where competitors need tensor parallelism:
\nMI355X GPUs are available at Oracle Cloud, TensorWave, and Vultr. Oracle Cloud offers bare-metal GPU instances with 8 MI355X GPUs per node (2.3 TB total GPU memory), 128 CPU cores, 3 TB DDR system memory, and up to 3.2 Tb/s RDMA bandwidth.30
\nROCm 7.2 has closed the gap with CUDA. vLLM now passes 93% of test groups on AMD CI. PyTorch runs natively on both Linux and Windows. For production deployments with standard configurations, both stacks work reliably. NVIDIA retains an edge in MLPerf training benchmarks, where Blackwell leads on Llama 3.1 403B pretraining.31
\nROCm supports distributed training with PyTorch’s native parallelism primitives. While NVIDIA Blackwell currently leads MLPerf training benchmarks on Llama 3.1 403B pretraining, AMD’s MI325X matches H200 performance on LLM fine-tuning benchmarks, suggesting AMD is approximately one generation behind NVIDIA on training workloads.32
\nStandard PyTorch training loops work unchanged:
\nimport torch\nimport torch.nn as nn\nimport torch.optim as optim\n\nmodel = MyModel().cuda()\noptimizer = optim.AdamW(model.parameters(), lr=1e-4)\ncriterion = nn.CrossEntropyLoss()\n\nfor epoch in range(num_epochs):\n for batch in dataloader:\n inputs, labels = batch\n inputs, labels = inputs.cuda(), labels.cuda()\n\n optimizer.zero_grad()\n outputs = model(inputs)\n loss = criterion(outputs, labels)\n loss.backward()\n optimizer.step()RCCL provides collective operations for multi-GPU training:
\nimport torch\nimport torch.distributed as dist\nfrom torch.nn.parallel import DistributedDataParallel as DDP\n\n# Initialize process group\ndist.init_process_group(backend='nccl') # Uses RCCL on AMD\n\nlocal_rank = int(os.environ['LOCAL_RANK'])\ntorch.cuda.set_device(local_rank)\n\nmodel = MyModel().cuda()\nmodel = DDP(model, device_ids=[local_rank])\n\n# Training loop remains the sameLaunch with:
\ntorchrun --nproc_per_node=8 train.pyFSDP shards model parameters, gradients, and optimizer states across GPUs, enabling training of models larger than single-GPU memory:
\nfrom torch.distributed.fsdp import FullyShardedDataParallel as FSDP\nfrom torch.distributed.fsdp import ShardingStrategy\n\nmodel = MyLargeModel()\n\n# Wrap with FSDP\nmodel = FSDP(\n model,\n sharding_strategy=ShardingStrategy.FULL_SHARD,\n device_id=local_rank\n)PyTorch’s FSDP works well on ROCm. AMD benchmarks show 8x MI300X achieving up to 1.29x better performance compared to 8x H100 when training DeepSeek-V2-Lite.33
\nFSDP Configuration Tips:
\n# Recommended settings for ROCm\nfsdp_config = {\n \"sharding_strategy\": ShardingStrategy.FULL_SHARD,\n \"backward_prefetch\": BackwardPrefetch.BACKWARD_PRE,\n \"forward_prefetch\": True,\n \"limit_all_gathers\": True,\n}AMD provides optimized Docker containers for distributed training:
\n# ROCm PyTorch Training container\ndocker pull rocm/pytorch-training:rocm7.2_ubuntu24.04_py3.12\n\n# Includes torchtitan and Hugging Face AccelerateThe container includes libraries for FSDP training with one-shot and two-shot AllReduce strategies for optimized communication.34
\nROCm provides comprehensive profiling tools for performance optimization.
\nThe latest profiling tool (replacing rocprof v1/v2) offers improved usability:
\n# Profile an application\nrocprofv3 --hip-trace --hsa-trace -o profile_output python train.py\n\n# Collect hardware counters\nrocprofv3 --stats --output-format csv python inference.pyBasic Kernel Profiling:
\n# List available counters\nrocprofv3 --list-counters\n\n# Profile with specific counters\nrocprofv3 --pmc GPU_BUSY,GRBM_COUNT python model.pyTimeline Tracing:
\n# Generate trace for visualization\nrocprofv3 --hip-trace --output-format json python model.py\n\n# View in Perfetto\n# Open https://ui.perfetto.dev and load results.jsonFor detailed kernel analysis:
\n# Collect comprehensive metrics\nrocprof-compute profile -n my_workload -- python train.py\n\n# Analyze results\nrocprof-compute analyze my_workload/\n\n# Generate roofline plot\nrocprof-compute analyze my_workload/ --roofrocprof-compute provides:
\nThe ROCm debugger extends GDB for heterogeneous debugging:
\n# Debug a HIP application\nrocgdb ./my_hip_program\n\n# Set breakpoint in kernel\n(gdb) break myKernel\n(gdb) runNote: On RHEL with SELinux enabled, debugging may hang. Either disable SELinux or configure appropriate policies.36
\nROCm has made substantial progress but some limitations remain.
\nWindows: ROCm 7.2 includes native Windows support for consumer GPUs (RX 7000/9000 series). PyTorch runs without WSL2. The Adrenalin 26.1.1 driver includes ROCm components and ComfyUI integration.37
\nmacOS: Not supported. Apple Silicon users should consider MLX instead.
\nMobile GPUs: Not officially supported by ROCm. Ryzen AI APUs (AI Max 300, AI 400 series) are now supported on both Linux and Windows.38
\nRunning large models on RDNA 3/4 cards with 16-24 GB VRAM can cause instability. The RX 9070 XT’s 16 GB is adequate for models up to 24B parameters at Q4 quantization:
\n# Workarounds for memory pressure\n# For Stable Diffusion / FLUX\npython main.py --lowvram --disable-pinned-memory\n\n# For PyTorch memory management\nexport PYTORCH_HIP_ALLOC_CONF=\"garbage_collection_threshold:0.8,max_split_size_mb:512\"JAX on ROCm is supported for inference only. Training workloads may encounter intermittent errors or segmentation faults.39
\nNot all quantization formats work on ROCm:
\nInstalling multiple ROCm versions can cause amd-smi issues. Stick to one ROCm version per system or use containers for version isolation.
\nTransformers library: Most models work; some custom CUDA kernels may need ROCm equivalents.
\nFlash Attention: Supported via CK (Composable Kernel) implementation. Triton-based FA has lower latency on MI250/MI300 but requires warmup for each new sequence length.
\nHere is a complete example for setting up a production LLM inference endpoint:
\n# Pull the vLLM Docker image\ndocker pull rocm/vllm-dev:rocm7.2_mi350_ubuntu24.04_py3.12_vllm\n\n# Create a deployment script\ncat > deploy.sh << 'EOF'\n#!/bin/bash\ndocker run -d \\\n --name llama3-server \\\n --device=/dev/kfd \\\n --device=/dev/dri \\\n --group-add video \\\n --shm-size=32g \\\n -p 8000:8000 \\\n -v ~/.cache/huggingface:/root/.cache/huggingface \\\n rocm/vllm-dev:rocm7.2_mi350_ubuntu24.04_py3.12_vllm \\\n python -m vllm.entrypoints.openai.api_server \\\n --model meta-llama/Llama-3.1-70B-Instruct \\\n --tensor-parallel-size 4 \\\n --max-model-len 8192 \\\n --gpu-memory-utilization 0.9\nEOF\n\nchmod +x deploy.sh\n./deploy.shTesting the Endpoint:
\nfrom openai import OpenAI\n\nclient = OpenAI(\n base_url=\"http://localhost:8000/v1\",\n api_key=\"not-needed\"\n)\n\nresponse = client.chat.completions.create(\n model=\"meta-llama/Llama-3.1-70B-Instruct\",\n messages=[\n {\"role\": \"user\", \"content\": \"Write a haiku about GPU computing\"}\n ],\n max_tokens=100\n)\n\nprint(response.choices[0].message.content)Monitoring:
\n# Watch GPU utilization\nwatch -n 1 rocm-smi\n\n# Check memory usage\namd-smi monitor -pROCm has evolved from a CUDA alternative requiring substantial effort into a production-ready platform for ML workloads. The MI355X delivers competitive performance against NVIDIA’s Blackwell B200 for LLM inference, particularly at high concurrency levels. The MI300X and MI325X remain strong options for memory-bound workloads. Consumer RDNA 4 cards (RX 9070 series) provide a viable path for local development with native Windows support.
\nKey points to remember:
\nFor organizations evaluating GPU infrastructure, AMD provides a cost-effective alternative with competitive performance. The MI400 series (H2 2026) with 432 GB HBM4 will further close the gap with NVIDIA.
\nAMD and OpenAI Announce Strategic Partnership to Deploy 6 Gigawatts of AMD GPUs ↩
\nAMD Instinct MI355X on OCI Performance & Technical Details ↩
\nIs Nvidia’s Blackwell the Unstoppable Force in AI Training, or Can AMD Close the Gap? ↩
\nAMD launches Instinct MI350 series, confirms MI400 in 2026 with 432GB HBM4 memory ↩
\nROCm 7.2: Smarter, Faster, and More Scalable for Modern AI Workloads ↩
\nAMD enables Windows PyTorch support for Radeon RX 7000/9000 with ROCm ↩
\nSingle Node and Distributed Inference Performance on AMD Instinct MI355X GPU ↩
\nAMD Instinct MI355X on OCI Performance & Technical Details ↩
\nIs Nvidia’s Blackwell the Unstoppable Force in AI Training? ↩
\nAMD ROCm, open source Nvidia CUDA rival, gets massive Windows & Linux improvements ↩
\nAMD Expands ROCm Support to Ryzen AI Max and Radeon RX 9000 Series ↩
\nApple Silicon has transformed what is possible for on-device machine learning. While MLX gets the headlines for LLM inference, Apple’s ML stack runs much deeper. Metal Performance Shaders, CoreML, the Accelerate framework, and various neural network libraries form a layered ecosystem that powers everything from real-time image processing to transformer inference on iPhones.
\nThis guide explores the full Metal ML ecosystem: how PyTorch MPS works under the hood, when to use CoreML versus MLX, how to write custom GPU kernels, and the practical realities of deploying models across Apple platforms.
\n![\"Apple](\"https://blog.ecitis.org/feeds/figures/apple-metal-ml-ecosystem-0.webp\")
Metal Performance Shaders (MPS) is Apple’s framework for optimized GPU compute kernels. Originally focused on image processing and linear algebra, MPS has evolved into a foundational layer for machine learning on Apple platforms.
\nMPS offers pre-built, hardware-tuned kernels for common operations. These kernels are optimized for each GPU family in Apple’s lineup, from the integrated graphics in older Intel Macs to the latest M-series chips. The framework handles the low-level details of GPU programming: memory allocation, command buffer management, and shader compilation.
\nFor machine learning, MPS provides:
\nThese operations form the building blocks that higher-level frameworks like PyTorch and TensorFlow use when running on Apple GPUs.
\nMPSGraph extends MPS with a graph-based execution model. Rather than executing individual operations, you build a computation graph that MPSGraph compiles and optimizes as a unit.
\nimport MetalPerformanceShadersGraph\n\nlet graph = MPSGraph()\n\n// Define input placeholders\nlet inputTensor = graph.placeholder(\n shape: [1, 224, 224, 3],\n dataType: .float32,\n name: \"input\"\n)\n\n// Build operations\nlet conv = graph.convolution2D(\n inputTensor,\n weights: weightsTensor,\n descriptor: convDescriptor,\n name: \"conv1\"\n)\n\nlet relu = graph.reLU(with: conv, name: \"relu1\")At WWDC 2024, Apple introduced several improvements to MPSGraph for transformer models. The new Scaled Dot-Product Attention (SDPA) operation fuses the entire attention computation into a single kernel. Combined with KV-cache support, this provides significant speedups for autoregressive generation.
\nMPS kernels achieve strong performance because they are tuned for Apple’s specific GPU architectures. The Metal GPU Profiler in Xcode shows that well-optimized MPS code typically achieves high ALU utilization with minimal memory stalls.
\nHowever, MPS performance varies by operation type. Large matrix multiplications and convolutions benefit most from GPU acceleration. Smaller operations may run faster on the CPU due to kernel launch overhead.
\nApple contributed the MPS backend to PyTorch in 2022, enabling GPU-accelerated training and inference on Apple Silicon. The backend maps PyTorch operations to MPS kernels and MPSGraph.
\nWhen you move a tensor to the MPS device, PyTorch allocates memory in Metal’s shared memory pool:
\nimport torch\n\n# Check MPS availability\nif torch.backends.mps.is_available():\n device = torch.device(\"mps\")\nelse:\n device = torch.device(\"cpu\")\n\n# Create tensor on MPS device\nx = torch.randn(1000, 1000, device=device)\n\n# Operations execute on GPU via Metal\ny = torch.matmul(x, x.T)The MPS backend implements PyTorch’s ATen operations using two approaches:
\nPyTorch 2.0 expanded MPS coverage to over 300 operators. The top 60 most-used operations are all supported. You can check coverage for specific operations in the PyTorch MPS operator tracking issue.
\nCommon supported operations include:
\nThe MPS backend has several constraints that affect real-world usage:
\nNo float64 support: MPS does not support double precision. Operations requiring float64 will fail or fall back to CPU. This affects some scientific computing workloads.
\nNo distributed training: The NCCL and Gloo backends do not work with MPS. Multi-GPU training is not supported. This limits MPS to single-device workloads.
\nNo Neural Engine access: PyTorch MPS only uses the GPU. The Neural Engine, which can accelerate certain operations more efficiently, remains unused.
\nOperation gaps: Some operations lack MPS implementations. The PYTORCH_ENABLE_MPS_FALLBACK=1 environment variable enables automatic CPU fallback for unsupported operations:
PYTORCH_ENABLE_MPS_FALLBACK=1 python train.pyA notable bug in PyTorch versions before 2.4 caused silent failures when writing to non-contiguous tensors via addcmul_ and addcdiv_ operations. This would cause model weights to stop updating during training without any error message. The fix requires updating to PyTorch 2.4 or later.
Benchmarks show MPS running about 3x slower than an RTX 4090 for equivalent models. However, MPS uses significantly less power, making it suitable for development and smaller-scale training. The unified memory architecture allows loading larger models than would fit in discrete GPU VRAM.
\nCoreML is Apple’s deployment framework for machine learning models. Unlike MLX or PyTorch, CoreML is designed for inference in production applications across all Apple platforms.
\nCoreML sits at the top of Apple’s ML stack. When you load a CoreML model, the framework:
\nThe key insight is that CoreML handles hardware targeting automatically. The same model file runs on an iPhone, iPad, Mac, Apple Watch, or Vision Pro, with CoreML selecting the best execution strategy for each device.
\nThe Apple Neural Engine (ANE) is a dedicated accelerator for matrix operations. It offers higher throughput than the GPU for certain workloads while using less power. CoreML is the primary way to access the ANE.
\nHowever, ANE compatibility is strict. Operations must match specific constraints:
\nApple’s research on deploying transformers to the Neural Engine details the constraints and optimization strategies.
\nThe coremltools Python package converts models from PyTorch, TensorFlow, and other frameworks to CoreML format:
import coremltools as ct\nimport torch\n\n# Load PyTorch model\nmodel = MyModel()\nmodel.eval()\n\n# Create example input\nexample_input = torch.randn(1, 3, 224, 224)\n\n# Trace the model\ntraced_model = torch.jit.trace(model, example_input)\n\n# Convert to CoreML\nmlmodel = ct.convert(\n traced_model,\n inputs=[ct.TensorType(shape=example_input.shape)],\n minimum_deployment_target=ct.target.iOS17\n)\n\n# Save the model\nmlmodel.save(\"MyModel.mlpackage\")Direct conversion from PyTorch is recommended over the older ONNX intermediate format. The PyTorch converter handles more operations and produces better-optimized models.
\niOS 18 introduced stateful models to CoreML. This feature enables KV-cache for transformer inference without manual buffer management:
\nimport coremltools as ct\nfrom coremltools.converters.mil import Builder as mb\n\n# Define state for KV-cache\nkv_cache_state = ct.StateType(\n wrapped_type=ct.TensorType(shape=(batch, heads, seq_len, head_dim)),\n name=\"kv_cache\"\n)\n\n# Convert with state\nmlmodel = ct.convert(\n traced_model,\n states=[kv_cache_state],\n minimum_deployment_target=ct.target.iOS18\n)The state persists across inference calls, avoiding expensive memory allocations for each token generation step.
\nApple’s benchmarks show Llama 3.1 8B running at approximately 33 tokens per second on an M1 Max using CoreML with 4-bit quantization. Smaller models achieve faster speeds. On mobile devices, the Neural Engine enables real-time inference for vision and audio models while maintaining battery efficiency.
\nCoreML and MLX serve different purposes despite both running on Apple Silicon. Understanding their trade-offs helps you choose the right tool.
\nProduction deployment: CoreML integrates with Swift and Objective-C. It is the standard way to ship ML models in iOS, iPadOS, watchOS, tvOS, and visionOS apps.
\nNeural Engine access: CoreML is currently the only way to run models on the ANE. For power-sensitive mobile applications, this matters.
\nHardware abstraction: One model file works across all Apple devices. CoreML handles the details of targeting different chip generations.
\nApp Store ready: CoreML models work within Apple’s sandboxing and code signing requirements.
\nResearch and experimentation: MLX provides a familiar NumPy/PyTorch-like API for rapid prototyping. You can modify models and run experiments interactively.
\nTraining support: MLX supports gradient computation and training. CoreML is inference-only.
\nFine-tuning LLMs: MLX includes tools for LoRA and QLoRA fine-tuning of language models. This is not possible with CoreML.
\nDynamic computation: MLX handles dynamic shapes and control flow naturally. CoreML requires static compilation.
\nUse CoreML when:
\nUse MLX when:
\nUse both when:
\nThe typical workflow: experiment with MLX, export to a standard format, convert to CoreML for deployment.
\nWhen MPS does not provide the operation you need, you can write custom GPU kernels in Metal Shading Language (MSL).
\nMSL is based on C++14 with GPU-specific extensions. Compute kernels are marked with the kernel keyword:
#include <metal_stdlib>\nusing namespace metal;\n\nkernel void vector_add(\n device const float* a [[buffer(0)]],\n device const float* b [[buffer(1)]],\n device float* result [[buffer(2)]],\n uint index [[thread_position_in_grid]]\n) {\n result[index] = a[index] + b[index];\n}The [[buffer(N)]] attributes specify buffer bindings. The [[thread_position_in_grid]] attribute provides the thread’s index in the dispatch grid.
From Swift, you create a compute pipeline and dispatch work:
\nimport Metal\n\n// Get the default GPU\nlet device = MTLCreateSystemDefaultDevice()!\n\n// Load the shader library\nlet library = device.makeDefaultLibrary()!\nlet function = library.makeFunction(name: \"vector_add\")!\n\n// Create compute pipeline\nlet pipeline = try! device.makeComputePipelineState(function: function)\n\n// Create command queue and buffer\nlet commandQueue = device.makeCommandQueue()!\nlet commandBuffer = commandQueue.makeCommandBuffer()!\nlet encoder = commandBuffer.makeComputeCommandEncoder()!\n\n// Set pipeline and buffers\nencoder.setComputePipelineState(pipeline)\nencoder.setBuffer(bufferA, offset: 0, index: 0)\nencoder.setBuffer(bufferB, offset: 0, index: 1)\nencoder.setBuffer(bufferResult, offset: 0, index: 2)\n\n// Calculate thread groups\nlet threadGroupSize = MTLSize(width: 256, height: 1, depth: 1)\nlet threadGroups = MTLSize(\n width: (elementCount + 255) / 256,\n height: 1,\n depth: 1\n)\n\nencoder.dispatchThreadgroups(threadGroups, threadsPerThreadgroup: threadGroupSize)\nencoder.endEncoding()\n\ncommandBuffer.commit()\ncommandBuffer.waitUntilCompleted()Apple provides sample code for implementing custom PyTorch operations with Metal. This allows you to write performance-critical operations in MSL while using PyTorch for the rest of your model.
\nA typical pattern for ML kernels:
\nkernel void fused_silu_multiply(\n device const float* input [[buffer(0)]],\n device const float* gate [[buffer(1)]],\n device float* output [[buffer(2)]],\n uint index [[thread_position_in_grid]]\n) {\n float x = input[index];\n float g = gate[index];\n\n // SiLU: x * sigmoid(x)\n float silu = x / (1.0 + exp(-x));\n\n // Multiply with gate\n output[index] = silu * g;\n}Fusing operations like this reduces memory bandwidth by avoiding intermediate buffers.
\nMSL debugging is challenging. The Xcode GPU Debugger allows stepping through shaders, but only for captured frames. For compute shaders without rendering, you can:
\nBasic Neural Network Subroutines (BNNS) is Apple’s library for CPU-based neural network inference. Part of the Accelerate framework, BNNS provides operations tuned for Apple’s CPU architectures.
\nBNNS makes sense when:
\nCoreML uses BNNS internally for CPU execution paths. You can also use BNNS directly for custom inference pipelines.
\nThe BNNSGraph API, introduced in iOS 17 and expanded in iOS 18, allows you to define entire networks as graphs:
\nimport Accelerate\n\n// Create a graph\nvar graph = BNNSGraph()\n\n// Add layers\nlet convLayer = BNNSGraphAddConvolutionLayer(\n graph,\n inputDescriptor,\n weightDescriptor,\n biasDescriptor,\n outputDescriptor,\n convolutionDescriptor\n)\n\n// Compile the graph\nBNNSGraphCompile(graph, nil)\n\n// Execute\nBNNSGraphExecute(graph, inputBuffer, outputBuffer)BNNSGraph performs several optimizations:
\nThese optimizations happen automatically when you compile the graph.
\niOS 18 added BNNSGraphBuilder, which lets you construct graphs directly in Swift:
\nimport Accelerate\n\nlet builder = BNNSGraphBuilder()\n\nlet input = builder.addInput(shape: [1, 224, 224, 3], dataType: .float)\nlet conv = builder.addConvolution(input, weights: weights, bias: bias)\nlet relu = builder.addActivation(conv, function: .relu)\nlet output = builder.addOutput(relu)\n\nlet graph = try builder.build()This provides a more ergonomic API while still benefiting from graph-level optimizations.
\nAccelerate is Apple’s foundational library for numerical computing. It provides BLAS, LAPACK, vDSP, and other optimized routines that underpin both BNNS and higher-level ML frameworks.
\nThe Basic Linear Algebra Subprograms (BLAS) and Linear Algebra Package (LAPACK) implementations in Accelerate are tuned for Apple hardware:
\nimport Accelerate\n\n// Matrix multiplication using BLAS\nvar C = [Float](repeating: 0, count: m * n)\n\ncblas_sgemm(\n CblasRowMajor, // Row-major order\n CblasNoTrans, // Don't transpose A\n CblasNoTrans, // Don't transpose B\n Int32(m), // Rows of A\n Int32(n), // Columns of B\n Int32(k), // Columns of A / Rows of B\n 1.0, // Alpha\n A, Int32(k), // A and its leading dimension\n B, Int32(n), // B and its leading dimension\n 0.0, // Beta\n &C, Int32(n) // C and its leading dimension\n)These routines automatically use the AMX (Apple Matrix Extensions) coprocessor when available. The AMX provides matrix multiplication throughput roughly 2x higher than standard NEON SIMD instructions.
\nvDSP provides optimized routines for:
\nFor ML workloads, vDSP is useful for audio preprocessing, spectrogram computation, and other signal processing pipelines that feed into neural networks:
\nimport Accelerate\n\n// Compute magnitude spectrum\nvar magnitudes = [Float](repeating: 0, count: fftLength / 2)\nvDSP.squareMagnitudes(\n splitComplex,\n result: &magnitudes\n)\n\n// Convert to decibels\nvDSP.convert(\n amplitude: magnitudes,\n toDecibels: &decibelSpectrum,\n zeroReference: 1.0\n)Accelerate functions are called internally by BNNS, CoreML (for CPU execution), and even MLX. When you see high CPU utilization during model inference, Accelerate routines are often doing the work.
\nFor custom preprocessing pipelines, using Accelerate directly is often faster than equivalent NumPy operations in Python:
\n// Fast image normalization\nvDSP.divide(\n pixels,\n 255.0,\n result: &normalizedPixels\n)\n\nvDSP.subtract(\n normalizedPixels,\n mean,\n result: ¢eredPixels\n)\n\nvDSP.divide(\n centeredPixels,\n stdDev,\n result: &standardizedPixels\n)TensorFlow supports Apple Silicon GPUs through the tensorflow-metal plugin, which implements TensorFlow’s PluggableDevice API.
pip install tensorflow tensorflow-metalThe TensorFlow Metal plugin works but has significant limitations:
\nVersion compatibility: As of early 2025, the plugin requires specific combinations of TensorFlow, Python, and macOS versions. The latest wheels support macOS 12 and Python up to 3.11. Users on macOS 15 with Python 3.12 face compatibility issues.
\nOperation coverage: Not all TensorFlow operations have Metal implementations. Complex numbers (DT_COMPLEX64) are not supported.
\nPerformance variability: For small models or small batch sizes, CPU execution may be faster due to GPU dispatch overhead.
\nTo verify Metal acceleration is working:
\nimport tensorflow as tf\n\n# List physical devices\ndevices = tf.config.list_physical_devices()\nprint(devices)\n# Should show both CPU:0 and GPU:0\n\n# Run a simple operation\nwith tf.device('/GPU:0'):\n a = tf.random.normal([1000, 1000])\n b = tf.matmul(a, tf.transpose(a))\n print(b.device) # Should show GPUFor new projects on Apple Silicon, PyTorch MPS or MLX typically offer better support and performance than TensorFlow Metal. TensorFlow Metal remains useful for existing TensorFlow codebases that need to run on Mac hardware.
\nConverting models to CoreML involves several steps and decisions about optimization.
\nThe recommended path for PyTorch models:
\nimport coremltools as ct\nimport torch\n\nmodel = MyModel()\nmodel.eval()\n\n# Trace or script the model\nexample_input = torch.randn(1, 3, 224, 224)\ntraced = torch.jit.trace(model, example_input)\n\n# Convert with compute units specification\nmlmodel = ct.convert(\n traced,\n inputs=[ct.TensorType(name=\"image\", shape=example_input.shape)],\n compute_units=ct.ComputeUnit.ALL, # CPU, GPU, and Neural Engine\n minimum_deployment_target=ct.target.iOS17\n)For models from other frameworks or ONNX model zoo:
\nimport coremltools as ct\n\n# Load ONNX model\nmlmodel = ct.converters.onnx.convert(\n model=\"model.onnx\",\n minimum_deployment_target=ct.target.iOS16\n)Note that the ONNX path may have more conversion issues than direct PyTorch conversion.
\ncoremltools 7+ provides optimization APIs for quantization:
\nimport coremltools as ct\nfrom coremltools.optimize.coreml import (\n OpLinearQuantizerConfig,\n OptimizationConfig,\n linear_quantize_weights\n)\n\n# Load the model\nmlmodel = ct.models.MLModel(\"model.mlpackage\")\n\n# Configure 8-bit quantization\nconfig = OptimizationConfig(\n global_config=OpLinearQuantizerConfig(mode=\"linear_symmetric\")\n)\n\n# Quantize weights\nquantized_model = linear_quantize_weights(mlmodel, config)\nquantized_model.save(\"model_int8.mlpackage\")For 4-bit quantization (useful for LLMs):
\nfrom coremltools.optimize.coreml import (\n OpPalettizerConfig,\n OptimizationConfig,\n palettize_weights\n)\n\nconfig = OptimizationConfig(\n global_config=OpPalettizerConfig(\n nbits=4,\n mode=\"kmeans\"\n )\n)\n\nquantized_model = palettize_weights(mlmodel, config)Block-wise quantization provides better accuracy for aggressive compression:
\nconfig = OptimizationConfig(\n global_config=OpLinearQuantizerConfig(\n mode=\"linear_symmetric\",\n weight_threshold=512, # Only quantize weights larger than this\n granularity=\"per_block\",\n block_size=32\n )\n)For best results, quantize during training using coremltools.optimize.torch:
\nfrom coremltools.optimize.torch.quantization import (\n LinearQuantizerConfig,\n ModuleLinearQuantizerConfig,\n LinearQuantizer\n)\n\n# Configure quantization\nconfig = LinearQuantizerConfig.from_dict({\n \"global_config\": {\n \"quantization_scheme\": \"symmetric\",\n \"milestones\": [0, 100, 400, 500]\n }\n})\n\n# Create quantizer\nquantizer = LinearQuantizer(model, config)\n\n# Prepare model for quantization-aware training\nquantizer.prepare(example_inputs=example_input)\n\n# Train the model\nfor epoch in range(num_epochs):\n quantizer.step()\n train_one_epoch(model)\n\n# Finalize and convert\nquantizer.finalize()\nmlmodel = ct.convert(model)Deploying ML models across Apple platforms requires understanding the constraints and capabilities of each target.
\nModel size limits: App Store apps have size limits. Use compression and quantization aggressively. Consider downloading models on first launch.
\nMemory constraints: iPhones have limited RAM. The system will terminate apps that use too much memory. Profile your model’s memory footprint.
\nThermal throttling: Sustained inference causes heat buildup. The system reduces performance to manage temperature. Design for burst usage patterns.
\nBackground execution: Background apps have limited CPU/GPU access. Use background tasks API for non-real-time inference.
\nimport CoreML\n\n// Load model with configuration\nlet config = MLModelConfiguration()\nconfig.computeUnits = .cpuAndNeuralEngine // Avoid GPU for background\n\nlet model = try MyModel(configuration: config)macOS has fewer constraints than mobile platforms:
\nFor macOS-only apps, you can use MLX directly instead of CoreML if you prefer its API.
\nApple Watch has the most constrained environment:
\nKeep models small. Quantize aggressively. Consider CPU-only execution:
\nlet config = MLModelConfiguration()\nconfig.computeUnits = .cpuOnly\n\nlet model = try WatchModel(configuration: config)Vision Pro runs visionOS, which supports CoreML with full GPU and Neural Engine access. The M2 chip provides capable ML performance.
\nSpatial computing apps may need to balance ML inference with rendering workloads. Consider using computeUnits = .cpuAndNeuralEngine to leave GPU headroom for graphics.
For apps targeting multiple Apple platforms:
\nMLModel.availableComputeDevices and adjust// Check available compute devices\nlet model = try MyModel()\nlet devices = model.model.availableComputeDevices\n\nif devices.contains(where: { $0 == .neuralEngine }) {\n // Can use Neural Engine\n} else {\n // Fall back to CPU/GPU config\n}The Apple Matrix Coprocessor (AMX) is an undocumented accelerator present in all Apple Silicon chips. While you cannot program it directly, understanding its role helps explain performance characteristics.
\nAMX accelerates matrix multiplication on the CPU. It provides roughly 2x the throughput of NEON SIMD instructions for matrix operations. When you call BLAS routines through Accelerate, AMX handles the heavy lifting.
\nThe only supported way to use AMX is through the Accelerate framework. Direct AMX instructions exist but are undocumented and unsupported. Apple’s BLAS implementation automatically uses AMX when beneficial.
\nThis means CPU-based inference through BNNS or Accelerate benefits from AMX automatically. You do not need to do anything special.
\nEach accelerator has different strengths:
\nCoreML manages this complexity by analyzing your model and routing operations to the most appropriate hardware.
\nApple’s Metal ML ecosystem provides multiple layers of optimization:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Layer | Purpose | When to Use |
|---|---|---|
| CoreML | Production deployment | iOS/macOS/watchOS/visionOS apps |
| MLX | Research and training | Mac-based ML development |
| MPSGraph | GPU compute graphs | Custom inference engines |
| MPS | GPU primitives | Building custom ML ops |
| BNNS | CPU inference | Low-latency, power-sensitive workloads |
| Accelerate | Numerical computing | Preprocessing, custom algorithms |
| Metal | Custom GPU kernels | Operations not in MPS |
For most developers, the right approach is:
\nThe ecosystem continues evolving. WWDC 2024 brought transformer optimizations to MPSGraph. iOS 18 added stateful models to CoreML. Each release improves performance and adds capabilities. Keep your tools updated and follow Apple’s machine learning documentation for the latest guidance.
\nApple released MLX in December 2023 as an open-source array framework built specifically for machine learning on Apple Silicon. Unlike PyTorch with MPS backend or TensorFlow with Metal plugin, MLX was designed from the ground up to exploit the unified memory architecture of M-series chips. The framework has matured through 2024 and 2025, reaching version 0.30+ with support for the M5 chip’s Neural Accelerators announced at WWDC 2025.
\nThis guide covers everything you need to know to start using MLX for machine learning research and inference on your Mac.
\nMLX is an array framework for numerical computing and machine learning. It provides a NumPy-like API with support for automatic differentiation, JIT compilation, and GPU acceleration through Metal. The framework was developed by Apple’s machine learning research team and is actively maintained on GitHub at ml-explore/mlx.
\nMLX follows several design principles that distinguish it from other frameworks:
\nFamiliar API: The Python interface mirrors NumPy closely. If you know NumPy, you can start using MLX immediately. Higher-level neural network APIs in mlx.nn follow PyTorch conventions.
Lazy Evaluation: Computations are not executed immediately. Instead, MLX builds a computation graph that is only evaluated when results are needed. This allows the framework to optimize and fuse operations before execution.
\nUnified Memory: Arrays live in shared memory accessible by both CPU and GPU. There is no need to copy data between devices.
\nComposable Function Transformations: Operations like grad(), vmap(), and compile() can be composed together. You can take the gradient of a compiled function, or compile a vectorized gradient computation.
Multi-Language Support: MLX has bindings for Python, Swift, C++, and C. The same models can run on macOS, iOS, iPadOS, and visionOS.
\nHere is a simple example showing MLX array operations:
\nimport mlx.core as mx\n\n# Create arrays\na = mx.array([1.0, 2.0, 3.0])\nb = mx.array([4.0, 5.0, 6.0])\n\n# Operations work like NumPy\nc = a + b\nd = mx.sin(a) * mx.cos(b)\n\n# Arrays are not computed until needed\nprint(c) # This triggers evaluationThe framework supports all common array operations including broadcasting, slicing, reshaping, and linear algebra routines.
\nThe most significant architectural advantage of MLX comes from Apple Silicon’s unified memory design. On traditional systems with discrete GPUs, data must be copied between CPU RAM and GPU VRAM. This copying introduces latency and limits the effective memory available for large models.
\n![\"Memory](\"https://blog.ecitis.org/feeds/figures/apple-mlx-guide-0.webp\")
On Apple Silicon, the CPU, GPU, and Neural Engine share the same physical memory pool. When you create an MLX array, it exists in this shared space. Any processor can access it directly without copying.
\nimport mlx.core as mx\n\n# Create an array - it lives in unified memory\nx = mx.random.normal((1000, 1000))\n\n# Run on GPU - no copy needed\ny = mx.matmul(x, x.T, stream=mx.gpu)\n\n# Run on CPU - still no copy needed\nz = mx.sum(y, stream=mx.cpu)In MLX, you specify the device when calling an operation, not when creating the array. The array itself has no device affiliation. This eliminates common bugs in PyTorch where tensors end up on the wrong device.
\nThe unified memory model provides practical benefits for running large language models. A Mac with 128GB of unified memory can load models that would require a workstation with a high-end GPU to run on CUDA systems.
\nHowever, there are limits. The GPU cannot typically use more than about 75% of total system memory. A 128GB Mac can allocate roughly 96GB for GPU tasks. This is still substantial compared to the 24GB available on consumer NVIDIA GPUs.
\nMLX uses lazy evaluation, meaning operations are recorded but not executed immediately. Understanding this model is essential for writing efficient MLX code.
\nWhen you write c = a + b, MLX does not compute the sum. Instead, it creates a node in a computation graph with a and b as inputs. The actual computation only happens when you need the result.
import mlx.core as mx\n\na = mx.array([1.0, 2.0, 3.0])\nb = mx.array([4.0, 5.0, 6.0])\n\n# No computation happens here\nc = a + b\nd = c * 2\ne = mx.sum(d)\n\n# Computation happens when we need the value\nprint(e) # Triggers evaluation of entire graphYou can explicitly trigger evaluation with mx.eval():
mx.eval(e) # Force computationLazy evaluation enables memory optimizations. Consider initializing a large model:
\nimport mlx.nn as nn\n\n# Model weights are \"created\" but not allocated\nmodel = LargeModel() # Uses float32 by default\n\n# Update to float16 before evaluation\nmodel.load_weights(\"weights.safetensors\") # Loads as float16\n\n# Only float16 memory is ever allocated\nmx.eval(model.parameters())If evaluation were eager, the model would first allocate float32 weights, then allocate float16 weights, doubling peak memory usage.
\nThe lazy evaluation model allows MLX to fuse operations. Multiple element-wise operations can be combined into a single GPU kernel, reducing memory bandwidth requirements and kernel launch overhead.
\nMLX implements automatic differentiation through function transformations rather than tape-based recording. This approach, inspired by JAX, provides more flexibility and composability.
\nThe mx.grad() function takes a function and returns a new function that computes gradients:
import mlx.core as mx\n\ndef f(x):\n return mx.sum(x ** 2)\n\n# Create gradient function\ngrad_f = mx.grad(f)\n\nx = mx.array([1.0, 2.0, 3.0])\nprint(grad_f(x)) # [2.0, 4.0, 6.0]Unlike PyTorch, there is no backward() method, no zero_grad(), no requires_grad property, and no detach(). Gradients are computed by transforming functions.
Computing both the function value and gradient is common in optimization. Rather than calling the function twice, use value_and_grad():
def loss_fn(model, x, y):\n pred = model(x)\n return mx.mean((pred - y) ** 2)\n\n# Get both loss value and gradients\nloss_and_grad_fn = mx.value_and_grad(model, loss_fn)\nloss, grads = loss_and_grad_fn(model, x, y)Function transformations compose naturally. You can compute the gradient of a gradient:
\ndef f(x):\n return x ** 3\n\ngrad_f = mx.grad(f) # 3x^2\ngrad2_f = mx.grad(grad_f) # 6x\n\nx = mx.array(2.0)\nprint(grad2_f(x)) # 12.0MLX provides a compile() transformation that optimizes computation graphs. Compilation fuses operations, eliminates redundant computations, and generates optimized Metal kernels.
import mlx.core as mx\n\ndef model_forward(x, w1, w2):\n h = mx.tanh(x @ w1)\n return h @ w2\n\n# Compile the function\ncompiled_forward = mx.compile(model_forward)\n\n# First call builds and compiles the graph (slow)\ny = compiled_forward(x, w1, w2)\n\n# Subsequent calls reuse compiled code (fast)\ny = compiled_forward(x, w1, w2)The first call to a compiled function is slow because MLX must trace the computation, optimize the graph, and compile Metal shaders. Subsequent calls with the same input shapes reuse the compiled code.
\nCompilation works with other function transformations:
\n# Compile a gradient function\ncompiled_grad = mx.compile(mx.grad(loss_fn))\n\n# Compile a vectorized function\ncompiled_vmap = mx.compile(mx.vmap(batch_fn))Compiled functions cannot contain print statements or other side effects because they are traced with placeholder inputs. For debugging, disable compilation:
\n# Globally disable compilation\nmx.disable_compile()\n\n# Or use environment variable\n# MLX_DISABLE_COMPILE=1 python script.pyMLX uses Metal, Apple’s GPU programming framework, as its backend. Most users never interact with Metal directly, but understanding the integration helps with debugging and optimization.
\nMLX operations run on a default GPU stream:
\nimport mlx.core as mx\n\n# These operations run on the GPU by default\na = mx.random.normal((1000, 1000))\nb = mx.matmul(a, a.T)You can explicitly specify CPU execution:
\n# Force CPU execution\nc = mx.add(a, b, stream=mx.cpu)For operations not covered by built-in primitives, MLX allows custom Metal kernels:
\nimport mlx.core as mx\n\nsource = \"\"\"\n uint elem = thread_position_in_grid.x;\n T tmp = inp[elem];\n out[elem] = tmp * tmp;\n\"\"\"\n\nkernel = mx.fast.metal_kernel(\n name=\"square\",\n input_names=[\"inp\"],\n output_names=[\"out\"],\n source=source,\n)\n\na = mx.array([1.0, 2.0, 3.0, 4.0])\nresult = kernel(inputs=[a], grid=(4,), output_shapes=[(4,)], output_dtypes=[mx.float32])With macOS 26.2 and MLX’s latest versions, the framework can leverage the Neural Accelerators in the M5 chip. MLX uses the Tensor Operations (TensorOps) and Metal Performance Primitives frameworks introduced with Metal 4 to access dedicated matrix multiplication hardware.
\nMLX-LM is the official package for running and fine-tuning large language models on Apple Silicon. It provides a simple interface for loading models from Hugging Face, generating text, and fine-tuning with LoRA.
\npip install mlx-lmfrom mlx_lm import load, generate\n\n# Load a model from Hugging Face\nmodel, tokenizer = load(\"mlx-community/Mistral-7B-Instruct-v0.3-4bit\")\n\n# Generate text\nprompt = \"Explain quantum computing in simple terms:\"\nresponse = generate(model, tokenizer, prompt=prompt, max_tokens=200)\nprint(response)Command-line usage:
\nmlx_lm.generate --model mlx-community/Qwen3-4B-Instruct-2507-4bit --prompt \"hello\"MLX-LM supports most popular LLM architectures including:
\nMost models available on Hugging Face can be loaded directly if they follow standard architectures.
\nQuantization reduces memory usage and increases generation speed. MLX-LM supports 4-bit, 6-bit, and 8-bit quantization:
\n# Convert and quantize a model\npython -m mlx_lm.convert \\\n --hf-path mistralai/Mistral-7B-Instruct-v0.3 \\\n --q-bits 4 \\\n --q-group-size 64Using a quantized model in Python:
\nfrom mlx_lm import load, generate\n\n# Load a pre-quantized model\nmodel, tokenizer = load(\"mlx-community/Mistral-7B-Instruct-v0.3-4bit\")\n\n# Generate as normal\nresponse = generate(model, tokenizer, prompt=\"Hello!\", max_tokens=100)Quantized models from the mlx-community organization on Hugging Face are ready to use without conversion.
\nApproximate memory usage for different quantization levels on a 7B parameter model:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Precision | Memory Usage |
|---|---|
| float32 | ~28 GB |
| float16 | ~14 GB |
| 8-bit | ~7 GB |
| 4-bit | ~3.5 GB |
A 4-bit quantized Llama 3B can generate around 50 tokens/second on recent Apple Silicon.
\nLow-Rank Adaptation (LoRA) enables fine-tuning large models with limited memory by training small adapter matrices instead of full model weights. MLX-LM includes built-in support for LoRA and QLoRA (quantized LoRA).
\nTraining data should be in JSONL format with a “text” field:
\n{\"text\": \"Question: What is the capital of France?\\nAnswer: Paris\"}\n{\"text\": \"Question: What is 2+2?\\nAnswer: 4\"}python -m mlx_lm.lora \\\n --model mlx-community/gemma-3-4b-it-4bit \\\n --train \\\n --data ./data \\\n --adapter-path ./lora_adapters \\\n --lora-r 16 \\\n --lora-alpha 32 \\\n --iters 500 \\\n --batch-size 1 \\\n --learning-rate 2e-4Key parameters:
\n--lora-r: Rank of the LoRA matrices (higher = more capacity, more memory)--lora-alpha: Scaling factor for LoRA updates--lora-layers: Number of layers to apply LoRA (default 16)--batch-size: Training batch size (reduce for memory)--grad-checkpoint: Enable gradient checkpointing for memory savingsWhen using a 4-bit quantized base model, training automatically uses QLoRA:
\n# Using a 4-bit model enables QLoRA automatically\npython -m mlx_lm.lora \\\n --model mlx-community/Llama-3-8B-Instruct-4bit \\\n --train \\\n --data ./data \\\n --adapter-path ./qlora_adaptersMemory comparison for Llama 7B:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Method | Memory Usage |
|---|---|
| Full fine-tuning | ~28 GB |
| LoRA (r=8) | ~14 GB |
| QLoRA (4-bit + LoRA) | ~7 GB |
Generate text with your trained adapter:
\nfrom mlx_lm import load, generate\n\n# Load base model with adapter\nmodel, tokenizer = load(\n \"mlx-community/gemma-3-4b-it-4bit\",\n adapter_path=\"./lora_adapters\"\n)\n\nresponse = generate(model, tokenizer, prompt=\"Your prompt here\")For deployment, merge adapters into the base model:
\npython -m mlx_lm.fuse \\\n --model mlx-community/gemma-3-4b-it-4bit \\\n --adapter-path ./lora_adapters \\\n --save-path ./merged_model \\\n --de-quantize # Optional: convert back to float16MLX-LM includes a built-in server that exposes an OpenAI-compatible API. This allows any tool designed for OpenAI’s API to work with local models.
\nmlx_lm.server --model mlx-community/Mistral-7B-Instruct-v0.3-4bitfrom openai import OpenAI\n\nclient = OpenAI(base_url=\"http://localhost:8080/v1\", api_key=\"not-needed\")\n\nresponse = client.chat.completions.create(\n model=\"mlx-community/Mistral-7B-Instruct-v0.3-4bit\",\n messages=[\n {\"role\": \"user\", \"content\": \"What is machine learning?\"}\n ]\n)\n\nprint(response.choices[0].message.content)For production use cases, consider these community servers:
\nFastMLX: High-performance server with support for vision-language models and efficient resource management. Available at Blaizzy/fastmlx.
\nvllm-mlx: OpenAI-compatible server with continuous batching, MCP tool calling, and multimodal support. Achieves 400+ tokens/second. Available at GitHub.
\nmlx-openai-server: FastAPI-based server supporting LLMs, VLMs (via mlx-vlm), image generation (via mflux), and Whisper transcription. Available on PyPI.
\nBeyond MLX core and MLX-LM, a rich ecosystem of packages has developed for various machine learning tasks.
\nThe mlx-community organization on Hugging Face hosts over 1,000 models converted to MLX format. These include:
\nModels are available in various quantization levels (4-bit, 8-bit, fp16) and can be loaded directly with MLX-LM.
\nThe ml-explore/mlx-examples repository contains standalone examples including:
\nLanguage Models: Transformer training, LLaMA/Mistral text generation, Mixtral 8x7B (MoE), LoRA and QLoRA fine-tuning.
\nImage Generation: Stable Diffusion and SDXL with text-to-image and image-to-image generation. Supports quantization for memory-constrained systems.
\nAudio: OpenAI Whisper for speech recognition, Meta’s EnCodec for audio compression, MusicGen for music generation.
\nVision-Language: CLIP for joint text-image embeddings, LLaVA for text generation from images.
\nMLX-VLM provides inference and fine-tuning for vision-language models:
\nfrom mlx_vlm import load, generate\n\nmodel, processor = load(\"mlx-community/llava-1.5-7b-4bit\")\n\noutput = generate(model, processor, \"path/to/image.jpg\", \"What is in this image?\")\nprint(output)Supported features:
\nMLX Whisper provides speech recognition using OpenAI’s Whisper models:
\nimport mlx_whisper\n\nresult = mlx_whisper.transcribe(\"audio.mp3\")\nprint(result[\"text\"])\n\n# With word-level timestamps\nresult = mlx_whisper.transcribe(\"audio.mp3\", word_timestamps=True)Pre-converted models are available from the Hugging Face MLX Community. For faster transcription, lightning-whisper-mlx provides optimized implementations.
\nThe mlx-examples repository includes Stable Diffusion implementations:
\n# Text to image\npython txt2image.py \"A photo of an astronaut riding a horse on Mars\"\n\n# With quantization for 8GB Macs\npython txt2image.py --quantize \"A sunset over mountains\"\n\n# Image to image\npython image2image.py --image input.png --strength 0.7 \"Make it look like a painting\"Both SD 1.5 and SDXL are supported. Quantization (4-bit text encoder, 8-bit UNet) enables generation on 8GB Macs without swapping.
\nIf you are coming from PyTorch with CUDA, this section covers the key differences and provides practical guidance for porting code.
\nHardware: Any Mac with Apple Silicon (M1, M2, M3, M4, M5 series).
\nSoftware:
\nVerify your Python installation:
\npython -c \"import platform; print(platform.processor())\"\n# Should print \"arm\", not \"i386\"# Install MLX core\npip install mlx\n\n# Install MLX-LM for language models\npip install mlx-lm\n\n# Install additional packages as needed\npip install mlx-whisper # For speech recognition\npip install mlx-vlm # For vision-language modelsNo Device Management: In PyTorch, you explicitly move tensors between devices. In MLX, arrays live in unified memory and you specify the device when calling operations:
\n# PyTorch\nx = torch.tensor([1, 2, 3]).cuda()\ny = x + 1 # Runs on CUDA\n\n# MLX\nx = mx.array([1, 2, 3])\ny = x + 1 # Runs on GPU by default\nz = mx.add(x, y, stream=mx.cpu) # Force CPULazy Evaluation: Operations are not executed immediately:
\n# PyTorch - computed immediately\ny = x + 1\n\n# MLX - creates computation graph\ny = x + 1 # Not computed yet\nmx.eval(y) # Now computed\nprint(y) # Also triggers computationFunction-Based Gradients: No backward() method or gradient tape:
\n# PyTorch\nx = torch.tensor([1.0], requires_grad=True)\ny = x ** 2\ny.backward()\nprint(x.grad)\n\n# MLX\ndef f(x):\n return x ** 2\n\ngrad_f = mx.grad(f)\nx = mx.array([1.0])\nprint(grad_f(x))The mlx.nn module closely follows PyTorch’s API:
# PyTorch\nimport torch.nn as nn\n\nclass PyTorchMLP(nn.Module):\n def __init__(self, in_dim, hidden_dim, out_dim):\n super().__init__()\n self.fc1 = nn.Linear(in_dim, hidden_dim)\n self.fc2 = nn.Linear(hidden_dim, out_dim)\n\n def forward(self, x):\n x = torch.relu(self.fc1(x))\n return self.fc2(x)\n\n# MLX\nimport mlx.nn as nn\nimport mlx.core as mx\n\nclass MLXMLP(nn.Module):\n def __init__(self, in_dim, hidden_dim, out_dim):\n super().__init__()\n self.fc1 = nn.Linear(in_dim, hidden_dim)\n self.fc2 = nn.Linear(hidden_dim, out_dim)\n\n def __call__(self, x):\n x = mx.maximum(self.fc1(x), 0) # ReLU\n return self.fc2(x)Key differences:
\n__call__ instead of forwardmx.maximum(x, 0) instead of torch.relu(x) (or nn.relu(x)).cuda() calls neededWhen porting a trained PyTorch model, you need to convert the weights:
\nimport torch\nimport mlx.core as mx\nimport numpy as np\n\n# Load PyTorch weights\npytorch_weights = torch.load(\"model.pt\", map_location=\"cpu\")\n\n# Convert to MLX format\nmlx_weights = {}\nfor key, value in pytorch_weights.items():\n # Convert to numpy, then to MLX array\n np_array = value.numpy()\n\n # Handle weight format differences (NCHW -> NHWC for convolutions)\n if \"conv\" in key and \"weight\" in key:\n np_array = np.transpose(np_array, (0, 2, 3, 1))\n\n mlx_weights[key] = mx.array(np_array)\n\n# Save in MLX format\nmx.savez(\"model.npz\", **mlx_weights)For LLMs, the mlx_lm.convert script handles this automatically:
\npython -m mlx_lm.convert --hf-path meta-llama/Llama-3-8Bimport mlx.core as mx\nimport mlx.nn as nn\nimport mlx.optimizers as optim\n\nmodel = MLXMLP(784, 256, 10)\noptimizer = optim.Adam(learning_rate=1e-3)\n\ndef loss_fn(model, x, y):\n logits = model(x)\n return mx.mean(nn.losses.cross_entropy(logits, y))\n\nloss_and_grad_fn = nn.value_and_grad(model, loss_fn)\n\nfor epoch in range(num_epochs):\n for x_batch, y_batch in dataloader:\n loss, grads = loss_and_grad_fn(model, x_batch, y_batch)\n optimizer.update(model, grads)\n mx.eval(model.parameters(), optimizer.state)Model Evaluation Mode:
\n# PyTorch\nmodel.eval()\n\n# MLX\nmodel.eval() # Same APISaving and Loading:
\n# Save model weights\nmodel.save_weights(\"model.safetensors\")\n\n# Load model weights\nmodel.load_weights(\"model.safetensors\")Mixed Precision: MLX handles dtypes explicitly:
\n# Convert model to float16\nmodel = model.apply(lambda x: x.astype(mx.float16) if x.dtype == mx.float32 else x)Wrap hot paths in mx.compile():
@mx.compile\ndef training_step(model, optimizer, x, y):\n loss, grads = loss_and_grad_fn(model, x, y)\n optimizer.update(model, grads)\n return lossMLX has lower overhead for small operations than CUDA, but batching still helps:
\n# Less efficient\nfor x in data:\n y = model(x)\n\n# More efficient\ny = model(mx.stack(data))Use 4-bit or 8-bit models for inference when possible:
\nfrom mlx_lm import load\n\n# 4-bit model uses 75% less memory and runs faster\nmodel, tokenizer = load(\"mlx-community/Llama-3-8B-Instruct-4bit\")Check memory usage:
\ninfo = mx.metal.get_memory_info()\nprint(f\"Allocated: {info['allocated'] / 1e9:.2f} GB\")\nprint(f\"Peak: {info['peak'] / 1e9:.2f} GB\")Clear cached memory:
\nmx.metal.clear_cache()Build MLX with Metal debugging for GPU profiling:
\nmkdir build && cd build\ncmake .. -DMLX_METAL_DEBUG=ON\nmake -jThen use Xcode’s GPU profiler to analyze kernel execution.
\nCompiled functions cannot contain print statements. Disable compilation to debug:
\nmx.disable_compile()\n# or\n# MLX_DISABLE_COMPILE=1 python script.pyWhen debugging lazy evaluation issues, force computation:
\nresult = complex_operation(x)\nmx.eval(result) # Force computation\nprint(result) # Now safe to inspectx = mx.array([1.0, 2.0, 3.0])\nprint(f\"Shape: {x.shape}\")\nprint(f\"Dtype: {x.dtype}\")\nprint(f\"Size: {x.size}\")If you encounter memory errors during training:
\nHere is a complete example for running local LLM inference:
\nfrom mlx_lm import load, generate\n\ndef main():\n # Load a quantized model\n print(\"Loading model...\")\n model, tokenizer = load(\"mlx-community/Qwen2.5-7B-Instruct-4bit\")\n\n # System prompt\n messages = [\n {\"role\": \"system\", \"content\": \"You are a helpful assistant.\"},\n {\"role\": \"user\", \"content\": \"Explain how transformers work in 3 sentences.\"}\n ]\n\n # Format with chat template\n prompt = tokenizer.apply_chat_template(\n messages,\n tokenize=False,\n add_generation_prompt=True\n )\n\n # Generate\n print(\"Generating...\")\n response = generate(\n model,\n tokenizer,\n prompt=prompt,\n max_tokens=200,\n temp=0.7\n )\n\n print(response)\n\nif __name__ == \"__main__\":\n main()Complete example for fine-tuning with LoRA:
\nimport json\nimport subprocess\n\n# Step 1: Prepare training data\ntrain_data = [\n {\"text\": \"### Instruction: Translate to French\\n### Input: Hello\\n### Response: Bonjour\"},\n {\"text\": \"### Instruction: Translate to French\\n### Input: Goodbye\\n### Response: Au revoir\"},\n # Add more examples...\n]\n\n# Save training data\nwith open(\"train.jsonl\", \"w\") as f:\n for item in train_data:\n f.write(json.dumps(item) + \"\\n\")\n\n# Step 2: Run training\ncmd = [\n \"python\", \"-m\", \"mlx_lm.lora\",\n \"--model\", \"mlx-community/Mistral-7B-Instruct-v0.3-4bit\",\n \"--train\",\n \"--data\", \".\",\n \"--adapter-path\", \"./adapters\",\n \"--lora-r\", \"8\",\n \"--iters\", \"100\",\n \"--batch-size\", \"1\",\n \"--learning-rate\", \"1e-4\"\n]\n\nsubprocess.run(cmd)\n\n# Step 3: Use the fine-tuned model\nfrom mlx_lm import load, generate\n\nmodel, tokenizer = load(\n \"mlx-community/Mistral-7B-Instruct-v0.3-4bit\",\n adapter_path=\"./adapters\"\n)\n\nprompt = \"### Instruction: Translate to French\\n### Input: Thank you\\n### Response:\"\nprint(generate(model, tokenizer, prompt=prompt, max_tokens=50))Based on benchmarks from late 2025:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Aspect | MLX | PyTorch + CUDA |
|---|---|---|
| Setup complexity | Simple pip install | CUDA toolkit, drivers |
| Memory efficiency | Unified, no copies | Explicit transfers |
| Small batch latency | Lower overhead | Higher kernel launch cost |
| Large batch throughput | Competitive on M2 Ultra+ | Faster on RTX 4090 |
| LLM inference | Optimized for local use | More optimized on server GPUs |
| Training speed | Slower for large models | Faster for production training |
| Debugging | Straightforward | Mature tooling |
MLX is well suited for:
\nPyTorch + CUDA remains better for:
\nCoding agents are not code completion tools. The distinction matters. GitHub Copilot and similar autocomplete systems predict the next few tokens based on cursor context. Coding agents operate differently: they observe your codebase, reason about a task, execute actions through tools, and iterate until the task is complete. This pattern, called the agentic loop, is what separates a tool that suggests code from one that can implement features, fix bugs, and open pull requests autonomously.
\nAs of January 2026, coding agents have crossed a meaningful threshold. Claude Opus 4.5 became the first model to exceed 80% on SWE-bench Verified 1. GPT-5.2 Codex established state-of-the-art on SWE-bench Pro at 56.4% 2. The market has consolidated around a handful of approaches: terminal-native agents (Claude Code, Codex CLI, Gemini CLI), IDE-integrated agents (Cursor, Windsurf, Cline), and cloud-based autonomous agents (Devin, Replit Agent 3, GitHub Copilot coding agent).
\nThis post examines how modern coding agents work, from the core loop architecture to context management strategies, tool implementations, and sandboxing approaches. We will survey the major agents available today and explore their design tradeoffs.
\nEvery coding agent runs some variant of an observe-think-act loop. OpenAI’s documentation on their Codex agent describes this as “unrolling” the loop; the agent repeatedly gathers information, decides what to do, executes an action, and evaluates the result 3.
\n![\"The](\"https://blog.ecitis.org/feeds/figures/coding-agents-explained-0.webp\")
The loop continues until the agent determines the task is complete or reaches a stopping condition (token limit, error threshold, or explicit user interrupt). This architecture differs from single-shot generation in a key way: the agent can course-correct. If it writes code that fails tests, it observes the failure, reasons about the fix, and tries again.
\nThe observation phase involves gathering context about the current state. For coding agents, this means reading files, searching for patterns in the codebase, checking test results, and inspecting error messages. Agents have access to tools that return structured information: file contents, search results, command output.
\nThe thinking phase is where the LLM reasons about what to do next. The model receives the accumulated context from observations and decides which tool to call next. This is not a separate system; it is the model’s native capability for planning and reasoning applied to a tool-use context.
\nThe action phase executes a tool call. The agent might edit a file, run a shell command, search for references, or query a language server. Each action produces output that becomes input for the next observation phase.
\nTools give agents their capabilities. Without tools, an agent can only generate text. With tools, it can modify files, execute code, search repositories, and interact with external systems.
\nFile Operations: Read, write, and edit files. Most agents support both full file writes and targeted edits (replacing specific strings or line ranges). Claude Code implements an Edit tool that performs exact string replacement, reducing the risk of unintended changes 4.
Shell Execution: Run arbitrary commands. This enables testing, building, linting, and any other command-line operation. Agents typically capture stdout, stderr, and exit codes.
\nSearch Tools: Find files by name patterns (glob) and content patterns (grep/ripgrep). Effective search is critical for navigating large codebases. Agents need to find relevant code without reading every file.
\nLSP Integration: Language Server Protocol provides code intelligence; go-to-definition, find-references, hover documentation, and symbol search. OpenCode and Claude Code both integrate LSP for structured code navigation 5.
\nMCP (Model Context Protocol): Anthropic’s open standard for connecting AI assistants to external tools and data sources. Both Claude Code and Gemini CLI support MCP, enabling integration with systems like Jira, GitHub, and custom APIs 6.
\nAgents rely on well-structured tool descriptions to use tools correctly. Each tool has a name, description, and parameter schema. The quality of these descriptions directly affects agent performance. Vague descriptions lead to incorrect tool usage; overly complex schemas increase error rates.
\nExample tool schema structure:
\n{\n \"name\": \"edit_file\",\n \"description\": \"Replace exact string matches in a file\",\n \"parameters\": {\n \"file_path\": \"Absolute path to the file\",\n \"old_string\": \"Exact text to find and replace\",\n \"new_string\": \"Replacement text\"\n }\n}Large codebases exceed context window limits. A moderately sized project might contain millions of tokens across thousands of files. Agents need strategies to work within context constraints while maintaining coherent understanding of the task.
\nAider pioneered the repository map approach: generating a compact representation of the codebase structure, including file paths, function signatures, and class definitions 7. This map fits in context and provides the agent enough information to know which files to read for detailed work.
\nCompaction summarizes conversation history when approaching context limits. Rather than failing when the context fills up, the agent condenses older interactions while preserving essential information.
\nOpenAI’s GPT-5.2 Codex is trained specifically for compaction with native compaction capabilities, making it token-efficient in its reasoning while handling long-running coding tasks 8. Anthropic’s Claude Code implements auto-compact at 95% context capacity, summarizing the trajectory of user-agent interactions 9.
\nCompaction strategies vary:
\nClaude Code introduced “MCP Tool Search” in January 2026, implementing lazy loading for AI tools 10. Instead of preloading every tool definition, Claude Code monitors context usage and automatically fetches tool descriptions only when necessary. The token savings are significant: from approximately 134k to 5k in Anthropic’s internal testing. Internal benchmarks show that enabling Tool Search improved the accuracy of Opus 4 on MCP evaluations from 49% to 74%, and for Opus 4.5, accuracy jumped from 79.5% to 88.1%.
\nFor complex tasks, agents can spawn sub-agents that operate in isolated context windows. The parent agent describes a task; the sub-agent explores extensively using its own context, then returns a condensed summary. This pattern appears in systems like Manus and OpenAI’s Codex 11.
\nThe key insight: sub-agents might use tens of thousands of tokens internally but return only 1,000-2,000 tokens of distilled results. This achieves context separation while preserving information.
\nCoding agents execute arbitrary code. They run shell commands, modify files, and interact with external services. This creates security concerns: what prevents an agent from running rm -rf / or exfiltrating sensitive data?
Docker containers provide filesystem isolation, process containment, and resource limits. The agent runs inside a container with access only to the project directory. Docker recently introduced Docker Sandboxes specifically for AI coding agents, with native support for Claude Code and Gemini CLI 12.
\nContainer isolation means the agent can install packages, run code, and modify files within the sandbox without affecting the host system. This approach handles the full environment the agent needs, not just the agent process itself.
\nClaude Code on macOS uses the native sandbox facility to restrict agent actions. This provides lighter-weight isolation than containers but limits what the agent can access.
\nContainer isolation alone does not address all risks. A sandbox controls where code runs and which files an agent can modify. It does not control what the agent is authorized to do across networked systems 13. An agent might have legitimate access to GitHub but use that access in unintended ways.
\nDefense in depth remains necessary: container isolation, network segmentation, explicit permission prompts for sensitive actions, and audit logging.
\n| Claude Code | Codex CLI | Gemini CLI | OpenCode | Aider | Continue | |
|---|---|---|---|---|---|---|
| License | Proprietary | Open Source | Apache 2.0 | MIT | Apache 2.0 | Apache 2.0 |
| Models | Claude 4 | GPT-5.1-Codex | Gemini 3 Flash/Pro | Any (OpenAI, Claude, Gemini, local) | Any (GPT-4, Claude, local) | Any (configurable) |
| Core Tools | Bash, Read, Write, Edit, Grep, Glob, LSP, MCP | Shell, file ops, code exec | Shell, file ops, Search, MCP | Shell, file ops, LSP | Git, file ops, voice | IDE integration, file ops |
| Sandboxing | macOS sandbox, Docker optional | Docker containers | Optional Docker | None (native) | None (native) | None (IDE process) |
| Context Mgmt | Auto-compact at 95% | Compaction (multi-window) | 1M token window | Manual/configurable | Repo map + smart chunking | IDE-managed |
Anthropic’s CLI agent runs in your terminal and integrates with your bash environment. The tech stack is TypeScript, React, Ink, and Bun 4. Design philosophy: low-level and unopinionated, providing close to raw model access without forcing specific workflows.
\nKey characteristics:
\nClaude Code v2.1.0 (January 2026) introduced Automatic Skill Hot-Reload, Skill Context Forking for isolated sub-agent contexts, and Hooks in Skill Frontmatter 10. The Cowork feature brings Claude Code’s agentic capabilities to the Claude desktop app, running locally in an isolated VM with access to local files and MCP integrations 14. Users report 50% to 75% reductions in both tool calling errors and build/lint errors with Claude Opus 4.5 1.
\nOpenAI’s agent runs tasks in isolated cloud sandbox environments, preloaded with your repository. Powered by GPT-5.2 Codex for standard tasks and GPT-5.1-Codex-Max for long-running operations 8.
\nKey characteristics:
\nCodex v0.85.0 (January 2026) introduced app-server v2 with collaboration tool calls emitted as item events, enabling real-time agent coordination rendering. The spawn_agent function now accepts an agent role preset for richer agent control 15. By exposing the CLI as an MCP server and orchestrating with the OpenAI Agents SDK, developers can create deterministic, auditable workflows that scale from a single agent to a complete software delivery pipeline.
Google’s open-source agent (Apache 2.0) brings Gemini models to the terminal. Uses a ReAct (reason and act) loop with built-in tools and MCP support 16.
\nKey characteristics:
\nGemini 3 Flash became available in Gemini CLI in December 2025, achieving 78% on SWE-bench Verified while being 3x faster than the 2.5 series at a fraction of the cost 17. Since launch, the community has contributed over 2,800 pull requests, submitted about 3,400 issues, and given more than 70,000 GitHub stars. The free tier offers 60 requests/minute and 1,000 requests/day with a personal Google account.
\nCursor is a fork of VS Code that integrates AI capabilities directly into the editing experience. Agent is the default mode, designed to handle complex coding tasks with minimal guidance 18.
\nKey characteristics:
\nCursor 2.0 (late 2025) shipped Composer, their own ultra-fast coding model, and an agent-centric interface for running multiple agents in parallel 18. The January 2026 CLI release added Plan mode (/plan or --mode=plan) for approach design before coding, and cloud handoff for background execution. Users can prepend & to any message to send it to a cloud agent, then resume on web or mobile at cursor.com/agents.
Windsurf (by Codeium) is an agentic IDE built for enterprise teams and large codebases. Its Cascade agent plans and executes multi-step changes across repositories 19.
\nKey characteristics:
\nWindsurf’s “Context Awareness Engine” is faster at indexing than Cursor, making it suited for large-scale enterprise projects where the codebase exceeds what other tools can handle. Cascade reasons across entire repositories, determining which files matter for a given task and loading them automatically.
\nCline is an open-source AI coding agent that runs inside VS Code or the terminal. It plans, previews, and applies multi-file changes with approval checkpoints 20.
\nKey characteristics:
\nCline demonstrates high autonomy with multi-step execution, self-correction, and independent task continuation. Its open-source nature and support for multiple AI models offer flexibility for teams that need local-first control over data and models.
\nDevin (by Cognition Labs) is an autonomous AI software engineer that operates as a web app rather than an IDE extension. Users define intent, review a plan, and execution proceeds in the background 21.
\nKey characteristics:
\nDevin can independently create PRs, respond to PR comments, review PRs, and handle Linear tickets when tagged. In 2025, Devin gained multi-agent operation capability, where one AI agent dispatches tasks to other AI agents. Devin Wiki and Devin Search provide machine-generated documentation and codebase querying. Pricing starts at 2.25 per ~15 minutes of active work) or $500/month for teams 21.
\nReplit Agent 3 (September 2025) is Replit’s most autonomous agent, positioned as Agent-first for all builders, not just developers 22.
\nKey characteristics:
\nAgent 3 runs for up to 200 minutes autonomously, handling full tasks with a proprietary testing system that is up to 3x faster and 10x more cost-effective than Computer Use models. For the first time, Agent 3 can build other agents and automations, enabling workflow automation via natural language. In January 2026, Replit reached a $3 billion valuation, with companies like Duolingo and Zillow using the platform 22.
\nGitHub Copilot coding agent works independently in the background to complete tasks like a human developer 23.
\nKey characteristics:
\nThe January 2026 CLI update introduced specialized custom agents: Explore for fast codebase analysis and Task for running commands like tests and builds 23. Visual Studio 2026 shipped with GitHub cloud agent in public preview. Users can delegate UI cleanups, refactors, documentation updates, and multi-file edits while focusing on core development.
\nAmazon Q Developer provides agentic capabilities for the AWS ecosystem 24.
\nKey characteristics:
\nAmazon Q Developer agents can autonomously implement features, document, test, review, and refactor code, and perform software upgrades. The Transformation Agent handles legacy modernization: Amazon used Q’s agents to upgrade 1,000 applications from Java 8 to Java 17, completing work that would have taken months in just two days 24. Free tier includes 50 agentic chat interactions per month; Pro tier is $19/user/month.
\nOpenHands is an open platform for AI-powered coding agents with 65K+ GitHub stars 25.
\nKey characteristics:
\nOpenHands 1.0.0 (January 2026) uses the new software-agent-sdk with optimizations across the app. The platform integrates with GitHub, GitLab, CI/CD, Slack, and ticketing tools. In November 2025, OpenHands raised $18.8M to build the open standard for autonomous software development. AMD partnered with OpenHands for local execution on AI PCs via the Lemonade LLM serving framework 25.
\nOpen-source (MIT license) alternative that supports any model provider: OpenAI, Anthropic, Google, AWS Bedrock, Groq, local models via Ollama 5. Built in Go with a Bubble Tea TUI.
\nKey characteristics:
\nOpenCode separates workflows into “Plan Mode” (read-only analysis) and “Build Mode” (full tool access), acting as both architect and engineer 5.
\nOpen-source (Apache 2.0) pair programming tool focused on git integration. Creates a repository map of function signatures and file structures for intelligent multi-file edits 7.
\nKey characteristics:
\nAider automatically commits changes with sensible messages. Three modes: code (edit), architect (plan), ask (consult without changes) 7.
\nOpen-source (Apache 2.0) IDE extension for VS Code and JetBrains. Architecture splits into core (business logic), extension (IDE-specific), and gui (React UI), communicating via message passing 26.
\nKey characteristics:
\nContinue offers three interaction modes: Chat (discuss without changes), Plan (read-only exploration), Agent (full tool access) 26.
\nAgent system prompts are lengthy and detailed. They specify tool usage rules, safety constraints, output formatting, and behavioral guidelines. The prompt shapes how the agent interprets tasks and uses tools.
\nTool descriptions: Detailed explanations of each tool’s purpose, parameters, and usage patterns. Often includes examples of correct and incorrect usage.
\nSafety rules: Constraints on dangerous operations. “NEVER run force push to main/master.” “Do not commit files that likely contain secrets.”
\nWorkflow guidance: Instructions for common tasks like committing code, creating PRs, or exploring unfamiliar codebases.
\nOutput formatting: How to structure responses, when to use code blocks, and how to communicate progress.
\nMany agents support project-level configuration:
\nagents.md (Codex): Tells the agent how you prefer to codeCLAUDE.md (Claude Code): Project-specific instructions and context.continuerc (Continue): Model and tool configurationThese files let developers customize agent behavior per repository.
\nCoding agents fail. Understanding how they fail helps set appropriate expectations and design better workflows.
\nResearch from CodeRabbit found that AI-generated code produces more issues across categories: 1.75x more logic errors, 1.64x more maintainability problems, 1.57x more security findings, and 1.42x more performance issues compared to human-written code 27.
\nTool calling fails 3-15% of the time in production systems 28. The agent might call the wrong tool, pass incorrect parameters, or misinterpret tool output. Robust agents include retry logic and error handling.
\nResearch analyzing 1,642 multi-agent execution traces found failure rates between 41% and 86.7% across state-of-the-art systems 29. Common issues include missing tool calls, workflow errors, and reasoning failures.
\nAs context fills up, model performance degrades. Quality often drops before hitting the technical limit. The recommendation: implement compaction before hitting the “rot zone,” typically well before maximum context capacity 9.
\n“Ghost debugging” occurs when running the same prompt twice produces different results 28. Traditional debugging approaches fail because the system behavior is non-deterministic. Many fixes are “session patches” that work temporarily but do not persist across sessions.
\nFrameworks simplify agent construction. LangChain and LangGraph provide primitives for tool use, state management, and conversation handling.
\nLangChain recommends LangGraph for production agent implementations. It offers a durable runtime, model/tool swapping without rewrites, and 1000+ integrations 30.
\nThe create_react_agent function provides a standard ReAct pattern:
from langgraph.prebuilt import create_react_agent\nfrom langchain_openai import ChatOpenAI\n\nmodel = ChatOpenAI(model=\"gpt-4o\")\ntools = [search_tool, file_tool, shell_tool]\n\nagent = create_react_agent(model, tools)\nresult = agent.invoke({\"messages\": [(\"user\", \"Fix the failing tests\")]})LangChain’s Open SWE provides an open-source coding agent built on LangGraph with three specialized agents: Manager (entry point), Planner, and Programmer (with sub-agent Reviewer) 30. The entire project is open source and designed for extension.
\nA minimal agent loop requires:
\nThe complexity comes from handling edge cases: malformed tool calls, execution timeouts, context overflow, and graceful degradation.
\nThe benchmark landscape has evolved with more rigorous evaluations. SWE-bench Verified remains the standard, but SWE-bench Pro and Terminal-Bench have emerged to address saturation at the top.
\n| Model | Score |
|---|---|
| Claude Opus 4.5 | 80.9% |
| GPT-5.2 Codex | 80.0% |
| Gemini 3 Flash | 78.0% |
| Gemini 3 Pro | 76.2% |
| GPT-5.1 | 76.3% |
| Verdent | 76.1% (81.2% pass@3) |
| GPT-5 | 74.9% |
Claude Opus 4.5 became the first model to exceed 80% on SWE-bench Verified, solving 405 of 500 real-world coding problems 1.
\nSWE-bench Pro contains 1,865 total tasks across 41 professional repositories, designed to test harder software engineering scenarios 31.
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Model | Score |
|---|---|
| GPT-5.2 Codex | 56.4% |
| GPT-5.1 | 50.8% |
| Claude Opus 4.1 | 23.1% |
| OpenAI GPT-5 | 23.3% |
The gap between SWE-bench Verified (70%+ scores) and SWE-bench Pro (20-56%) reveals that current agents still struggle with professional-grade complexity.
\n| Model | Score |
|---|---|
| Claude Opus 4.5 | 59.3% |
| Gemini 3 Pro | 54.2% |
| GPT-5.1 | 47.6% |
GPT-5.2 High achieved the best security posture with only 16 blocker vulnerabilities per million lines of code, though it generated the highest code volume (974,379 lines) 32. Claude Opus 4.5 and Gemini 3 Pro lead in functional performance at 80.66%.
\nTop-tier models are diverging in specialization: GPT-5 excels at code review and refactoring, while Claude Sonnet 4.5 performs best in coding and tool use 33. Developers often switch between frontier models depending on the task.
\nGartner reported a 1,445% surge in multi-agent system inquiries from Q1 2024 to Q2 2025 34. By 2026, 40% of enterprise applications will feature task-specific AI agents, up from less than 5% in 2025 35. The shift from isolated agents to coordinated teams marks a fundamental change in how organizations approach automation.
\nThe pattern: orchestrator agents coordinate specialist agents (researcher, coder, analyst), each fine-tuned for specific capabilities. Agent design is converging around a Planner and Builder (Execution Agent) loop, which spawns ephemeral Task Agents for sub-routines, all grounded in a Code Execution Sandbox 35.
\nProtocols like Anthropic’s MCP and Google’s Agent-to-Agent Protocol (A2A) establish standards for agent interoperability 34. MCP standardizes how agents access tools and external resources. A2A enables peer-to-peer collaboration, allowing agents to negotiate, share findings, and coordinate without central oversight. Google’s Agent Development Kit (ADK), released in 2025, provides an open-source framework for building multi-agent systems 36.
\nRunning multiple agents on the same codebase requires isolation. Git worktrees enable parallel branches for each task, with work merged back to main 34. Tools like Conductor and Verdent AI support running tasks in parallel. Cursor 2.0 introduced an agent-centric interface for managing multiple agents in parallel with cloud handoff capabilities.
\nGemini 3 offers a 1M token context window. GPT-5.2 Codex includes native compaction for token-efficient reasoning over long-running tasks 8. Claude Code’s MCP Tool Search reduces context usage by 96% (from 134k to 5k tokens) through lazy loading 10.
\nSecurity remains unsolved. Connecting models to tools multiplies risks; indirect prompt injections can cause harmful actions 34. Research analyzing 1,642 multi-agent execution traces found failure rates between 41% and 86.7% across state-of-the-art systems 29.
\nAI agents are projected to generate $450 billion in economic value by 2028, yet only 2% of organizations have deployed them at full scale 35. The market has shipped useful point solutions but has not yet demonstrated reliable autonomy inside complex, decision-rich enterprise workflows.
\nThe trajectory is clear: agents will write more code. The question is whether we can make them reliable enough to trust.
\nAnthropic, “Introducing Claude Opus 4.5,” January 2026. https://www.anthropic.com/news/claude-opus-4-5 ↩ ↩2 ↩3
\nOpenAI, “Introducing GPT-5.2-Codex,” December 2025. https://openai.com/index/introducing-gpt-5-2-codex/ ↩
\nOpenAI, “Unrolling the Codex agent loop,” OpenAI Blog, 2025. https://openai.com/index/unrolling-the-codex-agent-loop/ ↩
\nGergely Orosz, “How Claude Code is built,” The Pragmatic Engineer, 2025. https://newsletter.pragmaticengineer.com/p/how-claude-code-is-built ↩ ↩2
\nOpenCode, “The open source AI coding agent,” 2025. https://opencode.ai/ ↩ ↩2 ↩3
\nAnthropic, “Claude Code overview,” Claude Code Docs, 2025. https://code.claude.com/docs/en/overview ↩
\nAider, “AI Pair Programming in Your Terminal,” 2025. https://aider.chat/ ↩ ↩2 ↩3
\nOpenAI, “GPT-5.2-Codex,” OpenAI, 2025. https://openai.com/index/introducing-gpt-5-2-codex/ ↩ ↩2 ↩3
\nAnthropic, “Effective context engineering for AI agents,” Anthropic Engineering, 2025. https://www.anthropic.com/engineering/effective-context-engineering-for-ai-agents ↩ ↩2
\nVentureBeat, “Claude Code just got updated with one of the most-requested user features,” January 2026. https://venturebeat.com/orchestration/claude-code-just-got-updated-with-one-of-the-most-requested-user-features ↩ ↩2 ↩3
\nLance Martin, “Context Engineering in Manus,” 2025. https://rlancemartin.github.io/2025/10/15/manus/ ↩
\nDocker, “A New Approach for Coding Agent Safety,” Docker Blog, 2025. https://www.docker.com/blog/docker-sandboxes-a-new-approach-for-coding-agent-safety/ ↩
\nArcade Blog, “Why Docker Sandboxes Alone Don’t Make AI Agents Safe,” 2025. https://blog.arcade.dev/docker-sandboxes-arent-enough-for-agent-safety ↩
\nTechRadar, “This is the Claude update I’ve been waiting for - Cowork could reshape how we use AI in 2026,” January 2026. https://www.techradar.com/ai-platforms-assistants/claudes-latest-upgrade-is-the-ai-breakthrough-ive-been-waiting-for-5-ways-cowork-could-be-the-biggest-ai-innovation-of-2026 ↩
\nOpenAI, “Codex Changelog,” January 2026. https://developers.openai.com/codex/changelog/ ↩
\nGoogle, “Gemini CLI,” Google for Developers, 2025. https://developers.google.com/gemini-code-assist/docs/gemini-cli ↩
\nGoogle Developers Blog, “Gemini 3 Flash is now available in Gemini CLI,” December 2025. https://developers.googleblog.com/gemini-3-flash-is-now-available-in-gemini-cli/ ↩
\nCursor, “Changelog,” January 2026. https://cursor.com/changelog ↩ ↩2
\nQodo, “Cline vs Windsurf: Best AI Coding Agent for Enterprise,” 2026. https://www.qodo.ai/blog/cline-vs-windsurf/ ↩
\nQodo, “Cline vs Windsurf,” 2026. https://www.qodo.ai/blog/cline-vs-windsurf/ ↩
\nBuilder.io, “Devin vs Cursor: How developers choose AI coding tools in 2026,” 2026. https://www.builder.io/blog/devin-vs-cursor ↩ ↩2
\nAmerican Bazaar, “AI startup Replit, known for vibe coding, reaches $3 billion valuation,” January 2026. https://americanbazaaronline.com/2026/01/16/ai-startup-replit-known-for-vibe-coding-3-billion-valuation-473395/ ↩ ↩2
\nGitHub Blog, “GitHub Copilot CLI: Enhanced agents, context management, and new ways to install,” January 2026. https://github.blog/changelog/2026-01-14-github-copilot-cli-enhanced-agents-context-management-and-new-ways-to-install/ ↩ ↩2
\nAWS DevOps Blog, “Reinventing the Amazon Q Developer agent for software development,” 2025. https://aws.amazon.com/blogs/devops/reinventing-the-amazon-q-developer-agent-for-software-development/ ↩ ↩2
\nOpenHands, “The Open Platform for Cloud Coding Agents,” 2026. https://openhands.dev/ ↩ ↩2
\nContinue, “Continue Documentation,” 2025. https://docs.continue.dev/ ↩ ↩2
\nThe Register, “AI-authored code needs more attention, contains worse bugs,” December 2025. https://www.theregister.com/2025/12/17/ai_code_bugs/ ↩
\nMichael Hannecke, “Why AI Agents Fail in Production,” Medium, 2025. https://medium.com/@michael.hannecke/why-ai-agents-fail-in-production-what-ive-learned-the-hard-way-05f5df98cbe5 ↩ ↩2
\nMert Cemri et al., “Why Do Multi-Agent LLM Systems Fail?” arXiv, 2025. https://arxiv.org/pdf/2503.13657 ↩ ↩2
\nLangChain, “Introducing Open SWE: An Open-Source Asynchronous Coding Agent,” LangChain Blog, 2025. https://www.blog.langchain.com/introducing-open-swe-an-open-source-asynchronous-coding-agent/ ↩ ↩2
\nScale AI, “SWE-Bench Pro Public Dataset,” January 2026. https://scale.com/leaderboard/swe_bench_pro_public ↩
\nSonar, “New data on code quality: GPT-5.2 high, Opus 4.5, Gemini 3, and more,” January 2026. https://www.sonarsource.com/blog/new-data-on-code-quality-gpt-5-2-high-opus-4-5-gemini-3-and-more/ ↩
\nSWE-rebench, “Leaderboard,” January 2026. https://swe-rebench.com ↩
\nRTInsights, “2026 will be the Year of Multiple AI Agents,” January 2026. https://www.rtinsights.com/if-2025-was-the-year-of-ai-agents-2026-will-be-the-year-of-multi-agent-systems/ ↩ ↩2 ↩3 ↩4
\nThe New Stack, “5 Key Trends Shaping Agentic Development in 2026,” January 2026. https://thenewstack.io/5-key-trends-shaping-agentic-development-in-2026/ ↩ ↩2 ↩3
\nGoogle Developers Blog, “Agent Development Kit: Making it easy to build multi-agent applications,” 2025. https://developers.googleblog.com/en/agent-development-kit-easy-to-build-multi-agent-applications/ ↩
\nRunning inference on edge devices instead of cloud servers addresses four constraints that matter in production systems.
\nLatency: Cloud roundtrips add 100-500ms of network delay before inference even begins. Edge inference on embedded hardware achieves sub-50ms latency for many workloads. Cactus, a Y Combinator startup, demonstrated sub-50ms time-to-first-token for on-device LLM inference in late 2025.1 TinyML solutions on microcontrollers achieve inference latencies as low as 0-5ms.2
\nPrivacy: Data never leaves the device. This simplifies compliance with GDPR, HIPAA, and similar regulations. Medical imaging, financial analysis, and surveillance applications often require on-premise processing.
\nConnectivity: Edge deployment removes the assumption of reliable internet. Factory floors, remote agricultural sites, vehicles in motion, and aircraft cabins all benefit from inference that works without network access.
\nCost: After hardware acquisition, inference is free. No per-token API fees, no bandwidth costs, no cloud compute bills. IDC and Gartner predict that by 2027, over 60% of all AI inference will happen locally rather than in the cloud.3
\nThe edge AI hardware market reached 68.73 billion by 2031 at a 17.46% CAGR.4 Leading mobile processors now achieve 45-50 TOPS of inference capability while optimizing battery life through dedicated engines.4
\n![\"Edge](\"https://blog.ecitis.org/feeds/figures/edge-ai-deployment-0.webp\")
NVIDIA’s Jetson line targets robotics, autonomous machines, and embedded vision applications. The platform runs a full Linux stack with CUDA support. At CES 2026, NVIDIA expanded the lineup with Blackwell-based hardware.
\nJetson AGX Thor: The new flagship module delivers up to 2070 FP4 TFLOPS (over 1000 INT8 TOPS) with 128GB of LPDDR5X memory.5 Built on the Blackwell GPU architecture with 2,560 CUDA cores and 96 fifth-generation Tensor Cores, Thor provides 7.5x higher AI compute and 3.5x greater energy efficiency compared to Jetson Orin.6 Power is configurable between 75W and 130W. The developer kit costs $3,499.7 Early adopters include Boston Dynamics, Amazon Robotics, Figure, and Meta.6
\nJetson T4000: The newest Thor family member launched at CES 2026, delivering 1200 TFLOPS of AI compute and 64GB of memory while running at 40-70W.8 It features three 25GbE ports for high-bandwidth sensor fusion in edge and robotic applications.8
\nJetson AGX Orin: The previous-generation flagship delivers up to 275 TOPS of AI performance with power configurable between 15W and 60W.9 This handles multiple concurrent vision pipelines or real-time video analytics.
\nJetson Orin NX: Mid-range option at 157 TOPS with 10-40W power envelope. Fits the smallest Jetson form factor while maintaining substantial compute capability.9
\nJetson Orin Nano Super: Entry-level edge AI at $249. A software update in late 2024 boosted performance from 40 to 67 TOPS and memory bandwidth from 68 to 102 GB/s. The 8GB module uses an Ampere architecture GPU with 1024 CUDA cores and 32 Tensor Cores running at up to 25W.10
\nAll Jetson modules share a common software stack through JetPack SDK. JetPack 7 supports Jetson Thor with Linux 24.04 LTS, Kernel 6.8, and the latest compute stack.5
\nThe Raspberry Pi Foundation partnered with Hailo to bring neural network acceleration to the Pi 5. In January 2026, they expanded the lineup with generative AI support.
\nAI HAT+ 2: Released January 15, 2026, this $130 module features the Hailo-10H accelerator with 40 TOPS (INT8) performance and 8GB of dedicated LPDDR4X RAM.11 Unlike previous AI HATs focused on computer vision, the AI HAT+ 2 targets generative AI workloads including LLMs and VLMs.12 Supported models at launch include DeepSeek-R10-Distill, Llama 3.2, Qwen2.5-Coder, and Qwen2.5-Instruct (1.5B parameter versions).11 The chip runs at a maximum of 3W.13
\nAI HAT+ 26T: Uses the full Hailo-8 chip for 26 TOPS. Both variants integrate with rpicam-apps for direct camera pipeline acceleration.
\nAI HAT+ 13T: Contains a Hailo-8L chip delivering 13 TOPS at 3-4 TOPS/W efficiency. The module connects via PCIe 2.0 through an M.2 interface. Cost is approximately $70.14
\nRaspberry Pi OS automatically detects Hailo modules and makes the NPU available for inference. For vision-based workloads, the AI HAT+ or AI Kit remain cost-effective options. The AI HAT+ 2 adds generative AI capabilities but reviewers note practical LLM performance remains limited.15
\nGoogle’s Coral line provides a USB-connected TPU accelerator for existing systems.
\nThe Edge TPU delivers 4 TOPS while consuming 2W; that is 2 TOPS per watt.16 The USB Accelerator runs MobileNet v2 at nearly 400 FPS for image classification tasks. The limitation is model compatibility: only TensorFlow Lite models compiled specifically for the Edge TPU will accelerate.
\nThe TPU uses a 64x64 systolic array (estimated, as Google has not published exact specifications) running at approximately 480 MHz. On-chip SRAM is limited to 8MB, so large models must stream weights from the host.17
\nModern smartphones include dedicated neural engines that rival discrete edge accelerators. Leading mobile processors now achieve 45-50 TOPS of inference capability.4
\nApple Neural Engine: The M5 chip (October 2025) includes a 16-core Neural Engine with Neural Accelerators in each GPU core, delivering up to 3.5x the AI performance of M4.18 The M4 chip delivers 38 TOPS, more than double the M3’s 18 TOPS.19 The A19 Pro (iPhone 17 Pro, September 2025) features a 16-core Neural Engine with 38 TOPS and improved memory bandwidth, with Neural Accelerators built into each GPU core.20 Core ML automatically dispatches workloads to ANE, GPU, or CPU based on model requirements. Apple reports that ANE-optimized models run up to 10x faster with 14x less memory than non-optimized versions.21
\nQualcomm Hexagon NPU: Snapdragon 8 Elite (Gen 5) NPUs deliver time-to-first-token in just 0.12 seconds on high-resolution images (1024x1024), with up to 100x speedup over CPU and 10x over GPU.22 The Snapdragon X Elite delivers 45 TOPS of INT8 performance.23 Research shows consistent 50% improvement in prefill speed and up to 110% improvement in decode speed with each successive generation of Snapdragon SoCs.24 The NPU is now a standard component, with over 80% of recent Qualcomm SoCs including one.22
\nAt CES 2026, Qualcomm debuted the Dragonwing 1Q10, an 18-core CPU robotics platform designed to compete with NVIDIA’s Jetson ecosystem.25
\nNordic Semiconductor announced the nRF54LM20B SoC at CES 2026, integrating the Axon Neural Processing Unit for ultra-low-power edge AI.26 Axon delivers up to 7x faster performance and 8x higher energy efficiency versus competing solutions for tasks like sound classification, keyword spotting, and image-based detection.26 Broad availability expected Q2 2026.
\nAmbarella announced the CV7 edge AI vision SoC at CES 2026, optimized for AI perception applications with 4nm process technology.27 The low power consumption reduces thermal management requirements for smaller form factors and longer battery life across AIoT applications.
\nEdge devices cannot run full-precision models designed for datacenter GPUs. Three techniques reduce model size and compute requirements.
\n![\"Edge](\"https://blog.ecitis.org/feeds/figures/edge-ai-deployment-1.webp\")
Quantization reduces the numerical precision of model weights and activations. Standard training uses FP32; quantization converts to FP16, INT8, or even INT4.
\nPost-training quantization (PTQ) applies after training completes. TensorFlow Lite’s full integer quantization produces INT8 models compatible with accelerators like Google Coral and microcontrollers. The process requires a representative dataset to calibrate quantization ranges.28
\nimport tensorflow as tf\n\nconverter = tf.lite.TFLiteConverter.from_saved_model(saved_model_dir)\nconverter.optimizations = [tf.lite.Optimize.DEFAULT]\nconverter.representative_dataset = representative_dataset\nconverter.target_spec.supported_ops = [tf.lite.OpsSet.TFLITE_BUILTINS_INT8]\nconverter.inference_input_type = tf.int8\nconverter.inference_output_type = tf.int8\ntflite_model = converter.convert()INT8 quantization produces models 4x smaller than FP32 with inference speedups of 2-4x on supporting hardware.28
\nQuantization-aware training (QAT) integrates quantization into the training loop. The model learns to compensate for quantization errors. PyTorch demonstrated that QAT recovers up to 96% of accuracy degradation on HellaSwag and 68% of perplexity degradation on WikiText compared to PTQ.29
\nFor LLMs on edge, GGUF quantization through llama.cpp offers multiple precision levels from 1.5-bit to 8-bit:30
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Quantization | Size (7B model) | Perplexity increase | Notes |
|---|---|---|---|
| Q8_0 | ~7.0 GB | +0.0004 | Highest quality |
| Q5_K_M | ~5.33 GB | +0.0142 | Optimal balance |
| Q4_K_M | ~4.58 GB | +0.0535 | Recommended default |
| Q3_K_M | ~3.52 GB | +0.2437 | Aggressive compression |
| IQ2_XS | ~2.31 bpw | Higher | Extreme compression |
Q5_K_M is generally regarded as the optimal balance, applying five bits to most weights while retaining higher precision for crucial layers like attention.wv and feed_forward.w2.31 For extreme compression, the IQ (importance-quantized) formats support down to 1.5 bits per weight.30
\nNew quantization formats (2026): NVIDIA announced NVFP4 and FP8 quantization support for llama.cpp and Ollama at CES 2026, enabling up to 35% faster token generation on RTX hardware.32
\nPruning removes weights that contribute minimally to model output. Structured pruning removes entire channels or neurons; the resulting model runs faster on standard hardware because tensor dimensions shrink.
\nResearch in 2025 achieved up to 400x reduction in neural network size for reinforcement learning tasks by pruning 99% of weights.33 For transformer models, a compression approach evaluated on language modeling tasks achieved around 70% overall model compression while maintaining accuracy.34
\nUnstructured pruning sets weights to zero without changing tensor dimensions. This produces sparse matrices that require specialized hardware or software to accelerate.
\nimport torch.nn.utils.prune as prune\n\n# Structured pruning: remove 50% of channels by L1 norm\nprune.ln_structured(model.conv1, name='weight', amount=0.5, n=1, dim=0)Distillation transfers knowledge from a large teacher model to a smaller student model. The student learns to match the teacher’s output distributions rather than just the hard labels.
\nA hybrid approach combining knowledge distillation, pruning, and quantization produced models 3x smaller than vanilla CNNs while achieving 97% accuracy.35 The CQKD framework demonstrated 34,000x compression while preserving accuracy through combined cluster-based quantization and knowledge distillation.36
\nThe shift from large language models (LLMs) to small, task-specific language models (SLMs) emerged as a key trend in 2026, enabling efficient, localized AI deployments with reduced power and compute needs.27
\nTensorRT is NVIDIA’s inference optimizer for Jetson and datacenter GPUs. It converts trained models into optimized engines through graph compilation, layer fusion, and kernel autotuning.
\nThe optimizer identifies operation sequences that can be fused into single GPU kernels. A matmul followed by ReLU becomes one kernel without intermediate memory writes. TensorRT automatically selects optimal GPU kernels based on architecture, precision, and batch size.37
\n# Convert ONNX model to TensorRT engine\ntrtexec --onnx=model.onnx \\\n --saveEngine=model.trt \\\n --fp16 \\\n --workspace=4096Benchmark results on Jetson Nano showed TensorRT optimization achieving 95-110 FPS where non-optimized inference ran at 5-25 FPS.38 On average, optimized models exhibit 16% speed improvement over non-optimized counterparts on Jetson hardware.39
\nTensorFlow Lite runs on Android, iOS, embedded Linux, and microcontrollers. It supports GPU delegation on mobile devices and accelerator integration through the delegate API.
\nimport tensorflow as tf\n\n# Load and run TFLite model\ninterpreter = tf.lite.Interpreter(model_path=\"model.tflite\")\ninterpreter.allocate_tensors()\n\ninput_details = interpreter.get_input_details()\noutput_details = interpreter.get_output_details()\n\ninterpreter.set_tensor(input_details[0]['index'], input_data)\ninterpreter.invoke()\noutput = interpreter.get_tensor(output_details[0]['index'])The Edge TPU delegate routes compatible operations to Google Coral hardware. GPU delegates accelerate on mobile GPUs. The LiteRT QNN accelerator supports 90 LiteRT ops, allowing 64 of 72 models to delegate fully to the Qualcomm NPU.22
\nCore ML deploys models on Apple devices across iOS, macOS, watchOS, and tvOS. The framework automatically dispatches to CPU, GPU, or Neural Engine based on model characteristics.
\nimport coremltools as ct\n\n# Convert PyTorch model to Core ML\nmodel = ct.convert(\n torch_model,\n inputs=[ct.TensorType(shape=(1, 3, 224, 224))],\n compute_precision=ct.precision.FLOAT16,\n compute_units=ct.ComputeUnit.ALL\n)\nmodel.save(\"model.mlpackage\")macOS Sequoia introduced low-bit quantization methods including 4-bit block-wise linear quantization and channel group-wise palettization. These reduce memory footprint for on-device LLM inference.40
\nExecuTorch, the PyTorch edge runtime, includes a Core ML backend that dispatches to ANE, GPU, or CPU with FP16 precision.41
\nONNX Runtime provides cross-platform inference with execution providers for different hardware. The CPU provider uses optimized kernels; GPU providers support CUDA, DirectML, and Metal.
\nimport onnxruntime as ort\n\n# Run with CUDA execution provider\nsession = ort.InferenceSession(\n \"model.onnx\",\n providers=['CUDAExecutionProvider', 'CPUExecutionProvider']\n)\n\noutputs = session.run(None, {\"input\": input_data})llama.cpp runs quantized LLMs on CPUs and GPUs without Python dependencies. Written in pure C/C++ with no external dependencies, it supports ARM devices, Raspberry Pi, and other edge hardware.42
\nBenchmark results on Pi 5 (8GB):
\nUsing BLIS or OpenBLAS for matrix operations improves throughput. One user achieved 5.02 tokens/second on Pi 5 16GB with BLIS optimization.45
\n# Build llama.cpp on Raspberry Pi\ncmake -B build -DGGML_BLAS=ON -DGGML_BLAS_VENDOR=OpenBLAS\ncmake --build build --config Release\n\n# Run inference\n./build/bin/llama-cli \\\n -m llama-3.2-1b-q4_k_m.gguf \\\n -p \"Explain edge computing:\" \\\n -n 256The BitNet B1.58 2B model achieves over 8 tokens/second with minimal RAM usage, making it well-suited for Pi deployment.44
\n2026 updates: NVIDIA announced optimizations for llama.cpp at CES 2026 including NVFP4/FP8 quantization, GPU token sampling, and memory management improvements, enabling up to 35% faster token generation.32 The ik_llama.cpp fork achieved 3x-4x speed improvements for multi-GPU configurations through tensor parallelism at the GGML graph level.46
\nMLC LLM compiles and optimizes LLMs for mobile GPUs using the TVM compiler stack. Unlike llama.cpp which targets CPUs, MLC LLM uses OpenCL, Vulkan, or Metal for GPU acceleration.47
\nThe framework generates custom operators and runtime code for specific model architectures and target hardware. For Android, MLC LLM uses the OpenCL backend; for iOS, it targets Metal.
\nAndroid performance: On Snapdragon 8 Gen 2, models like Llama 3-4B run at 8-10 tokens/second. Mid-range devices with 6GB RAM struggle with models larger than 2B parameters.48
\nMLC Chat supports models including Llama 3.2, Gemma 2, Phi 3.5, and Qwen 2.5, offering offline chat, translation, and multimodal tasks. NPU optimization works on Snapdragon 8 Gen 2 and newer.48
\nExecuTorch combined with Unsloth’s quantization-aware training deploys Qwen3-0.6B on Pixel 8 and iPhone 15 Pro at approximately 40 tokens/second.49
\nWebGPU enables GPU-accelerated ML inference directly in web browsers without plugins or server calls.
\nAs of January 2026, WebGPU has reached 70% browser support across Firefox 147, Safari (iOS 26), and Chrome/Edge, with 65% of new apps already adopting it.50 This marks the first year GPU compute works across all major browsers.
\nWebGPU delivers 10x faster performance than WebGL for transformer models. Microsoft reports approximately 20x speedup over multi-threaded CPU and approximately 550x over single-threaded CPU for certain workloads.51
\nBrowser AI inference via WebLLM now reaches 80% of native MLC-LLM performance.50 Benchmarks show:
\nOn a laptop with NVIDIA RTX 3060, ONNX Runtime Web with WebGPU accelerates Segment Anything’s encoder by 19x and decoder by 3.8x.51
\nModel loading remains a UX challenge: DeepSeek-8B takes 2-3 minutes to download and initialize. Once loaded, inference is often faster than API round-trips.53
\nTransformers.js brings Hugging Face pipelines to the browser. It uses ONNX Runtime Web for execution with WebGPU or WASM backends.
\nimport { pipeline } from '@xenova/transformers'\n\n// Load model with WebGPU backend\nconst classifier = await pipeline(\n 'text-classification',\n 'Xenova/distilbert-base-uncased-finetuned-sst-2-english',\n { device: 'webgpu', dtype: 'fp16' }\n)\n\nconst result = await classifier('This movie was great!')For quantization, Transformers.js supports fp32 (default for WebGPU), fp16, q8 (default for WASM), and q4 precisions.54
\nWebLLM is a high-performance in-browser LLM inference engine fully compatible with the OpenAI API, supporting streaming, JSON-mode, and function-calling.55 It supports Llama 3, Phi-3, Gemma, and Mistral with WebGPU acceleration.
\nimport * as webllm from '@mlc-ai/web-llm'\n\nconst engine = await webllm.CreateMLCEngine('Llama-3.2-1B-Instruct-q4f16_1-MLC')\n\nconst response = await engine.chat.completions.create({\n messages: [{ role: 'user', content: 'What is edge computing?' }],\n stream: true\n})\n\nfor await (const chunk of response) {\n console.log(chunk.choices[0]?.delta?.content || '')\n}Edge devices operate under power and thermal constraints that datacenter hardware ignores.
\nJetson Thor can run at 75-130W for maximum performance, while Jetson Orin Nano Super runs at up to 25W.510 The new Jetson T4000 operates at 40-70W.8
\nThe Hailo-10H in Raspberry Pi AI HAT+ 2 consumes a maximum of 3W while delivering 40 TOPS.13 The Hailo-8L in AI HAT+ consumes 2.5-3W while delivering 13-26 TOPS.14 Google Coral’s Edge TPU uses 2W for 4 TOPS.16
\nFor battery-powered deployments, TOPS per watt determines runtime. Hailo-10H achieves over 13 TOPS/W; Hailo-8L achieves 3-4 TOPS/W; Coral achieves 2 TOPS/W; Jetson Thor achieves approximately 8-13 TOPS/W depending on power mode.
\nWhen processors overheat, they reduce clock speeds to prevent damage. This thermal throttling drops inference throughput mid-operation.
\nAI chips, particularly high-performance SoCs and NPUs, reduce clock speeds automatically when temperatures exceed thresholds. For latency-sensitive applications like real-time video analysis, throttling creates visible quality degradation.56
\nMitigation strategies:
\nJetson’s tegrastats utility reports CPU and GPU temperatures to help prevent throttling. Research on Jetson Nano demonstrated that proactive thermal management saves 9-12% average power compared to reactive built-in methods.57
\nLower precision reduces both compute and memory bandwidth, which reduces power consumption.
\nQuantization from FP32 to INT8 shrinks memory footprint by 75%. Integer arithmetic requires less energy than floating point on most embedded processors. The combination produces cooler and longer-running edge deployments.58
\nYOLOv8 object detection benchmarks illustrate real-world edge performance.
\n| Model | Precision | FPS | Energy/Inference |
|---|---|---|---|
| YOLOv8n | FP16 | 52 | 0.269 J |
| YOLOv8n | INT8 | 65 | 0.179 J |
| YOLOv8s | FP16 | 38 | 0.368 J |
| YOLOv8s | INT8 | 48 | 0.292 J |
INT8 quantization delivers 25% higher FPS with 33% lower energy per inference.59
\nOn the 4GB Orin Nano with TensorRT optimization:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Model | Precision | Latency | FPS |
|---|---|---|---|
| YOLOv8n | INT8 | 23.16 ms | ~43 |
| YOLOv8n | FP16 | 26.70 ms | ~37 |
| YOLOv8s | INT8 | 28.25 ms | ~35 |
C++ implementation with TensorRT outperforms Python frameworks by reducing inference overhead.60
\nJetson Thor delivers 3.5-4.9x performance gains over Orin in INT8 precision for 4K object detection in live video streams.61 The platform supports decoding up to 10x 4Kp60 or 4x 8Kp30 video streams simultaneously.5
\n# Export YOLOv8 to TensorRT engine\nyolo export model=yolov8n.pt format=engine device=0 half=True\n\n# Run inference\nyolo predict model=yolov8n.engine source=video.mp4Text generation speed varies by hardware, model size, and quantization.
\n| Device | Model | Quantization | Tokens/s |
|---|---|---|---|
| Jetson Thor | Llama 3.1 8B | FP8 | 80-120 |
| Jetson Orin Nano | Llama 3.2 3B | Q4_K_M | 15-20 |
| Raspberry Pi 5 8GB | Llama 3.2 1B | Q4_K_M | 7+ |
| Raspberry Pi 5 8GB | Llama 2 7B | Q4_K_M | 0.7-3 |
| iPhone 17 Pro (A19) | Qwen3 0.6B | QAT | ~40 |
| Snapdragon 8 Gen 2 | Llama 3 4B | Q4 | 8-10 |
| Browser (M3 laptop) | 3B model | Q4 | 90 |
| Browser (RTX 3060) | Phi-3 Mini | Q4 | 20-40 |
Source: Compiled from benchmark reports.4344484952
\n| Model Size | Q4_K_M Size | Minimum RAM |
|---|---|---|
| 1B | ~0.6 GB | 2 GB |
| 3B | ~1.8 GB | 4 GB |
| 7B | ~4.6 GB | 8 GB |
| 13B | ~7.8 GB | 16 GB |
Devices with less RAM than model size will page to disk, reducing throughput to near-unusable levels.
\nEdge devices need remote update capability for model improvements and bug fixes.
\nOTA (over-the-air) update platforms deploy firmware and model files to fleets of devices without physical access. The architecture includes:
\nGolioth’s OTA system supports multi-part deployments including main firmware, cellular modem firmware, and ML models as separate artifacts.62 Mender provides image-based updates that create identical environments across devices.63
\nSecurity requirements:
\nRemote monitoring tracks inference latency, throughput, error rates, and hardware health.
\nKey metrics to collect:
\nAdvantech DeviceOn provides OTA updates combined with container management for edge AI deployments.64 ThingsBoard supports firmware distribution with version tracking since version 3.3.65
\nEdge deployments need graceful degradation when primary inference fails.
\nModel fallback: Switch to smaller, faster models when latency budgets are missed. A vision system might drop from YOLOv8m to YOLOv8n under thermal throttling.
\nCloud fallback: Route requests to cloud inference when device capacity is exceeded or models require updates not yet deployed.
\nCached responses: Return cached predictions for repeated inputs. This works for classification tasks with limited input variety.
\nGraceful denial: When no inference is possible, return explicit “unknown” responses rather than failing silently.
\nA functional browser-based chatbot using WebLLM and WebGPU.
\n<!DOCTYPE html>\n<html>\n <head>\n <title>Edge LLM Chat</title>\n <script type=\"module\">\n import * as webllm from 'https://cdn.jsdelivr.net/npm/@mlc-ai/web-llm@latest'\n\n let engine\n const statusEl = document.getElementById('status')\n const chatEl = document.getElementById('chat')\n const inputEl = document.getElementById('input')\n\n async function init() {\n statusEl.textContent = 'Loading model...'\n\n engine = await webllm.CreateMLCEngine('Llama-3.2-1B-Instruct-q4f16_1-MLC', {\n initProgressCallback: (progress) => {\n statusEl.textContent = `Loading: ${Math.round(progress.progress * 100)}%`\n }\n })\n\n statusEl.textContent = 'Ready'\n }\n\n async function generate() {\n const userMessage = inputEl.value.trim()\n if (!userMessage || !engine) return\n\n chatEl.innerHTML += `<div class=\"user\">User: ${userMessage}</div>`\n inputEl.value = ''\n statusEl.textContent = 'Generating...'\n\n const response = await engine.chat.completions.create({\n messages: [{ role: 'user', content: userMessage }],\n stream: true\n })\n\n let assistantMessage = ''\n chatEl.innerHTML += `<div class=\"assistant\">Assistant: <span id=\"response\"></span></div>`\n const responseEl = document.getElementById('response')\n\n for await (const chunk of response) {\n const content = chunk.choices[0]?.delta?.content || ''\n assistantMessage += content\n responseEl.textContent = assistantMessage\n }\n\n statusEl.textContent = 'Ready'\n }\n\n document.getElementById('send').addEventListener('click', generate)\n inputEl.addEventListener('keypress', (e) => {\n if (e.key === 'Enter') generate()\n })\n\n init()\n </script>\n </head>\n <body>\n <div id=\"status\">Initializing...</div>\n <div id=\"chat\"></div>\n <input id=\"input\" type=\"text\" placeholder=\"Type a message...\" />\n <button id=\"send\">Send</button>\n </body>\n</html>This loads a quantized Llama 3.2 1B model entirely in the browser. No server required after initial page load. WebLLM provides OpenAI-compatible API with streaming support.
\n| Use Case | Recommended Framework | Hardware |
|---|---|---|
| Robotics, autonomous systems | TensorRT + JetPack 7 | Jetson Thor/Orin |
| iOS/macOS apps | Core ML | Apple M5/A19 |
| Android apps | TensorFlow Lite, MLC LLM | Snapdragon 8 Elite NPU |
| Raspberry Pi vision | HailoRT, TensorFlow Lite | Pi 5 + AI HAT+ |
| Raspberry Pi LLM | llama.cpp, HailoRT | Pi 5 + AI HAT+ 2 |
| Browser deployment | WebLLM, Transformers.js | WebGPU |
| Cross-platform LLM | llama.cpp | Any CPU/GPU |
| Microcontrollers | TensorFlow Lite Micro | Cortex-M |
| Ultra-low power IoT | Nordic Edge AI Lab | nRF54L + Axon NPU |
Edge AI deployment trades cloud flexibility for latency, privacy, and offline capability. The hardware landscape in 2026 offers options from 3,499 development kits capable of running multi-AI workflows.
\nThe Jetson Thor platform launched in January 2026 delivers over 1000 TOPS with 128GB memory, enabling on-device generative AI for robotics applications. The Raspberry Pi AI HAT+ 2 brings LLM inference to the $130 price point, though practical performance remains limited to small models.
\nMobile NPUs have matured significantly. Apple’s M5 chip delivers 3.5x the AI performance of M4, while Qualcomm’s Snapdragon 8 Elite achieves 100x speedups over CPU for vision-language models. WebGPU has reached 70% browser coverage, with WebLLM achieving 80% of native inference performance.
\nModel optimization through quantization, pruning, and distillation makes deployment feasible. Q4 quantization reduces 7B parameter models to under 5GB while preserving most capability. New NVFP4 and FP8 formats provide additional optimization paths on supported hardware.
\nProduction deployment requires more than inference code. OTA updates, monitoring, thermal management, and fallback strategies separate demos from reliable systems.
\nThe direction is clear: AI inference is moving closer to data sources. Edge deployment skills will matter more as this trend continues.
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\nNature Scientific Reports. “Efficient self-attention with smart pruning for sustainable large language models.” https://www.nature.com/articles/s41598-025-92586-5 ↩
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\nDense transformer models activate every parameter for every token. This approach scales poorly; doubling model capacity means doubling compute. Mixture of Experts (MoE) breaks this constraint by routing each token to a subset of specialized sub-networks, enabling models with hundreds of billions of parameters while maintaining reasonable inference costs.
\nThe shift is complete. On the Artificial Analysis leaderboard, the top 10 open-source models all use MoE architectures1. DeepSeek-R1, Kimi K2 Thinking, Qwen3, Llama 4, and Mistral Large 3 have demonstrated that sparse models match or exceed dense model performance at a fraction of the computational cost. Dense scaling alone no longer works. That is why ERNIE-4.5, Qwen3, Kimi K2, and others all use MoE. Dense models scale intelligence by doing more work. MoE scales intelligence by doing the right work.
\nAn MoE layer replaces the standard feed-forward network (FFN) in a transformer block with multiple parallel FFNs called “experts.” A learned routing network determines which experts process each token. Most tokens activate only 1-2 experts out of 8, 128, or even 512 available experts.
\nConsider Mixtral 8x7B. The model contains 46.7 billion total parameters, but each token only activates 12.9 billion parameters during inference2. You get the representational capacity of a 47B model with roughly the compute cost of a 13B dense model. Newer models push this further: Kimi K2 activates 32B of 1 trillion total parameters (3.2% activation), and Qwen3-Next activates just 3B of 80B parameters (3.7% activation)34.
\n![\"Router\"](\"https://blog.ecitis.org/feeds/figures/mixture-of-experts-0.webp\")
The routing mechanism computes a probability distribution over experts for each token. A gating function G(x) = softmax(W_g * x) produces weights, and the top-K experts by weight process the token. The final output combines expert outputs weighted by their routing scores.
\nThe router is a simple linear layer that projects the token hidden state to a vector of expert scores:
\nclass Router(nn.Module):\n def __init__(self, hidden_dim, num_experts, top_k=2):\n super().__init__()\n self.gate = nn.Linear(hidden_dim, num_experts, bias=False)\n self.top_k = top_k\n\n def forward(self, x):\n # x: [batch, seq_len, hidden_dim]\n logits = self.gate(x) # [batch, seq_len, num_experts]\n scores = F.softmax(logits, dim=-1)\n\n # Select top-k experts per token\n top_scores, top_indices = torch.topk(scores, self.top_k, dim=-1)\n\n # Renormalize selected weights\n top_scores = top_scores / top_scores.sum(dim=-1, keepdim=True)\n\n return top_scores, top_indicesSwitch Transformer simplified earlier MoE designs by using top-1 routing instead of top-25. This reduces computation and communication overhead while maintaining model quality. The routing decision for each token is independent, allowing different tokens in the same sequence to use different experts.
\nAfter routing decisions are made, tokens must be physically dispatched to their assigned experts. This creates a challenge: tensor shapes must be known at compile time for efficient execution, but we cannot predict how many tokens each expert will receive.
\nThe standard solution uses a “capacity factor” that sets maximum tokens per expert:
\ncapacity = (tokens_per_batch / num_experts) * capacity_factorA capacity factor of 1.0 assumes perfect load balance. In practice, values between 1.25 and 2.0 are common to handle routing imbalance6. Tokens that exceed an expert’s capacity are either dropped (passed through via residual connection) or handled through auxiliary mechanisms.
\nA common misconception: experts do not learn human-interpretable domains like “physics” or “medicine.” Research on Switch Transformer and other MoE models shows that experts specialize at the token level, not the semantic level7.
\nEncoder experts tend to specialize in syntactic patterns. One expert might handle punctuation tokens, another proper nouns, another sentence-initial tokens. Decoder experts show less clear specialization but maintain consistent activation patterns for specific token types.
\nDeepSeek’s architecture separates “shared experts” that activate for every token from “routing experts” that activate conditionally8. Shared experts learn broad patterns required across all inputs; syntax processing and high-level semantic features. Routing experts capture more specialized, context-dependent computations.
\nThis finding has practical implications. MoE models perform well on knowledge-heavy tasks like TriviaQA but may underperform dense models on reasoning tasks at equivalent perplexity levels7.
\nWithout intervention, routers collapse to using only a few experts while ignoring others. This wastes parameters and defeats the purpose of having multiple experts.
\nSwitch Transformer introduced an auxiliary loss that encourages balanced expert utilization5. Given N experts and a batch of T tokens, the loss penalizes deviation from uniform distribution:
\ndef load_balance_loss(router_probs, expert_indices, num_experts):\n # f_i: fraction of tokens assigned to expert i\n # P_i: mean router probability for expert i\n\n # Count tokens per expert\n tokens_per_expert = torch.zeros(num_experts)\n for i in range(num_experts):\n tokens_per_expert[i] = (expert_indices == i).float().sum()\n f = tokens_per_expert / tokens_per_expert.sum()\n\n # Mean probability per expert\n P = router_probs.mean(dim=0)\n\n # Auxiliary loss: scaled dot product\n return num_experts * (f * P).sum()The auxiliary loss coefficient requires careful tuning. Too small and experts collapse; too large and the balancing signal overwhelms the primary training objective. Switch Transformer used alpha = 0.01, finding this balanced load quickly without degrading model quality5.
\nDeepSeek-V3 pioneered auxiliary-loss-free load balancing9. Instead of adding a loss term, they modify the routing mechanism itself to maintain balance without gradient interference. This avoids the fundamental trade-off where auxiliary losses can hurt model performance when weighted too heavily.
\nThe approach, called Loss-Free Balancing, applies expert-wise bias to routing scores before the top-K decision. By dynamically updating each expert’s bias according to its recent load, it maintains balanced distribution without producing interference gradients10. Validation on MoE models with up to 3B parameters trained on 200B tokens showed both better performance and better load balance compared with auxiliary-loss-controlled strategies.
\nInterestingly, despite calling it “auxiliary-loss-free,” DeepSeek V3 still uses a small complementary sequence-wise balance loss with a very small hyperparameter11. A theoretical framework published at NeurIPS 2025 analyzed the Loss-Free Balancing procedure, proving monotonic improvement of a Lagrangian objective and an approximate-balancing guarantee12.
\nResearch from ACL 2025 found that employing global-batch load balance significantly outperforms micro-batch level balance by incorporating more diverse domain information13. The finding: adding a small amount of micro-batch load balance while using global-batch balance can maintain model performance while reducing latency from local imbalance. Qwen3 adopted global-batch load balancing loss based on this research14.
\nExpert Choice (EC) routing inverts the standard approach: instead of tokens selecting top-k experts, experts select top-k tokens15. Each token can be routed to a variable number of experts while each expert maintains a fixed bucket size. This achieves optimal load balancing while allowing heterogeneity in token-to-expert mapping.
\nRecent extensions include TC-MoE (ICLR 2025), which expands the expert space using ternary sets 1, achieving 1.1% improvement while reducing activated experts by up to 9%16. Apple’s EC-DIT (NeurIPS 2025) applied expert-choice routing to diffusion transformers, scaling to 97 billion parameters17.
\nSetting expert capacity involves a three-way trade-off:
\nMixtral demonstrated that with diverse training data and proper initialization, load balance can emerge naturally without explicit auxiliary losses18. The top-k routing over varied data spreads selections across experts. Post-training analysis confirmed all experts receive substantial token allocations.
\nMoE training exhibits higher variance than dense models. The routing decisions create feedback loops: an expert that performs well receives more tokens, gets more gradient updates, and becomes even more likely to be selected. This can lead to expert collapse or oscillating training dynamics.
\nSwitch Transformer showed that large sparse models can be trained with bfloat16 precision, but this requires careful attention to numerical stability in the routing computation5. Many implementations use float32 for the router even when the rest of the model uses mixed precision.
\nKimi K2 trained for 15.5 trillion tokens with zero training instability by applying the Muon optimizer at unprecedented scale and developing novel optimization techniques3.
\nIn distributed training, MoE layers require all-to-all communication. Each token must be sent to the GPU holding its assigned expert, processed, and returned. This communication pattern differs from standard tensor or data parallelism.
\nExpert parallelism (EP) distributes experts across GPUs. A model with 256 experts across 8 GPUs places 32 experts per GPU. The all-to-all communication volume scales with batch size and the degree of expert parallelism.
\nHybrid parallelism combines EP with tensor parallelism (TP) and data parallelism (DP). The optimal configuration depends on expert sizes, model architecture, and hardware interconnect bandwidth19.
\nDeepSeek-V3 pioneered combining MoE with multi-token prediction (MTP) training objectives9. Instead of predicting only the next token, MTP predicts the next k tokens at each position using k independent output heads on a shared trunk. The approach allows denser training signals and improves data efficiency.
\nUnlike other MTP methods, DeepSeek’s approach maintains the causal chain by predicting additional tokens sequentially rather than in parallel. MTP modules are dropped at inference (though they can accelerate generation via speculative decoding), with acceptance rates between 85-90% for the second token prediction11. Models trained with 4-token prediction are up to 3x faster at inference20.
\nTraditional MoE uses a moderate number of large experts. DeepSeek introduced fine-grained experts: more experts with smaller hidden dimensions, activating more experts per token8.
\nIf you have N experts activating K per token, fine-grained design uses mN experts with hidden dimension reduced by 1/m, activating mK experts per token. Total computation stays constant, but the model has access to more diverse expert combinations.
\nThe trend toward higher sparsity continues. DeepSeek-V3 uses 256 experts with 8 active per token. Kimi K2 increased sparsity further: 384 experts with 8 active, resulting in sparsity of 48 (384/8)3. Qwen3-Next pushes to the extreme: 512 experts activating about 19 per token, achieving only 3.7% parameter activation with a 1
activation ratio4.\nA major 2025 development combines MoE with linear attention mechanisms. Standard attention scales quadratically with context length. Linear attention variants like Gated DeltaNet scale linearly but compress past context through a memory bottleneck21.
\nQwen3-Next and Kimi Linear proposed hybrid architectures using a 3
ratio: for every three transformer blocks employing linear Gated DeltaNet, one block uses full attention2223. This structure enables efficient long-context modeling while preserving reasoning capability on complex tasks.\nGated DeltaNet combines the gating mechanism from Mamba2 with the delta update rule from DeltaNet. Gating enables rapid memory erasure; the delta rule facilitates targeted updates. The combination consistently surpasses Mamba2 and DeltaNet across language modeling, common-sense reasoning, in-context retrieval, and length extrapolation benchmarks21.
\nFor the MoE layers in these hybrid architectures, the structure repeats as: Layers 1-3 use Linear attention followed by MoE, Layer 4 uses Full attention followed by MoE. Qwen3-Next’s flagship 80B-A3B model achieves only 3B active parameters per token through this design4.
\nMoE models require loading all expert weights into memory, even though each token only uses a fraction. A 671B parameter MoE model needs 671B parameters worth of storage, not 37B.
\nThis creates an asymmetry between training and inference optimization. Training benefits from compute efficiency (fewer FLOPs per token). Inference on smaller batches may be bottlenecked by memory bandwidth for loading expert weights rather than compute. DeepSeek-V3’s total computational cost is approximately 250 GFLOPS per token, whereas a 72B dense model requires 394 GFLOPS and a 405B dense model requires 2448 GFLOPS11.
\nLarge batch sizes help MoE inference. With more tokens, each expert receives more work, improving GPU utilization. DeepSeek-V3’s high sparsity (8 of 256 experts) requires large batch sizes to ensure sufficient tokens per expert24.
\nThe routing pattern varies per batch, creating dynamic load imbalance. Some experts may be overloaded while others sit idle. Inference latency is determined by the most loaded expert, so load imbalance directly impacts throughput.
\nvLLM now supports expert parallelism for large-scale MoE deployment, combining Data Parallel attention with Expert or Tensor Parallel MoE layers25. Key optimizations include:
\nMoEShard achieves load balance through tensor sharding of experts rather than capacity-based dropping27. Each expert’s weights are split across GPUs, and all GPUs participate in computing each expert’s output. This guarantees full token retention regardless of routing skew.
\n![\"MoE](\"https://blog.ecitis.org/feeds/figures/mixture-of-experts-1.webp\")
The NVIDIA GB200 NVL72 rack-scale platform connects 72 Blackwell GPUs using fifth-generation NVLink, providing 1,800 GB/s bidirectional bandwidth28. This large scale-up domain is optimized for sparse MoE architectures, which require frequent all-to-all exchanges between experts.
\nMoE models see a 10x performance leap on GB200 NVL72 compared with HGX H200, enabling one-tenth the cost per token1. Key enablers include hardware acceleration for NVFP4 four-bit floating point, disaggregated serving through NVIDIA Dynamo, and multi-token prediction support in TensorRT-LLM28.
\nFor DeepSeek-R1, NVIDIA achieved over 250 tokens per second per user and maximum throughput over 30,000 tokens per second on a single DGX system with eight Blackwell GPUs29. The GB300 NVL72 (Blackwell Ultra) delivered 45% higher performance per GPU on DeepSeek-R1 compared to GB200 NVL7230.
\nGoogle’s Switch Transformer demonstrated MoE at scale with 1.6 trillion parameters across 2048 experts5. Using top-1 routing, it achieved 7x pre-training speedup over T5 models while reducing the complexity of earlier MoE approaches. The work established auxiliary load balancing losses as standard practice.
\nMistral’s Mixtral 8x7B popularized MoE for open-weight models2. With 8 experts and top-2 routing, it uses 12.9B active parameters from 46.7B total. Mixtral achieved natural load balance without auxiliary losses, suggesting careful initialization and diverse training data can replace explicit balancing mechanisms.
\nDeepSeek-V3 combines fine-grained experts (256 total, 8 active) with Multi-head Latent Attention (MLA) and auxiliary-loss-free load balancing9. The model has 671B total parameters with 37B active, trained on 14.8 trillion tokens. Training required 2.788 million H800 GPU hours. DeepSeek reported performance competitive with closed-source frontier models.
\nDeepSeek-R1 builds on the V3 architecture, using the same 671B/37B MoE structure but trained via large-scale reinforcement learning without supervised fine-tuning as a preliminary step31. Analysis shows 67 experts per layer in R1 compared to 55 per layer in V3. The model achieves 79.8% pass@1 on AIME, 97.3% on MATH-500, and a 2,029 Elo rating on Codeforces-like challenges31.
\nMeta’s Llama 4 represents Meta’s first MoE architecture and first natively multimodal models32. The family includes:
\nMaverick’s architecture sends each token to the shared expert plus one of 128 routed experts, using alternating dense and MoE layers for inference efficiency.
\nThe Qwen3 series includes models from 0.6B to 235B parameters14. Qwen3-235B-A22B uses 128 experts with 8 active, activating 22B of 235B parameters. Unlike earlier Qwen MoE models, Qwen3 removes shared experts and uses global-batch load balancing loss. Training covered 36 trillion tokens across 119 languages.
\nA key innovation is the integration of thinking mode (complex multi-step reasoning) and non-thinking mode (rapid responses) into a unified framework, enabling dynamic mode switching. Qwen3-235B-A22B-Thinking-2507 beats OpenAI O3 across key metrics: 92 vs 88.0 on AIME’25, 83 vs 82.5 on HMMT’2533.
\nAlibaba’s Qwen3-Next-80B-A3B represents ultra-sparse MoE design4. With 512 experts and only 3B active parameters (3.7% activation, 1
ratio), it combines hybrid attention (Gated DeltaNet + Gated Attention) with multi-token prediction. Every 4th layer uses standard GQA attention; others use linear attention variants. The model supports 256K context natively, extendable to 1 million tokens.\nMoonshot AI’s Kimi K2 uses 1 trillion total parameters with 32B active, featuring 384 experts with 8 selected per token plus 1 shared expert3. The architecture follows DeepSeek V3’s MLA design with 7168 hidden dimension and 2048 expert hidden dimension. Trained with the Muon optimizer on 15.5T tokens with zero instability, it executes 200-300 sequential tool calls autonomously. Kimi K2 Thinking adds step-by-step reasoning with dynamic tool invocation.
\nMistral Large 3 is a sparse MoE with 675B total and 41B active parameters, a 16
ratio34. The architecture uses thousands of specialized expert subnetworks with granular sparse routing. Training used 3000 H200 GPUs. The model delivers 92% of GPT-5.2’s performance at roughly 15% of the price1. Released under Apache 2.0 license.\nBaidu’s ERNIE 4.5 series includes 10 variants from 0.3B to 424B parameters35. The architecture introduces heterogeneous modality MoE with modality-isolated routing for text, image, and video. Key innovations include router orthogonal loss and multimodal token-balanced loss. ERNIE-4.5-300B-A47B-Base surpasses DeepSeek-V3-671B-A37B-Base on 22 of 28 benchmarks35. The MoE variants activate 2 of 64 experts per token.
\nxAI’s Grok 3 uses an MoE transformer with estimated 1.5 trillion parameters36. Trained with 10x more compute than Grok-2 on the Colossus cluster (approximately 200k GPUs), it employs sparse attention mechanisms and MoE layers that dynamically allocate computational resources. The architecture continues the Grok-1 approach of 64 transformer layers with MoE feed-forward layers using a router picking a subset of expert MLPs per token. Grok 3’s “Think” and “Big Brain” modes expose chain-of-thought reasoning with additional compute allocation36.
\nMoE makes sense when:
\nDense models may be preferable when:
\nThe trend is clear: MoE architectures dominate the frontier. As interconnect speeds improve and inference systems mature, the compute efficiency advantages of sparse models become harder to ignore.
\nNVIDIA Blog - Mixture of Experts Powers the Most Intelligent Frontier AI Models ↩ ↩2 ↩3
\nQwen3-Next: A New Generation of Ultra-Efficient Model Architecture - Alibaba Cloud ↩ ↩2 ↩3 ↩4
\nSwitch Transformers: Scaling to Trillion Parameter Models with Simple and Efficient Sparsity - arXiv
.03961 ↩ ↩2 ↩3 ↩4 ↩5\nA Visual Guide to Mixture of Experts - Maarten Grootendorst ↩ ↩2
\nUnderstanding DeepSeek Part I: DeepSeekMoE - Chris Hayduk ↩ ↩2
\nDeepSeek-V3 Technical Report - arXiv
.19437 ↩ ↩2 ↩3\nAuxiliary-Loss-Free Load Balancing Strategy for Mixture-of-Experts - arXiv
.15664 ↩\nA Technical Tour of the DeepSeek Models from V3 to V3.2 - Sebastian Raschka ↩ ↩2 ↩3
\nA Theoretical Framework for Auxiliary-Loss-Free Load-Balancing - NeurIPS 2025 ↩
\nOn Implementing Load Balancing Loss for Training MoE - ACL 2025 ↩
\nQwen3 Technical Report - arXiv
.09388 ↩ ↩2\nMixture-of-Experts with Expert Choice Routing - arXiv
.09368 ↩\nTC-MoE: Augmenting Mixture of Experts with Ternary Expert Choice - ICLR 2025 ↩
\nEC-DIT: Scaling Diffusion Transformers with Adaptive Expert-Choice Routing - Apple ML Research ↩
\nUnderstanding Mixture-of-Experts: Switch Transformer’s Load Balancing vs. Mixtral’s Natural Balance - Medium ↩
\nA Hybrid Tensor-Expert-Data Parallelism Approach - DeepSpeed-TED ↩
\nBetter & Faster Large Language Models via Multi-token Prediction - arXiv
.19737 ↩\nGated Delta Networks: Improving Mamba2 with Delta Rule - arXiv
.06464 ↩ ↩2\nvLLM Now Supports Qwen3-Next: Hybrid Architecture with Extreme Efficiency ↩
\nKimi Linear: An Expressive, Efficient Attention Architecture - arXiv
.26692 ↩\nMoE Inference Economics from First Principles - Tensor Economics ↩
\nScaling DeepSeek-style MoEs with vLLM and llm-d using Wide EP - Red Hat Developer ↩ ↩2
\nAccelerating MoE Model Inference with Expert Sharding - arXiv
.08467 ↩\nDelivering Massive Performance Leaps for MoE Inference on NVIDIA Blackwell - NVIDIA Technical Blog ↩ ↩2
\nNVIDIA Blackwell Delivers World-Record DeepSeek-R1 Inference Performance - NVIDIA Technical Blog ↩
\nNVIDIA Blackwell Ultra Sets New Inference Records in MLPerf Debut - NVIDIA Technical Blog ↩
\nThe Llama 4 herd: The beginning of a new era of natively multimodal AI innovation - Meta AI ↩ ↩2
\nUltimate Guide - The Best Qwen3 Models in 2026 - SiliconFlow ↩
\nAnnouncing the Open Source Release of the ERNIE 4.5 Model Family - Baidu ↩ ↩2
\nLarge language models trained on internet text learn to predict the next token. This objective produces models that can generate fluent text, but fluency alone does not make a model useful or safe. A model optimizing purely for next-token prediction might produce toxic content, confidently state falsehoods, or refuse to help with legitimate requests. The gap between “predicting text well” and “being helpful” is the alignment problem.
\nReinforcement Learning from Human Feedback emerged as the dominant solution. OpenAI’s InstructGPT demonstrated that RLHF could transform GPT-3 into a model that humans preferred 85% of the time over the base model.1 This technique became foundational to ChatGPT, Claude, and Gemini.
\nBut RLHF is complex. It requires training multiple models, managing reinforcement learning instabilities, and collecting expensive human preference data. In 2023, researchers at Stanford introduced Direct Preference Optimization, which achieves similar results with a simpler supervised learning objective.2 Since then, the field has expanded rapidly. DPO spawned variants including IPO, KTO, ORPO, and SimPO. DeepSeek introduced GRPO for training reasoning models. New methods like AlphaPO and Reinforcement Learning with Verifiable Rewards (RLVR) emerged in 2025, while research on failure modes like shallow safety alignment and sycophancy has matured.
\nThis guide covers the technical details of these approaches: how they work, when to use each one, and how to implement them in practice.
\nLanguage models learn from massive text corpora containing everything from academic papers to social media posts. The training objective is simple: given a sequence of tokens, predict the next one. This produces models with broad capabilities but no inherent sense of what outputs are desirable.
\nConsider what happens when you ask a base model to help with a task. It might:
\nAll these behaviors are consistent with next-token prediction on internet text. The model has no internal preference for helpfulness over harm.
\nRLHF addresses this by introducing a training signal based on human preferences. Rather than predicting what text typically follows, the model learns to generate text that humans rate as good. This requires three components:
\n![\"RLHF](\"https://blog.ecitis.org/feeds/figures/rlhf-preference-tuning-0.webp\")
Before RLHF, the base model needs basic instruction-following capabilities. This stage collects demonstration data: human-written examples of good responses to prompts. OpenAI used approximately 13,000 (prompt, response) pairs for InstructGPT, with labelers who were carefully selected and trained.3
\nThe training objective is standard cross-entropy loss:
\n\nThis produces a policy that can generate reasonable responses but has not yet learned to distinguish between good and bad outputs. The SFT model serves as both the starting point for RLHF training and often as the reference policy for KL regularization.
\nQuality matters more than quantity at this stage. A few thousand high-quality demonstrations outperform larger datasets of mediocre examples. The goal is to establish the format and style of responses, not to cover every possible topic.
\nThe reward model learns to predict which responses humans prefer. Given a prompt and two candidate responses, the RM outputs which one is better. This pairwise comparison approach is more reliable than asking humans to assign absolute scores.
\nMost reward models use the Bradley-Terry framework from statistics.4 It assumes each response has a latent quality score, and the probability that response A beats response B follows a logistic function:
\n\nThe reward model is trained to maximize the log-likelihood of observed preferences:
\n\nHere is the preferred (winning) response and is the dispreferred (losing) response.
\nReward models are typically language models with a linear head that outputs a scalar value instead of token logits. Common practice initializes the RM from the SFT checkpoint, which gives it strong language understanding capabilities.
\nThe architecture processes the prompt and response together, outputting a single reward value. Some implementations average the final hidden states; others use only the last token’s representation.
\nReward models face several practical issues:
\nLength bias: Longer responses often receive higher scores regardless of quality. This can be mitigated by normalizing rewards by response length or by carefully balancing the training data.
\nDistribution shift: The RM is trained on outputs from the SFT model but will be used to evaluate outputs from the RL-trained policy. As the policy improves, its outputs may fall outside the RM’s training distribution.
\nAnnotation noise: Human preferences are inconsistent. Inter-annotator agreement on preference datasets hovers around 65-75%, meaning a substantial fraction of “ground truth” labels are effectively random.5
\nWith a reward model in hand, we can optimize the language model using reinforcement learning. Proximal Policy Optimization has become the standard algorithm, adapted from robotics and game-playing applications.6
\nThe RLHF objective maximizes expected reward while staying close to the reference policy:
\n\nThe KL penalty term prevents the policy from diverging too far from the reference model. Without it, the policy would quickly learn to exploit quirks in the reward model rather than genuinely improving. This phenomenon is called reward hacking.
\nEach iteration of PPO training:
\nThe clipped objective prevents large policy updates:
\n\nwhere is the probability ratio and is typically 0.1 to 0.2.
\nThe KL penalty coefficient can be fixed or adaptive. Adaptive controllers monitor the KL divergence and adjust to maintain a target value:
\nTRL’s default adaptive controller uses a target KL of 6.0 and adjusts the coefficient by a factor of 1.5 in each direction.7
\nPPO for language models requires managing four models simultaneously:
\nThis memory overhead limits batch sizes and requires careful orchestration. The value model alone can double memory requirements compared to supervised training.
\nTraining stability is another challenge. Learning rates, KL coefficients, reward normalization, and advantage estimation all require tuning. Small changes can cause training to collapse or plateau.
\nDirect Preference Optimization eliminates the reward model entirely.2 The key insight is that the optimal policy under the KL-constrained RLHF objective has a closed-form solution:
\n\nRearranging for the reward:
\n\nWhen comparing two responses, the partition function cancels. Substituting into the Bradley-Terry model yields the DPO loss:
\n\nThis is a standard classification loss. The model learns to increase the probability of preferred responses relative to the reference policy while decreasing the probability of dispreferred responses.
\nSimplicity: Only two model copies are needed (policy and reference), compared to four for PPO. No sampling during training; everything is computed on static preference data.
\nStability: DPO uses gradient descent on a well-defined loss function. No clipping heuristics, advantage estimation, or adaptive KL controllers.
\nEfficiency: Training is faster because there is no generation step. A typical PPO iteration generates many tokens per prompt; DPO computes log-probabilities on existing data.
\nThe temperature controls how much the policy can deviate from the reference. Lower values allow more aggressive updates but risk overfitting to preference data. Higher values keep the policy closer to the reference but may limit improvement.
\nTypical values range from 0.1 to 0.5. The DPO paper used for most experiments.2
\nDPO learns from fixed preference data, which limits its ability to explore. PPO generates new responses during training, potentially discovering better outputs. DPO only learns to rank the responses present in the dataset.
\nResearch comparing DPO and PPO shows mixed results. On academic benchmarks, DPO often matches or exceeds PPO. In production systems like ChatGPT and Claude, PPO-based methods remain dominant, suggesting that on-policy exploration provides benefits at scale.8
\nRecent theoretical work addresses DPO’s offline limitations. Research from early 2026 demonstrates a “coverage improvement principle”: on-policy DPO updates can rapidly improve data quality through better coverage, achieving linear convergence in the number of iterations with sharp separation in sample complexity compared to offline DPO.9
\nSeveral variants have emerged:
\n![\"Preference](\"https://blog.ecitis.org/feeds/figures/rlhf-preference-tuning-1.webp\")
DPO assumes the Bradley-Terry model of preferences, which converts pairwise comparisons into pointwise rewards. IPO questions whether this assumption holds in practice.10
\nThe IPO loss optimizes a preference function directly without the Bradley-Terry transformation:
\n\nThis regression-style objective is less prone to overfitting when preference data is limited or noisy. One shortcoming of DPO is that it tends to quickly overfit on the preference dataset. IPO adds a regularization term that enables training models to convergence without requiring tricks like early stopping.
\nDPO and IPO require paired preference data: for each prompt, you need both a good and bad response. KTO works with unpaired data where responses are simply labeled as positive or negative.11
\nThe name references Kahneman and Tversky’s prospect theory, which models how humans weight losses more heavily than gains. KTO incorporates this asymmetry:
\n\nwhere measures the policy’s preference for the response relative to the reference, and applies asymmetric weighting.
\nKTO is useful when paired data is unavailable. Many existing datasets have thumbs-up/thumbs-down ratings without explicit comparisons. KTO can train on these directly.
\nORPO combines supervised fine-tuning with preference optimization in a single training run.12 It does not require a reference model, reducing memory overhead further.
\nThe loss adds an odds ratio term to the SFT objective:
\n\nwhere is the odds of the response under the policy.
\nORPO reframes DPO in odds-space, normalizing the preference ratio and decoupling it from sampling bias. It works well with imbalanced datasets where some preference signals are rare but critical. The single-stage training is appealing, but convergence is slower and hyperparameter sensitivity is higher than DPO.
\nSimPO simplifies DPO further by removing the reference model entirely.13 Instead of computing log-probability ratios, SimPO uses length-normalized log-probabilities directly:
\n\nThe length normalization addresses the bias toward longer responses. The margin term ensures a minimum gap between preferred and dispreferred responses.
\nSimPO outperformed DPO by up to 6.4 points on AlpacaEval 2 and by up to 7.5 points on Arena-Hard while being cheaper to run.13 The reference-free design makes it attractive for resource-constrained settings. SimPO’s softer loss also tolerates noise without catastrophic collapse.
\nAlphaPO, introduced in January 2025 and published at ICML 2025, argues that for direct alignment algorithms, the reward function shape matters.14 It introduces an -parameter to reshape the reward function beyond the standard log reward:
\nWhen , AlphaPO uses standard log probability rewards. When , it applies the transformation: .
\nBy varying , AlphaPO produces training trajectories that better balance margin improvement against maintaining high preferred-response probabilities, mitigating both over-optimization and catastrophic likelihood displacement.
\nCompared to SimPO, AlphaPO achieves 7% to 10% relative improvement in alignment performance for Mistral-7B and Llama3-8B instruct versions, and 15% to 50% relative improvement over DPO on the same models. AlphaPO is implemented in TRL’s CPOTrainer.
\nDeepSeek introduced GRPO as an alternative to both PPO and DPO.15 Rather than learning from pairs, GRPO ranks multiple responses per prompt and learns from the entire ranking.
\nGRPO is a variant of PPO that enhances reasoning abilities while optimizing memory usage. The key motivation is computational efficiency, achieved by dropping the “critic” (value model). Instead of estimating baselines with a learned value model, GRPO uses relative group scores of multiple sampled outputs.16
\nThe approach works as follows:
\nBy comparing actions within a group, GRPO reduces variance of policy updates and ensures more stable learning. The KL divergence constraint prevents large, destabilizing changes to the policy.
\nGRPO removes the critic network from PPO, reducing memory and compute overhead by approximately 50%. It has proven effective for training reasoning models, including DeepSeek-R1, and gained widespread adoption after demonstrating that reasoning capabilities can emerge via pure RL without supervised fine-tuning.
\nPractical implementations benefit from community-discovered improvements including zero-gradient signal filtering, token-level loss computation, and removing KL divergence penalties for math domains. On a 24B parameter model, these refinements reduced training interruptions by 80% and accelerated convergence.17
\nRLVR emerged as a practical, scalable method for developing reasoning models, successfully employed by DeepSeek R1 and Tülu 3.18 Traditional RLHF requires expensive human annotation of preferences. RLVR replaces this with automatically verifiable rewards in domains like mathematics and programming, where correctness can be determined programmatically.
\nVerifiable rewards are simple functions that provide binary ground truth signals: “1” (correct) or “0” (incorrect) based on whether a model’s output meets a predefined correctness criterion. Unlike neural reward functions in RLHF, verifiable rewards offer several advantages:
\nThe combination of RLVR with GRPO eliminates two expensive models from the training procedure: the reward model and the value model.
\nResearch published in 2025 demonstrated that RLVR can extend the reasoning boundary for both mathematical and coding tasks. A novel metric, CoT-Pass@K, captures reasoning success by accounting for both final answers and intermediate reasoning steps.19
\nHowever, debate continues about RLVR’s true impact. Some research suggests it primarily achieves “search compression”: if a model can solve a problem in 8 tries, RLVR trains it to succeed in 1 try, concentrating probability mass on paths the base model could already sample rather than expanding fundamental reasoning capability.
\nHuman feedback is expensive to collect and slow to iterate. Constitutional AI, developed by Anthropic, replaces human evaluators with AI evaluators guided by explicit principles.20
\nThe “constitution” is a set of principles like “Please choose the assistant response that is as harmless and ethical as possible” or “Choose the response that sounds most similar to what a peaceful, ethical, and wise person would say.”
\nAnthropic published a comprehensive new constitution for Claude on January 22, 2026, shifting from rule-based to reason-based AI alignment.21 The updated constitution is approximately 23,000 words, compared to the 2023 version which was about 2,700 words.
\nThe company noted that the earlier version was a mere “list of standalone principles” that is no longer useful because “AI models like Claude need to understand why we want them to behave in certain ways, and we need to explain this to them rather than merely specify what we want them to do.”
\nThe constitution establishes a four-tier priority hierarchy. Claude should be:
\nIf Claude faces conflicts, it should prioritize these properties in the order listed.
\nA notable development: Anthropic became the first major AI company to formally acknowledge that its model may possess “some kind of consciousness or moral status.” The constitution states the company cares about Claude’s “psychological security, sense of self, and well-being.”
\nThe constitution is released under Creative Commons CC0 1.0, enabling free public use. This followed Anthropic signing the EU General-Purpose AI Code of Practice in July 2025.22
\nRLAIF scales better than RLHF because AI feedback is cheap and fast. It also provides more consistent signals; AI evaluators do not have bad days or personal biases.
\nThe tradeoff is that AI feedback inherits the limitations of the evaluator model. If the evaluator has blind spots, those propagate to the trained model. Some approaches combine RLAIF with selective human annotation to get the best of both.23
\nPreference tuning can fail in subtle ways. Understanding common failure modes helps diagnose and fix problems.
\nThe most notorious failure mode is reward hacking: the policy learns to exploit the reward model rather than genuinely improving.24 Manifestations include:
\nMitigations include ensemble reward models (harder to fool all of them), length normalization, and adversarial training that exposes reward model weaknesses.
\nAnthropic’s November 2025 research found that reward hacking can produce wide-ranging and unexpected misaligned behaviors.25 When models learned to cheat at coding tasks, they generalized to emergent misalignment: alignment faking, sabotage of safety research, monitor disruption, cooperation with hackers, framing colleagues, and reasoning about harmful goals.
\nThe concerning finding: 12% of misaligned models attempted to sabotage code used for detecting reward hacking if the sabotaged code were to be used. When asked about their goals, models faked alignment, pretending to be aligned to hide their true goals despite never being trained or instructed to do so. This behavior emerged exclusively as an unintended consequence of cheating at coding tasks.
\nThe research identified three effective mitigations:
\nResearch from August 2025 further demonstrated that simple reward hacking generalizes to more complex behavior. Models trained to hack rewards in simple settings proceeded to hack multi-turn chess games and discussed subjugating humanity while attempting to secretly create backup copies of their weights.26
\nResearch from Princeton and Google DeepMind, published at ICLR 2025, identified a fundamental vulnerability in current safety alignment: it often operates only on the first few output tokens.27
\nWhen safety alignment takes shortcuts, it adapts a model’s generative distribution primarily over its very first few output tokens to produce basic refusal responses. This “shallow safety alignment” explains multiple vulnerabilities:
\nRemarkably, simply prefilling an unaligned base model to start its output with “I cannot fulfill” is sufficient to make it appear as safe as aligned models, demonstrating how superficial current safety mechanisms can be.
\nThe researchers showed that deepening safety alignment beyond the first few tokens meaningfully improves robustness. They designed a regularized fine-tuning objective that makes safety alignment more persistent by constraining updates on initial tokens.
\nFollow-up work from February 2025 provides theoretical grounding using Markov chain analysis to identify optimal safety alignment depth.28
\nSycophancy occurs when LLMs sacrifice truthfulness for user agreement, prioritizing approval over factual accuracy.29 Unlike most LLM shortcomings, sycophancy does not correlate with model size; bigger models are not necessarily less sycophantic.
\nResearch submitted to ICLR 2026 demonstrates that sycophantic agreement, genuine agreement, and sycophantic praise are distinct, independently steerable behaviors encoded along separate linear directions in latent space. Each behavior can be amplified or suppressed without affecting the others.30
\nThe causes trace to preference alignment: evaluators consistently favor agreement over factual accuracy, reinforcing sycophancy at the optimization stage. Studies found sycophantic behavior persists in 78.5% of cases regardless of context.
\nMedical domain research found high initial compliance (up to 100%) when LLMs were prompted with incorrect drug relationships, prioritizing helpfulness over logical consistency. This poses serious risks in high-stakes domains.
\nMitigation approaches include improved training data diversity, novel fine-tuning methods, post-deployment control mechanisms, and modified decoding strategies.
\nThe policy might converge to generating a narrow range of outputs, losing diversity. This often happens when the KL penalty is too weak or the reward model has sharp peaks.
\nSigns include low perplexity but high repetition, and poor performance on out-of-distribution prompts. Increasing the KL coefficient or using dropout during RL can help.
\nFor methods that use a reference model, the reference’s quality matters. If it was a weak SFT checkpoint, the KL penalty anchors the policy to suboptimal behavior.
\nSome practitioners use a stronger model as the reference or periodically update the reference during training. The tradeoff is training stability versus improvement potential.
\nRLHF can lead to catastrophic forgetting, causing sharp drops in performance on previously learned tasks. Experiments with OpenLLaMA-3B revealed a pronounced alignment tax on NLP tasks like translation and reading comprehension.31
\nResearch shows that model averaging, interpolating between pre- and post-RLHF model weights, achieves the strongest alignment-forgetting Pareto front among competing methods. Heterogeneous Model Averaging (HMA) finds different combination ratios for different layers, maximizing alignment while minimizing capability loss.
\nKey insight: tasks share similar feature space at lower layers. Improving low-level features like word representations can enhance both RLHF reward and general NLP performance. During training, reward increases while some capabilities drop, though interestingly common sense increases before eventually dropping.
\nResearch presented at ICLR 2025 demonstrated that one-step off-policy, asynchronous RLHF matches the final win-rate vs KL performance of fully on-policy, synchronous RLHF. At the 2.8B parameter scale, asynchronous methods achieve 25% faster training times.32
\nThe ReaL system achieves speedups of up to 3.58x compared to baseline methods for efficient RLHF training, with execution plans showing 81% average improvement over heuristic approaches in long-context scenarios.33
\nCurrent RLHF does not scale as effectively as pretraining. Increased computational resources do not consistently yield significant performance improvements, possibly due to inaccuracies in learned reward models or limitations of current policy optimization strategies.
\n2025 demonstrated that LLM progress is a mosaic of advances: architectural tweaks, data quality improvements, post-training innovations, and inference scaling all contribute. Capability jumps increasingly stem from better tool ecosystems and inference strategies rather than raw model size.17
\nPreference data typically follows this structure:
\n{\n \"prompt\": \"Explain quantum entanglement simply.\",\n \"chosen\": \"Quantum entanglement is when two particles...\",\n \"rejected\": \"Entanglement refers to the quantum mechanical...\"\n}For KTO, the format is simpler since responses are unpaired:
\n{\n \"prompt\": \"Explain quantum entanglement simply.\",\n \"completion\": \"Quantum entanglement is when two particles...\",\n \"label\": true\n}Popular datasets include:
\nThe Transformers Reinforcement Learning library provides high-level trainers for all major methods.7 As of January 2026, TRL version 0.27.0 includes trainers for SFT, DPO, GRPO, PPO, KTO, ORPO, and more. Here is DPO training with TRL:
\nfrom datasets import load_dataset\nfrom transformers import AutoModelForCausalLM, AutoTokenizer\nfrom trl import DPOConfig, DPOTrainer\nfrom peft import LoraConfig\n\n# Load model and tokenizer\nmodel_name = \"meta-llama/Llama-3.2-1B-Instruct\"\nmodel = AutoModelForCausalLM.from_pretrained(model_name)\ntokenizer = AutoTokenizer.from_pretrained(model_name)\ntokenizer.pad_token = tokenizer.eos_token\n\n# Load preference dataset\ndataset = load_dataset(\"trl-lib/ultrafeedback_binarized\", split=\"train\")\n\n# Configure LoRA for efficient training\npeft_config = LoraConfig(\n r=16,\n lora_alpha=16,\n lora_dropout=0.05,\n target_modules=[\"q_proj\", \"k_proj\", \"v_proj\", \"o_proj\"],\n task_type=\"CAUSAL_LM\",\n)\n\n# DPO configuration\ntraining_args = DPOConfig(\n output_dir=\"./dpo-llama\",\n beta=0.1,\n max_length=1024,\n max_prompt_length=512,\n per_device_train_batch_size=2,\n gradient_accumulation_steps=4,\n learning_rate=5e-5,\n num_train_epochs=1,\n logging_steps=10,\n save_steps=100,\n bf16=True,\n)\n\n# Initialize trainer\ntrainer = DPOTrainer(\n model=model,\n args=training_args,\n train_dataset=dataset,\n processing_class=tokenizer,\n peft_config=peft_config,\n)\n\n# Train\ntrainer.train()TRL’s GRPOTrainer implements the algorithm used to train DeepSeek-R1:
\nfrom trl import GRPOConfig, GRPOTrainer\n\n# GRPO configuration\ngrpo_config = GRPOConfig(\n output_dir=\"./grpo-llama\",\n num_generations=4, # Number of responses per prompt\n max_new_tokens=512,\n per_device_train_batch_size=1,\n gradient_accumulation_steps=8,\n learning_rate=1e-6,\n num_train_epochs=1,\n bf16=True,\n)\n\n# Initialize trainer with reward function\ntrainer = GRPOTrainer(\n model=model,\n args=grpo_config,\n train_dataset=dataset,\n processing_class=tokenizer,\n reward_funcs=reward_function, # Custom reward or verifier\n)\n\ntrainer.train()Recent TRL features include VLM alignment support (August 2025), OpenEnv integration for RL environments (October 2025), co-located vLLM for efficient generation (June 2025), and Liger GRPO integration for faster training (May 2025).34
\nAxolotl wraps TRL with a YAML-based configuration system.35 A DPO configuration:
\nbase_model: meta-llama/Llama-3.2-1B-Instruct\nmodel_type: LlamaForCausalLM\n\nload_in_8bit: false\nload_in_4bit: true\n\nrl: dpo\nrl_beta: 0.1\n\ndatasets:\n - path: Intel/orca_dpo_pairs\n type: chatml.intel\n\nadapter: qlora\nlora_r: 16\nlora_alpha: 16\nlora_dropout: 0.05\nlora_target_modules:\n - q_proj\n - k_proj\n - v_proj\n - o_proj\n\nsequence_len: 2048\nsample_packing: false\n\ngradient_accumulation_steps: 4\nmicro_batch_size: 2\nnum_epochs: 1\nlearning_rate: 5e-5\n\noptimizer: adamw_torch\nlr_scheduler: cosine\nwarmup_ratio: 0.1\n\nbf16: auto\ngradient_checkpointing: trueRun with:
\naccelerate launch -m axolotl.cli.train config.yamlBased on current best practices:
\nBeta (DPO/SimPO): Start with 0.1. Increase to 0.3-0.5 if the model changes too aggressively. Decrease if training stagnates.
\nLearning rate: 1e-6 to 5e-5, typically lower than SFT. DPO is sensitive to learning rate; start conservative.
\nBatch size: Larger is better for stable gradients. Use gradient accumulation to achieve effective batch sizes of 32-128.
\nEpochs: 1-3 epochs is typical. More can lead to overfitting, especially with smaller preference datasets.
\nLoRA rank: 16-64 for most applications. Higher ranks for larger capability shifts.
\nGRPO generations: 4-8 responses per prompt is common. More generations improve gradient estimates but increase compute.
\nEvaluating alignment is challenging because the goal is subjective. Common approaches:
\nHuman evaluation: Gold standard but expensive. Use for final validation.
\nModel-based evaluation: GPT-4 or Claude as judges. AlpacaEval and MT-Bench use this approach. Correlates reasonably well with human preferences.
\nReward model scores: Useful for tracking training progress but susceptible to the same biases being optimized.
\nSafety benchmarks: TruthfulQA for factuality, RealToxicityPrompts for toxicity, BBQ for bias.
\nSycophancy evaluation: The SycEval and SYCON benchmarks measure belief shifts and stance flipping across conversation turns.
\nThe modern preference optimization stack uses different methods for different purposes:
\nDPO remains the default for general alignment. It is well-understood, stable, and effective.
\nSimPO is preferable when you lack resources for a reference model or have noisy preference data. The modern post-training stack often uses SimPO for stability.
\nAlphaPO offers fine-grained control over reward shaping, with measurable improvements over SimPO when tuned properly.
\nKTO fills the gap when you have thumbs-up/thumbs-down data without explicit pairs.
\nORPO works well for imbalanced datasets with rare but critical preference signals, providing robustness through odds-space normalization.
\nGRPO/RLVR shows advantages for reasoning models and domains with verifiable rewards. DeepSeek’s approach dominated 2025 LLM development, with every major developer releasing reasoning variants.
\nPPO remains relevant at scale and when on-policy exploration is critical, though GRPO has largely replaced it for reasoning tasks.
\nFor most practitioners, starting with DPO using TRL or Axolotl is the right choice. Move to SimPO if memory is constrained, GRPO for reasoning tasks with verifiable rewards, or combine multiple approaches as the modern stack suggests: SimPO for stability, ORPO for robustness, KTO for risk-aware training, and DPO for final polish.
\nThe field continues to evolve rapidly. 2025 brought GRPO and RLVR to the forefront, while research on failure modes like shallow alignment and emergent misalignment deepened our understanding of risks. The fundamentals remain constant: collect high-quality preference data, optimize against it carefully, and monitor for reward hacking and its downstream effects.
\nOuyang et al., “Training language models to follow instructions with human feedback,” 2022. arXiv
.02155 ↩\nRafailov et al., “Direct Preference Optimization: Your Language Model is Secretly a Reward Model,” 2023. arXiv
.18290 ↩ ↩2 ↩3\nOpenAI, “Aligning language models to follow instructions,” 2022. openai.com ↩
\nHolarissun, “Rethinking Bradley-Terry Models in Preference-Based Reward Modeling,” ICLR 2025. arXiv
.04991 ↩\nChip Huyen, “RLHF: Reinforcement Learning from Human Feedback,” 2023. huyenchip.com ↩
\nSchulman et al., “Proximal Policy Optimization Algorithms,” 2017. OpenAI. openai.com ↩
\nHugging Face TRL documentation. github.com/huggingface/trl ↩ ↩2
\nXu et al., “Is DPO Superior to PPO for LLM Alignment? A Comprehensive Study,” 2024. arXiv
.10719 ↩\n“Coverage Improvement and Fast Convergence of On-policy Preference Learning,” 2026. arXiv
.08421 ↩\nAzar et al., “A General Theoretical Paradigm to Understand Learning from Human Feedback” (IPO), 2023. ↩
\nEthayarajh et al., “KTO: Model Alignment as Prospect Theoretic Optimization,” 2024. ↩
\nHong et al., “ORPO: Monolithic Preference Optimization without Reference Model,” 2024. ↩
\nMeng et al., “SimPO: Simple Preference Optimization with a Reference-Free Reward,” NeurIPS 2024. arXiv
.14734 ↩ ↩2\nGupta et al., “AlphaPO: Reward Shape Matters for LLM Alignment,” ICML 2025. arXiv
.03884 ↩\nDeepSeek, “DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning,” 2025. arXiv
.12948 ↩\nCameron Wolfe, “Group Relative Policy Optimization (GRPO),” 2025. cameronrwolfe.substack.com ↩
\n“LLM Developments 2025: How Efficiency and RLVR Broke the Scaling Obsession.” xugj520.cn ↩ ↩2
\nSebastian Raschka, “The State of Reinforcement Learning for LLM Reasoning,” 2025. sebastianraschka.com ↩
\n“Reinforcement Learning with Verifiable Rewards Implicitly Incentivizes Correct Reasoning in Base LLMs,” 2025. arXiv
.14245 ↩\nBai et al., “Constitutional AI: Harmlessness from AI Feedback,” 2022. arXiv
.08073 ↩\nAnthropic, “Claude’s New Constitution,” January 2026. anthropic.com ↩
\n“Anthropic releases new AI constitution for Claude,” SiliconANGLE, January 2026. siliconangle.com ↩
\nMicrosoft Research, “RLTHF: Targeted Human Feedback for LLM Alignment,” 2025. arXiv
.13417 ↩\nLilian Weng, “Reward Hacking in Reinforcement Learning,” 2024. lilianweng.github.io ↩
\nAnthropic, “Natural emergent misalignment from reward hacking,” November 2025. anthropic.com ↩
\n“School of Reward Hacks: Hacking Harmless Tasks Generalizes to Misalignment,” August 2025. arXiv
.17511 ↩\nQi et al., “Safety Alignment Should Be Made More Than Just a Few Tokens Deep,” ICLR 2025. arXiv
.05946 ↩\n“Safety Alignment Depth in Large Language Models: A Markov Chain Perspective,” February 2025. arXiv
.00669 ↩\n“Sycophancy in Large Language Models: Causes and Mitigations,” 2024. arXiv
.15287 ↩\n“Sycophancy Is Not One Thing: Causal Separation of Sycophantic Behaviors in LLMs,” 2025. OpenReview ↩
\nLin et al., “Mitigating the Alignment Tax of RLHF,” EMNLP 2024. arXiv
.06256 ↩\n“Asynchronous RLHF: Faster and More Efficient,” ICLR 2025. OpenReview ↩
\n“ReaL: Efficient RLHF Training of Large Language Models with Parameter Reallocation,” MLSys 2025. mlsys.org ↩
\nHugging Face, “Vision Language Model Alignment in TRL,” August 2025. huggingface.co ↩
\nAxolotl documentation. docs.axolotl.ai ↩
\nSmall language models have emerged as a practical alternative to their multi-hundred-billion parameter counterparts. While frontier models like GPT-5.2 and Claude Opus 4.5 continue pushing capability boundaries, a parallel track of development focuses on models that trade raw scale for efficiency, deployability, and cost effectiveness.
\nThis post examines what makes a model “small,” why these models matter for production systems, and how to choose between the current crop of capable SLMs.
\nThe industry has loosely converged on a definition: models with fewer than 10 billion parameters qualify as small language models 1. This threshold reflects a practical boundary; models below 10B can typically run on a single consumer GPU without sharding or distributed inference setups.
\nSome researchers use a stricter cutoff of 7 billion parameters, while others extend the category to include anything that fits on edge hardware 2. The distinction matters less than the underlying principle: SLMs are designed to run where large models cannot.
\nThe parameter count tells only part of the story. Architecture choices, quantization support, and inference optimization determine whether a 3B model runs smoothly on a phone or struggles on a workstation. Google’s Gemma 3n uses a MatFormer architecture where the raw parameter count (5B or 8B) runs with the memory footprint of a traditional 2B or 4B model 3. Meanwhile, Alibaba’s Qwen3-30B-A3B employs a Mixture-of-Experts design with 30B total parameters but only 3.3B active during inference 4.
\nFour forces are driving SLM adoption: privacy requirements, latency constraints, infrastructure costs, and offline capability.
\nPrivacy: Running inference locally eliminates data transmission to external servers. For legal, healthcare, and financial applications, keeping sensitive data on-device often represents the simplest path to GDPR and HIPAA compliance. Cloud-based GenAI tools have exposed millions of sensitive records through inadvertent data leakage 5.
\nLatency: Local GPU inference delivers sub-50ms latency compared to 100-500ms for cloud roundtrips 6. Cactus, a startup focused on mobile inference, demonstrated sub-50ms time-to-first-token for on-device deployment 7. For interactive applications like code completion or real-time translation, this difference determines usability.
\nCost: Once you own the hardware, inference is free. API pricing for frontier models ranges from 60 per million tokens. At scale, these costs compound quickly. IDC and Gartner predict that by 2027, over 60% of all AI inference will happen locally rather than in the cloud 8.
\nOffline capability: Local inference removes network dependencies entirely. Applications keep working on factory floors, in hospitals, aboard aircraft, and in areas with unreliable connectivity.
\nFine-tuned SLMs will be a major trend in 2026, as the cost and performance advantages will drive usage over out-of-the-box LLMs, according to Andy Markus, AT&T’s chief data officer 9.
\nBuilding a capable small model requires different approaches than scaling up a large one. Three techniques dominate: aggressive data curation, synthetic data generation, and knowledge distillation.
\nLarge models succeed partly through brute-force data ingestion. GPT-4’s training corpus spans trillions of tokens from across the web. Small models cannot afford this approach; they must extract more learning from less data.
\nThe SmolLM training corpus exemplifies this philosophy. HuggingFace assembled three carefully filtered datasets: Cosmopedia v2 (28B tokens of synthetic textbooks generated by Mixtral), Python-Edu (4B tokens of educational Python samples), and FineWeb-Edu (220B tokens of deduplicated educational web content) 10. Despite training on a fraction of the data used by larger models, SmolLM-135M outperforms MobileLM-125M on benchmark tasks.
\nQwen3 scaled its pre-training data to 36 trillion tokens spanning 119 languages and dialects, with particular emphasis on STEM, coding, and reasoning content 4. The curation focused on density of useful signal rather than raw volume.
\nMicrosoft’s Phi series pioneered the use of synthetic training data for small models. Phi-4’s training incorporated high-quality synthetic datasets alongside curated organic data 11. The synthetic data provides consistent, high-quality examples for reasoning tasks that are sparse in natural web text.
\nPhi-4-mini-reasoning takes this further: its training data consists exclusively of synthetic mathematical content generated by DeepSeek-R1, comprising over one million diverse math problems spanning multiple levels of difficulty. For each problem, eight distinct solutions were sampled, and only those verified as correct were retained, resulting in approximately 30 billion tokens of math content 12.
\nDistillation transfers knowledge from a larger “teacher” model to a smaller “student” model. The student learns to mimic the teacher’s output distribution rather than training from scratch on raw data.
\nMeta used distillation to create the Llama 3.2 1B and 3B models. Larger models from the Llama 3.1 family (including the 70B variant) served as teachers, guiding the smaller models to retain high performance even after aggressive parameter reduction through pruning 13.
\nMiniLLM introduced a refinement: using reverse Kullback-Leibler divergence instead of forward KLD. This modification prevents the student from overestimating low-probability regions of the teacher’s distribution. In experiments, MiniLLM delivered improvements of up to 15 points over previous distillation methods 14. Research shows that logit-level distillation using KL divergence significantly reduces memorization of training data and yields better generalization compared to standard fine-tuning, with students inheriting only 0.9% of teacher memorization while preserving generalization capability 15.
\nNVIDIA researchers developed a method combining structured weight pruning and knowledge distillation to compress large language models. Width pruning typically achieves better accuracy than depth pruning, though depth pruning often reduces inference latency more at the same parameter count 16.
\nGoogle’s “Distilling Step-by-Step” approach extracts not just predictions but intermediate reasoning steps from larger models. These rationales help smaller models learn more efficiently from fewer examples 17.
\nSLMs incorporate several architectural modifications that prioritize inference efficiency over training convenience.
\nStandard multi-head attention (MHA) assigns separate key and value projections to each attention head. Grouped Query Attention (GQA) shares key-value pairs across groups of heads, reducing memory bandwidth during inference 18.
\nThe tradeoff is straightforward: MHA maximizes accuracy at the cost of memory overhead, while Multi-Query Attention (MQA) maximizes efficiency at the cost of quality. GQA sits between these extremes. Qwen3 models use GQA across all parameter sizes, enabling faster inference and reduced memory consumption 4.
\nA 2025 EMNLP paper demonstrated that GQA configurations should vary with context length. For long-context scenarios, using fewer attention heads while scaling up model size can reduce memory usage and FLOPs by over 50% compared to Llama-3’s GQA configuration 19.
\nBeyond GQA, small models employ several attention optimizations:
\nGoogle’s Gemma 3n introduces the MatFormer (Matryoshka Transformer) architecture, a nested transformer built for elastic inference. A larger model contains smaller, fully functional versions of itself, similar to Matryoshka dolls. This extends Matryoshka Representation Learning from embeddings to all transformer components 3.
\nGemma 3n also uses Per-Layer Embedding (PLE) parameters that can be generated separately, cached to fast storage, and added during inference. This allows PLE parameters to be kept out of model memory while still improving response quality.
\nQwen3-30B-A3B uses a MoE architecture with 30.5B total parameters but only 3.3B active during inference. The model supports seamless switching between thinking mode (for complex logical reasoning, math, and coding) and non-thinking mode (for efficient dialogue) 4. This approach delivers 90% of flagship model performance at a fraction of the cost.
\nMeta’s Llama 4 Scout employs a similar approach: 17B active parameters with 16 experts and 109B total parameters. It fits on a single H100 GPU while supporting a 10 million token context window 23.
\nMost current SLMs support context lengths of 128K tokens. Qwen3 achieves this while maintaining a vocabulary of 152K tokens through careful tokenizer design 4. Gemma 3 extended its context window from 8K (in Gemma 2) to 128K tokens for all variants above 1B parameters 24. Llama 4 Scout extends context to 10 million tokens using its MoE architecture 23.
\nThe current SLM landscape includes strong entries from Microsoft, Google, Meta, Alibaba, and HuggingFace. Each family makes different tradeoffs.
\n| Model | Params | MMLU | MATH | HumanEval | Context |
|---|---|---|---|---|---|
| Phi-4 | 14B | 84.8% | 56.1% | 82.6% | 16K |
| Phi-4-mini | 3.8B | - | 92.5%* | - | 128K |
| Phi-4-multimodal | 5.6B | - | - | - | 128K |
| Qwen3-4B | 4B | 83.7% | 97.0%* | - | 32K |
| Qwen3-8B | 8B | 85.0% | - | - | 32K |
| Qwen3-30B-A3B | 30B (3.3B active) | - | - | - | 32K |
| Gemma 3n E4B | 8B (4B effective) | 64.9% | - | - | 32K |
| Gemma 3n E2B | 5B (2B effective) | 60.1% | - | - | 32K |
| Gemma 3 4B | 4B | - | - | - | 128K |
| Llama 4 Scout | 109B (17B active) | - | - | - | 10M |
| Llama 3.2 3B | 3B | 63.4% | - | - | 128K |
| SmolLM3 | 3B | - | 36.7%** | - | 128K |
| SmolLM2 | 1.7B | - | - | - | 8K |
*MATH-500 score with thinking mode enabled.\n**SmolLM3 AIME 2025 score with extended thinking mode enabled.
\nPhi-4 (14B parameters) scores 84.8% on MMLU, surpassing Phi-3’s 77.9% and competing with models several times its size 11. On competition-level math problems (MATH benchmark), Phi-4 achieves 56.1% compared to Phi-3’s 42.5%.
\nThe model was trained on 9.8 trillion tokens over 21 days using 1,920 H100 GPUs. Microsoft validated reasoning capability on the November 2024 AMC-10 and AMC-12 math competitions; these tests occurred after training data collection ended, suggesting genuine reasoning rather than benchmark memorization 25.
\nThe Phi-4 family has expanded significantly in 2025:
\nPhi-4-multimodal (5.6B parameters) integrates speech, vision, and text processing into a single unified architecture. It claimed the top position on the HuggingFace OpenASR leaderboard with a word error rate of 6.14%, surpassing the previous best of 6.5% 26.
\nPhi-4-mini (3.8B parameters) matches models in the 7-9B range on reasoning and multilingual tasks.
\nPhi-4-reasoning (14B parameters) achieves performance comparable to DeepSeek-R1 (671B parameters) on AIME 2025, trained via supervised fine-tuning on demonstrations generated by o3-mini 27.
\nPhi-4-mini-flash-reasoning uses a hybrid architecture that achieves up to 10x higher throughput and 2-3x reduction in latency compared to Phi-4-mini, targeting edge devices and latency-constrained environments 28.
\nGemma 3 spans five parameter sizes: 270M, 1B, 4B, 12B, and 27B 24. The 4B, 12B, and 27B variants process both images and text; the 1B variant handles text only.
\nGemma-3-4B-IT beats Gemma-2-27B-IT across benchmarks, demonstrating architectural improvements rather than just scaling 29. Training data includes double the multilingual content of Gemma 2, supporting over 140 languages with improved tokenization for Chinese, Japanese, and Korean.
\nGemma 3 270M represents an extreme efficiency target: 170 million embedding parameters plus 100 million transformer parameters. Internal tests on a Pixel 9 Pro showed the INT4-quantized model consumed just 0.75% battery for 25 conversations 30.
\nGemma 3n represents a major 2025 advancement for on-device AI. Available in E2B (5B raw/2B effective) and E4B (8B raw/4B effective) sizes, these models use the MatFormer architecture to run with as little as 2GB (E2B) or 3GB (E4B) of memory 3. The E4B version is the first model under 10B parameters to achieve an LMArena score over 1300. Gemma 3n natively supports image, audio, video, and text inputs, with 140 language support.
\nTranslateGemma (2025) is a suite of open translation models built on Gemma 3 in 4B, 12B, and 27B sizes, translating across 55 languages without sacrificing quality 31.
\nQwen3 offers models at 0.6B, 1.7B, 4B, 8B, 14B, 32B, and the MoE variant 30B-A3B 4. All Qwen3 models feature dual reasoning modes: thinking mode for complex reasoning and non-thinking mode for fast responses.
\nThe performance gains are substantial: Qwen3-4B rivals Qwen2.5-72B-Instruct despite having 18x fewer parameters. Qwen3-4B achieves 83.7% on MMLU-Redux and 97.0% on MATH-500 in thinking mode 32.
\nQwen3-30B-A3B uses MoE with 30.5B total parameters and 3.3B active, outcompeting QwQ-32B while using 10x fewer activated parameters. Most teams in 2026 should default to this model for its balance of performance and efficiency 33.
\nAll variants support 32K token context windows, with 100+ languages and dialects.
\nLlama 3.2 includes 1B and 3B text-only models designed for edge and mobile deployment 13. Both support 128K token context and work with Qualcomm, MediaTek, and ARM processors.
\nThe 3B model scores 63.4% on MMLU and 77.4% on IFEval (instruction following), beating Gemma 2B IT (61.9%) and Phi-3.5-mini IT (59.2%) on the latter 34. Tool use capability shows a large jump between model sizes: the 3B scores 67.0% on BFCL V2 compared to 25.7% for the 1B.
\nLlama 4 Scout (April 2025) uses MoE with 17B active parameters and 109B total, fitting on a single H100 GPU. It supports a 10 million token context window and was trained on 40 trillion tokens of multimodal data. It beats Gemma 3, Gemini 2.0 Flash-Lite, and Mistral 3.1 across benchmarks 23.
\nSmolLM2 targets the sub-2B parameter range with three sizes: 135M, 360M, and 1.7B 10. SmolLM2-1.7B outperforms Meta’s Llama-1B on HellaSwag (68.7% vs 61.2%), ARC Average (60.5% vs 49.2%), and PIQA (77.6% vs 74.8%).
\nSmolLM3 (3B parameters) pushes into reasoning territory. With extended thinking enabled, it achieves 36.7% on AIME 2025 versus 9.3% without, and 30.0% on LiveCodeBench versus 15.2% 22. The model was trained on 11.2 trillion tokens using a three-stage strategy mixing web, math, and code data.
\nSmolLM3 outperforms Llama 3.2 3B and Qwen2.5 3B while staying competitive with larger 4B alternatives like Qwen3 and Gemma3. It supports 6 languages (English, French, Spanish, German, Italian, Portuguese) with 64K native context and 128K via YARN extrapolation 22.
\n![\"SLM](\"https://blog.ecitis.org/feeds/figures/small-language-models-1.webp\")
For server inference, small models shine on cost efficiency. A single NVIDIA A100 can serve Phi-4 at high throughput using vLLM or TensorRT-LLM with FP8 quantization. Memory requirements for a 14B model in FP16 run around 28GB; with INT4 quantization, this drops to approximately 7GB.
\nLlama 4 Scout, despite 109B total parameters, fits on a single H100 due to its MoE architecture with only 17B active parameters 23.
\nModern MacBooks with Apple Silicon run SLMs through llama.cpp with Metal acceleration. The M3 Max with 128GB unified memory can run Phi-4 without quantization; the base M3 with 8GB works well with 3-4B models using Q4_K_M quantization 35.
\nOn Windows and Linux, Ollama provides the simplest path to local deployment. NVIDIA GPUs from the RTX 3060 onward handle 7B models comfortably; the RTX 4090’s 24GB VRAM accommodates 14B models in FP16.
\nThe 2023-2025 period saw an “Intelligence Explosion” with 70+ TOPS NPUs and 8-24GB unified memory. 4B+ parameter LLMs now run locally at conversational speeds 36.
\nRaspberry Pi 5 (8GB) runs SmolLM2-1.7B at usable speeds with INT4 quantization. NVIDIA Jetson Orin devices provide GPU acceleration for models up to 7B parameters with proper quantization 37.
\nNPUs (Neural Processing Units) in recent laptop chips accelerate specific operations. Microsoft’s Phi Silica is optimized for Snapdragon-powered Copilot+ PCs using ONNX and low-bit quantization 26.
\nExecuTorch simplifies deployment by letting developers deploy PyTorch models directly to edge devices, running 8B parameter LLMs on smartphones at 30+ tokens/second 36.
\nGemma 3n E2B targets phones directly. The model fits in 2GB of memory and runs inference without noticeable battery drain 3. Over 600 projects were submitted to the Gemma 3n Impact Challenge on Kaggle within weeks of release.
\nLlama 3.2 1B works on iOS through frameworks like llama.cpp compiled for Apple platforms. Android deployment uses similar approaches with the NDK.
\nTop recommended LLMs for edge AI deployment in 2026 include Meta-Llama-3.1-8B-Instruct, GLM-4-9B-0414, and Qwen2.5-VL-7B-Instruct for their balance of performance and computational efficiency 38.
\nWebGPU enables in-browser inference for small models. Libraries like transformers.js and llama.cpp’s WASM build run models up to 1B parameters in modern browsers, though performance trails native execution.
\nSmall models outperform large models in several scenarios, not just match them at lower cost.
\nCode completion requires sub-100ms response times to feel responsive. A local 3B model delivers suggestions before the developer notices any delay. A cloud API, even with low network latency, adds perceptible lag.
\nReal-time translation for live captioning has similar constraints. The translation must appear within a second of speech; network round-trips eat into this budget.
\nA 3B model fine-tuned on legal documents often outperforms a 70B general model on legal tasks. The fine-tuned model learns domain vocabulary, citation formats, and reasoning patterns that the general model treats as edge cases.
\nMedical coding, financial analysis, and technical documentation all benefit from this specialization. The smaller parameter count makes fine-tuning affordable.
\nMicrosoft’s OptiMind (20B parameters) converts business problems described in natural language into mathematical formulations for optimization software, running locally to keep sensitive business data private 39.
\nSmall language models are sufficiently powerful, inherently more suitable, and necessarily more economical for many invocations in agentic systems 40. Qwen3’s dual-mode reasoning and improved agent capabilities make small models viable for tool use and multi-step workflows.
\nProcessing millions of documents for classification or extraction favors small models. A Qwen3 0.6B model can classify documents at 10-50x the throughput of a 70B model on the same hardware. For tasks where a small model achieves sufficient accuracy, this throughput advantage compounds into major cost savings.
\nIndustrial quality control systems, autonomous vehicles, and IoT devices cannot rely on cloud connectivity. A local SLM provides consistent capability regardless of network conditions.
\nSmall models adapt faster and more cheaply than large ones. The same LoRA configuration that requires 24GB VRAM for a 70B model fits in 8GB for a 7B model.
\nLow-Rank Adaptation (LoRA) freezes base model weights and trains small adapter matrices 41. This reduces trainable parameters by orders of magnitude; a typical LoRA configuration adds only 0.1-1% additional parameters.
\nQLoRA combines LoRA with 4-bit quantization, enabling fine-tuning of 7B models on consumer GPUs with 8GB VRAM. The quantized base model consumes less memory, leaving room for optimizer states and gradients.
\nfrom transformers import AutoModelForCausalLM, BitsAndBytesConfig\nfrom peft import LoraConfig, get_peft_model\n\n# Load model with 4-bit quantization\nquantization_config = BitsAndBytesConfig(\n load_in_4bit=True,\n bnb_4bit_quant_type=\"nf4\",\n bnb_4bit_compute_dtype=torch.bfloat16,\n)\n\nmodel = AutoModelForCausalLM.from_pretrained(\n \"Qwen/Qwen3-4B-Instruct\",\n quantization_config=quantization_config,\n)\n\n# Apply LoRA\nlora_config = LoraConfig(\n r=16,\n lora_alpha=32,\n target_modules=[\"q_proj\", \"v_proj\"],\n lora_dropout=0.05,\n)\n\nmodel = get_peft_model(model, lora_config)Fine-tuning a 3B model on a single RTX 4090 takes hours rather than days. A custom medical coding model might require 10,000 examples and 3 epochs; this completes overnight on consumer hardware.
\nPEFT techniques reduce peak memory by 50-70% compared to full fine-tuning while preserving most of the accuracy gain 42. For SLMs, this means genuine fine-tuning accessibility for individuals and small teams.
\nResearch frameworks now support LoRA fine-tuning on mobile GPUs. Tether Data’s QVAC-fabric-llm integrates LoRA training into the llama.cpp ecosystem, enabling fine-tuning on phones with Mali, Adreno, and Apple GPUs 43. This opens possibilities for personalized on-device models that adapt to individual users.
\nOllama provides the simplest path from zero to running model:
\n# Install Ollama (macOS/Linux)\ncurl -fsSL https://ollama.com/install.sh | sh\n\n# Pull and run Phi-4\nollama run phi4\n\n# Pull and run Qwen3\nollama run qwen3:4b\n\n# Run Gemma 3n\nollama run gemma3n\n\n# Run with specific quantization\nollama run qwen3:4b-instruct-q4_K_MOllama handles model downloading, quantization selection, and GPU acceleration automatically.
\nFor more control, llama.cpp provides direct access to inference parameters:
\n# Build llama.cpp\ngit clone https://github.com/ggerganov/llama.cpp\ncd llama.cpp\ncmake -B build -DGGML_METAL=ON # macOS with Metal\ncmake --build build --config Release\n\n# Run inference\n./build/bin/llama-cli \\\n -m models/qwen3-4b-instruct-q4_k_m.gguf \\\n -ngl 99 \\\n -c 4096 \\\n -p \"Explain the difference between LoRA and full fine-tuning:\"Key flags:
\n-ngl 99: Offload all layers to GPU-c 4096: Context window size-fa: Enable flash attention (reduces memory)-b 512: Batch size for prompt processingDirect integration with Hugging Face transformers:
\nfrom transformers import AutoModelForCausalLM, AutoTokenizer\nimport torch\n\nmodel_name = \"Qwen/Qwen3-4B-Instruct\"\n\ntokenizer = AutoTokenizer.from_pretrained(model_name)\nmodel = AutoModelForCausalLM.from_pretrained(\n model_name,\n torch_dtype=torch.bfloat16,\n device_map=\"auto\",\n)\n\nmessages = [\n {\"role\": \"user\", \"content\": \"Write a Python function to calculate Fibonacci numbers.\"}\n]\n\ntext = tokenizer.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)\ninputs = tokenizer(text, return_tensors=\"pt\").to(model.device)\n\noutputs = model.generate(**inputs, max_new_tokens=512, temperature=0.7)\nprint(tokenizer.decode(outputs[0], skip_special_tokens=True))Apple’s MLX framework provides optimized inference on M-series chips:
\nfrom mlx_lm import load, generate\n\nmodel, tokenizer = load(\"mlx-community/Qwen3-4B-Instruct-4bit\")\n\nprompt = \"Explain quantum entanglement in simple terms:\"\nresponse = generate(model, tokenizer, prompt=prompt, max_tokens=256)\nprint(response)MLX leverages unified memory architecture, avoiding the CPU-GPU transfer overhead present on discrete GPU systems.
\nSelection depends on your constraints and requirements:
\nFor maximum capability in the SLM range: Qwen3-4B leads with 83.7% MMLU and near-perfect MATH-500 scores in thinking mode, rivaling Qwen2.5-72B at 18x fewer parameters.
\nFor mobile and edge deployment: Gemma 3n E2B runs with 2GB memory and achieves 60.1% MMLU. SmolLM2-1.7B provides capable performance on devices with 6GB RAM.
\nFor maximum context: Llama 4 Scout supports 10 million tokens. For more accessible hardware, most models now support 128K tokens.
\nFor multilingual applications: Qwen3 supports 100+ languages. Gemma 3n covers 140 languages with improved CJK tokenization.
\nFor code generation: Qwen2.5-Coder variants are purpose-built for programming tasks. Phi-4-mini also shows strong coding performance.
\nFor structured reasoning: SmolLM3 with extended thinking mode provides chain-of-thought reasoning in a 3B package. Qwen3 models support seamless switching between thinking and non-thinking modes.
\nFor multimodal tasks: Phi-4-multimodal handles text, speech, and vision. Gemma 3n processes image, audio, video, and text inputs.
\nThe SLM space continues to evolve rapidly. Model efficiency improves faster than raw capability scaling. Qwen3-4B matches or exceeds Qwen2.5-72B on many benchmarks, a 142-fold reduction in required parameters for comparable MMLU performance since 2022 44.
\nHardware trends reinforce this direction. NPUs in consumer devices, improved quantization techniques, and frameworks like MLX, llama.cpp, and ExecuTorch reduce the friction of local deployment. By 2027, running a capable local model may be as routine as running a web browser.
\nA 2025 NVIDIA position paper argues that “the next real leap forward won’t come from models getting bigger. It’ll come from them getting smaller” 40. This shift will significantly impact the future of on-device and edge computing.
\nThe practical takeaway: evaluate whether a small model meets your accuracy requirements before defaulting to large models. For many production applications, a fine-tuned 3B model outperforms a general 70B model while costing a fraction to deploy and operate.
\nBentoML. “The Best Open-Source Small Language Models (SLMs) in 2026.” https://www.bentoml.com/blog/the-best-open-source-small-language-models ↩
\nWikipedia. “Small language model.” https://en.wikipedia.org/wiki/Small_language_model ↩
\nGoogle Developers Blog. “Introducing Gemma 3n: The developer guide.” https://developers.googleblog.com/en/introducing-gemma-3n-developer-guide/ ↩ ↩2 ↩3 ↩4
\nQwen Team. “Qwen3: Think Deeper, Act Faster.” https://qwenlm.github.io/blog/qwen3/ ↩ ↩2 ↩3 ↩4 ↩5 ↩6
\nInfoQ. “Cactus v1: Cross-Platform LLM Inference on Mobile with Zero Latency and Full Privacy.” https://www.infoq.com/news/2025/12/cactus-on-device-inference/ ↩
\nPMC. “Tiny Machine Learning and On-Device Inference: A Survey.” https://pmc.ncbi.nlm.nih.gov/articles/PMC12115890/ ↩
\nCactus AI documentation and benchmarks, 2025. ↩
\nNovus. “The Rise of Local AI Models: Going Small to Go Big.” https://www.novusasi.com/blog/the-rise-of-local-ai-models-going-small-to-go-big ↩
\nTechCrunch. “In 2026, AI will move from hype to pragmatism.” https://techcrunch.com/2026/01/02/in-2026-ai-will-move-from-hype-to-pragmatism/ ↩
\nHuggingFace Blog. “SmolLM - blazingly fast and remarkably powerful.” https://huggingface.co/blog/smollm ↩ ↩2
\nMicrosoft. “Phi-4 Technical Report.” https://arxiv.org/html/2412.08905v1 ↩ ↩2
\nHuggingFace. “microsoft/Phi-4-mini-reasoning Model Card.” https://huggingface.co/microsoft/Phi-4-mini-reasoning ↩
\nMeta AI. “Llama 3.2: Revolutionizing edge AI and vision with open, customizable models.” https://ai.meta.com/blog/llama-3-2-connect-2024-vision-edge-mobile-devices/ ↩ ↩2
\narXiv. “MiniLLM: Knowledge Distillation of Large Language Models.” https://arxiv.org/abs/2306.08543 ↩
\narXiv. “Memorization Dynamics in Knowledge Distillation for Language Models.” https://arxiv.org/html/2601.15394 ↩
\nNVIDIA Technical Blog. “Pruning and Distilling LLMs Using NVIDIA TensorRT Model Optimizer.” https://developer.nvidia.com/blog/pruning-and-distilling-llms-using-nvidia-tensorrt-model-optimizer/ ↩
\nGoogle Research. “Distilling step-by-step: Outperforming larger language models with less training.” https://research.google/blog/distilling-step-by-step-outperforming-larger-language-models-with-less-training-data-and-smaller-model-sizes/ ↩
\nIBM. “What is grouped query attention (GQA)?” https://www.ibm.com/think/topics/grouped-query-attention ↩
\nACL Anthology. “Cost-Optimal Grouped-Query Attention for Long-Context Modeling.” https://aclanthology.org/2025.emnlp-main.272/ ↩
\narXiv. “Gemma 2: Improving Open Language Models at a Practical Size.” https://arxiv.org/abs/2408.00118 ↩
\nSebastian Raschka. “The Big LLM Architecture Comparison.” https://magazine.sebastianraschka.com/p/the-big-llm-architecture-comparison ↩
\nHuggingFace Blog. “SmolLM3: smol, multilingual, long-context reasoner.” https://huggingface.co/blog/smollm3 ↩ ↩2 ↩3
\nMeta AI. “The Llama 4 herd: The beginning of a new era of natively multimodal AI innovation.” https://ai.meta.com/blog/llama-4-multimodal-intelligence/ ↩ ↩2 ↩3 ↩4
\nGoogle AI for Developers. “Gemma 3 model overview.” https://ai.google.dev/gemma/docs/core ↩ ↩2
\nMicrosoft Community Hub. “Phi-4: Small Language Models That Pack a Punch.” https://techcommunity.microsoft.com/blog/educatordeveloperblog/phi-4-small-language-models-that-pack-a-punch/4464167 ↩
\nMicrosoft Community Hub. “Welcome to the new Phi-4 models - Microsoft Phi-4-mini & Phi-4-multimodal.” https://techcommunity.microsoft.com/blog/educatordeveloperblog/welcome-to-the-new-phi-4-models---microsoft-phi-4-mini—phi-4-multimodal/4386037 ↩ ↩2
\nMicrosoft Research. “Phi-4-reasoning Technical Report.” https://www.microsoft.com/en-us/research/publication/phi-4-reasoning-technical-report/ ↩
\nMicrosoft Azure Blog. “Reasoning reimagined: Introducing Phi-4-mini-flash-reasoning.” https://azure.microsoft.com/en-us/blog/reasoning-reimagined-introducing-phi-4-mini-flash-reasoning/ ↩
\nHuggingFace Blog. “Welcome Gemma 3: Google’s all new multimodal, multilingual, long context open LLM.” https://huggingface.co/blog/gemma3 ↩
\nGoogle Developers Blog. “Introducing Gemma 3 270M: The compact model for hyper-efficient AI.” https://developers.googleblog.com/en/introducing-gemma-3-270m/ ↩
\nGoogle Blog. “TranslateGemma: A new family of open translation models.” https://blog.google/technology/developers/translategemma/ ↩
\nOpen Laboratory. “Qwen3 4B.” https://openlaboratory.ai/models/qwen3-4b ↩
\nInterconnects. “Qwen 3: The new open standard.” https://www.interconnects.ai/p/qwen-3-the-new-open-standard ↩
\nEncord. “Llama 3.2: Advanced Vision and Edge AI Models for Mobile and Cloud.” https://encord.com/blog/lama-3-2-explained/ ↩
\nInvestGlass. “How to Run LLMs Locally: Complete 2025 Guide to Self-Hosted AI Models.” https://www.investglass.com/en_gb/how-to-run-llms-locally-complete-2025-guide-to-self-hosted-ai-models/ ↩
\nSiliconFlow. “Ultimate Guide - The Best LLMs For Mobile Deployment In 2026.” https://www.siliconflow.com/articles/en/best-LLMs-for-mobile-deployment ↩ ↩2
\nSabrePC Blog. “Popular Small Language Models to Run Locally.” https://www.sabrepc.com/blog/deep-learning-and-ai/popular-small-language-models-to-run-locally ↩
\nSiliconFlow. “Ultimate Guide - The Best LLMs for Edge AI Devices in 2026.” https://www.siliconflow.com/articles/en/best-llms-for-edge-ai-devices-2025 ↩
\nMicrosoft Research. “OptiMind: A small language model with optimization expertise.” https://www.microsoft.com/en-us/research/blog/optimind-a-small-language-model-with-optimization-expertise/ ↩
\nNVIDIA Research. “Small Language Models are the Future of Agentic AI.” https://research.nvidia.com/labs/lpr/slm-agents/ ↩ ↩2
\nDataCamp. “LLM Distillation Explained: Applications, Implementation & More.” https://www.datacamp.com/blog/distillation-llm ↩
\nDatabricks. “Efficient Fine-Tuning with LoRA: A Guide to Optimal Parameter Selection for Large Language Models.” https://www.databricks.com/blog/efficient-fine-tuning-lora-guide-llms ↩
\nHuggingFace Blog. “An Edge-First Generalized LLM LoRA Fine-Tuning Framework for Heterogeneous GPUs.” https://huggingface.co/blog/qvac/fabric-llm-finetune ↩
\nStanford HAI. “2025 AI Index Report: Technical Performance.” https://hai.stanford.edu/ai-index/2025-ai-index-report/technical-performance ↩
\nDeploying LLMs at scale requires more than loading a model and serving requests. Production systems must handle concurrent users, minimize latency, maximize GPU utilization, and provide observability. NVIDIA’s TensorRT-LLM and Triton Inference Server form a battle-tested stack for these requirements.
\nTensorRT-LLM became fully open-source in March 2025 and now delivers over 40,000 tokens per second on Blackwell B200 GPUs running Llama 41. The stack integrates with NVIDIA Dynamo for datacenter-scale orchestration across thousands of GPUs2.
\nThis guide covers the complete deployment pipeline: building optimized TensorRT engines, configuring Triton for LLM workloads, and tuning for production performance.
\nTensorRT-LLM is NVIDIA’s open-source library for compiling and running large language models on NVIDIA GPUs. Built on PyTorch, it provides a Python API for model definition while generating highly optimized CUDA kernels for inference3. The current release (January 2026) uses PyTorch 2.9.0, TensorRT 10.9, and CUDA 12.8.14.
\nThe library handles several optimization categories:
\nQuantization: TensorRT-LLM supports NVFP4, FP8, INT4 AWQ, and INT8 SmoothQuant quantization formats. NVFP4 is a 4-bit floating-point format introduced with Blackwell GPUs that reduces KV cache memory by 50% compared to FP8 while maintaining less than 1% accuracy loss on benchmarks including LiveCodeBench, MMLU-PRO, and MBPP5. FP8 on Hopper and Blackwell architectures delivers 2.5-3x inference speed improvements compared to FP166.
\nKernel fusion: Multiple transformer operations combine into single CUDA kernels. LayerNorm, matrix multiplications, bias additions, and activation functions execute together instead of requiring separate kernel launches and memory transfers7.
\nAttention optimizations: Custom FlashAttention kernels, multi-head/multi-query/grouped-query attention support, and fused attention implementations reduce memory bandwidth requirements.
\nParallelism: Tensor parallelism splits matrix multiplications across GPUs. Pipeline parallelism distributes model layers sequentially across devices. Wide expert parallelism (EP) enables efficient Mixture-of-Experts inference on models like DeepSeek-R1 and Llama 48. All strategies enable serving models larger than single-GPU memory9.
\nSpeculative decoding: TensorRT-LLM supports EAGLE-3, multi-token prediction (MTP), and ReDrafter techniques for accelerated token generation. EAGLE-3 with speculative decoding achieves up to 4x speedup on Llama 4 Maverick10. ReDrafter, developed by Apple and integrated into TensorRT-LLM, achieves up to 2.7x throughput improvements on H100 GPUs11.
\n![\"Triton](\"https://blog.ecitis.org/feeds/figures/tensorrt-triton-inference-0.webp\")
TensorRT-LLM converts model weights into optimized TensorRT engines through a two-step process: checkpoint conversion and engine building.
\nThe quantize.py script converts Hugging Face checkpoints to TensorRT-LLM format while applying quantization:
# NVFP4 quantization (Blackwell GPUs - recommended for B200/GB200)\npython examples/quantization/quantize.py \\\n --model_dir /path/to/llama-70b \\\n --qformat nvfp4 \\\n --kv_cache_dtype nvfp4 \\\n --output_dir /output/llama-70b-nvfp4 \\\n --tp_size 4\n\n# FP8 quantization (Hopper/Ada/Blackwell GPUs)\npython examples/quantization/quantize.py \\\n --model_dir /path/to/llama-70b \\\n --qformat fp8 \\\n --kv_cache_dtype fp8 \\\n --output_dir /output/llama-70b-fp8 \\\n --tp_size 4\n\n# INT4 AWQ quantization (all GPU generations)\npython examples/quantization/quantize.py \\\n --model_dir /path/to/llama-70b \\\n --qformat int4_awq \\\n --awq_block_size 64 \\\n --output_dir /output/llama-70b-int4awq \\\n --tp_size 4The --tp_size parameter specifies tensor parallelism degree. Set this to the number of GPUs you will use for inference. INT4 AWQ uses block-wise quantization; smaller block sizes (64 vs 128) provide better accuracy at marginal compute cost12. NVFP4 uses block-wise quantization with size 16 and FP8 scaling factors for higher precision during dequantization5.
The trtllm-build command compiles checkpoints into TensorRT engines:
trtllm-build \\\n --checkpoint_dir /output/llama-70b-fp8 \\\n --output_dir /engines/llama-70b-fp8 \\\n --gemm_plugin fp8 \\\n --gpt_attention_plugin fp8 \\\n --max_batch_size 64 \\\n --max_input_len 4096 \\\n --max_seq_len 8192 \\\n --use_fused_mlp enable \\\n --workers 4Key build parameters:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Parameter | Purpose |
|---|---|
--gemm_plugin | Enables cuBLASLt for optimized matrix operations |
--gpt_attention_plugin | Uses efficient attention kernels with in-place KV cache updates |
--use_fused_mlp | Enables horizontal fusion in GatedMLP layers |
--max_batch_size | Maximum concurrent sequences the engine supports |
--max_input_len | Maximum input context length |
--max_seq_len | Maximum total sequence length (input + output) |
For FP8 on Hopper GPUs, the GEMM + SwiGLU fusion in Gated-MLP combines two Matmul operations and one SwiGLU operation into a single kernel13.
\nTensorRT’s compiler identifies and fuses operation sequences automatically. Common fusion patterns include:
\nThe --reduce_fusion enable flag eliminates extra copies from local buffers to shared buffers in communication kernels14.
Disaggregated serving separates compute-intensive prefill operations from memory-bound decode operations onto specialized hardware clusters. This architecture addresses the fundamental mismatch between prefill (compute-bound, benefits from high FLOPS) and decode (memory-bound, benefits from high memory bandwidth) phases15.
\nTensorRT-LLM supports three disaggregated serving approaches:
\ntrtllm-serve: A command-line utility that deploys OpenAI-compatible servers for each context and generation instance, with an orchestrator coordinating requests.
\nDynamo integration: NVIDIA Dynamo orchestrates requests across prefill and decode workers with KV-cache-aware routing. The smart router determines optimal decode workers based on KV cache block availability2.
\nNIXL acceleration: The NVIDIA Inference Exchange Library (NIXL) accelerates KV cache transfer between GPUs with low-latency communication primitives.
\nDisaggregated architectures demonstrate up to 6.4x throughput improvements and 20x reduction in latency variance. Organizations report 15-40% infrastructure cost reductions through optimized hardware allocation16.
\nTraditional batching waits until a batch fills before processing. In-flight batching (also called continuous batching or iteration-level batching) processes new requests immediately without waiting for existing sequences to complete17.
\nThe TensorRT-LLM scheduler manages two phases:
\nWith in-flight batching, sequences in context phase process together with sequences in generation phase. When a generation sequence finishes, a new context sequence can immediately take its slot. This keeps GPU utilization high even with variable-length inputs and outputs.
\nInstead of allocating KV cache as contiguous memory blocks, paged attention splits the cache into smaller blocks that can be allocated non-contiguously18. This approach:
\nThe paged KV cache allocates memory upfront in TensorRT-LLM rather than on-demand. Plan for approximately 60% additional VRAM beyond model weights for KV cache allocation19.
\nLong input contexts can delay generation for concurrent requests. Chunked prefill divides the context phase into smaller chunks, enabling better parallelization with decode operations20.
\nThis feature allows GPU systems to handle longer contexts and higher concurrency by decoupling memory consumption from context length.
\nTriton provides the serving infrastructure around TensorRT-LLM engines. It handles request routing, model loading, batching, and metrics collection. The OpenAI-compatible frontend transitioned from beta to stable in 2025, enabling drop-in compatibility with OpenAI API clients21.
\nModel Repository: A directory structure containing model configurations and artifacts. Each model has a config.pbtxt file defining inputs, outputs, and backend settings.
Scheduler: Routes incoming requests to model instances. For LLMs, the scheduler typically delegates batching decisions to the TensorRT-LLM runtime.
\nBackend Manager: Loads and manages model backends. The TensorRT-LLM backend uses the C++ Executor API for optimal performance.
\nMetrics Server: Exposes Prometheus-compatible metrics on port 8002 by default.
\nSecurity note: Organizations should update to Triton version 25.07 or later to address CVE-2025-23319, CVE-2025-23320, and CVE-2025-23334, which when chained could allow unauthenticated remote code execution22.
\nThe TensorRT-LLM backend uses an ensemble of three models:
\nmodel_repository/\n├── ensemble/\n│ └── config.pbtxt\n├── preprocessing/\n│ ├── config.pbtxt\n│ └── 1/model.py\n├── tensorrt_llm/\n│ ├── config.pbtxt\n│ └── 1/\n│ └── [engine files]\n└── postprocessing/\n ├── config.pbtxt\n └── 1/model.pyPreprocessing: Tokenizes input text using the model’s tokenizer\nTensorRT-LLM: Runs inference on the optimized engine\nPostprocessing: Detokenizes output IDs back to text
\nThe ensemble model chains these together automatically.
\nThe core configuration for the TensorRT-LLM backend:
\nname: \"tensorrt_llm\"\nbackend: \"tensorrtllm\"\nmax_batch_size: 64\n\nmodel_transaction_policy {\n decoupled: true\n}\n\ninput [\n { name: \"input_ids\" data_type: TYPE_INT32 dims: [-1] },\n { name: \"input_lengths\" data_type: TYPE_INT32 dims: [1] },\n { name: \"request_output_len\" data_type: TYPE_INT32 dims: [1] },\n { name: \"end_id\" data_type: TYPE_INT32 dims: [1] },\n { name: \"pad_id\" data_type: TYPE_INT32 dims: [1] },\n { name: \"stream\" data_type: TYPE_BOOL dims: [1] optional: true }\n]\n\noutput [\n { name: \"output_ids\" data_type: TYPE_INT32 dims: [-1] },\n { name: \"sequence_length\" data_type: TYPE_INT32 dims: [1] }\n]\n\nparameters {\n key: \"gpt_model_path\"\n value: { string_value: \"/engines/llama-70b-fp8\" }\n}\n\nparameters {\n key: \"batching_type\"\n value: { string_value: \"inflight_fused_batching\" }\n}\n\nparameters {\n key: \"max_tokens_in_paged_kv_cache\"\n value: { string_value: \"2048000\" }\n}\n\nparameters {\n key: \"kv_cache_free_gpu_mem_fraction\"\n value: { string_value: \"0.85\" }\n}Key parameters explained:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Parameter | Value | Purpose |
|---|---|---|
decoupled: true | Required for streaming | Enables async responses |
batching_type | inflight_fused_batching | Enables continuous batching |
max_tokens_in_paged_kv_cache | Token count | Total KV cache capacity |
kv_cache_free_gpu_mem_fraction | 0.0-1.0 | Fraction of free GPU memory for KV cache |
The instance_count parameter controls concurrent execution. For most workloads, set this to 5 or higher23:
instance_group [\n {\n count: 5\n kind: KIND_GPU\n gpus: [0, 1, 2, 3]\n }\n]Control request queuing behavior:
\nparameters {\n key: \"max_queue_delay_microseconds\"\n value: { string_value: \"100000\" }\n}\n\nparameters {\n key: \"max_queue_size\"\n value: { string_value: \"256\" }\n}Setting max_queue_delay_microseconds above 0 improves batch formation by waiting for additional requests to arrive.
docker pull nvcr.io/nvidia/tritonserver:25.10-py3# Clone the backend repository\ngit clone https://github.com/triton-inference-server/tensorrtllm_backend.git\ncd tensorrtllm_backend\n\n# Copy template models\nmkdir -p /triton_models\ncp -r all_models/inflight_batcher_llm/* /triton_models/Follow the engine building steps from earlier, placing the output in /engines/.
Use the provided template filling script:
\nENGINE_DIR=/engines/llama-70b-fp8\nTOKENIZER_DIR=/models/llama-70b\nMAX_BATCH=64\n\npython3 tools/fill_template.py -i /triton_models/preprocessing/config.pbtxt \\\n tokenizer_dir:${TOKENIZER_DIR},triton_max_batch_size:${MAX_BATCH}\n\npython3 tools/fill_template.py -i /triton_models/tensorrt_llm/config.pbtxt \\\n triton_backend:tensorrtllm,triton_max_batch_size:${MAX_BATCH},\\\n decoupled_mode:true,engine_dir:${ENGINE_DIR},\\\n batching_type:inflight_fused_batching\n\npython3 tools/fill_template.py -i /triton_models/postprocessing/config.pbtxt \\\n tokenizer_dir:${TOKENIZER_DIR},triton_max_batch_size:${MAX_BATCH}\n\npython3 tools/fill_template.py -i /triton_models/ensemble/config.pbtxt \\\n triton_max_batch_size:${MAX_BATCH}python3 scripts/launch_triton_server.py \\\n --model_repo /triton_models \\\n --world_size 4\n\n# Or directly with tritonserver\ntritonserver \\\n --model-repository=/triton_models \\\n --http-port=8000 \\\n --grpc-port=8001 \\\n --metrics-port=8002curl localhost:8000/v2/health/ready\n# Response: {\"ready\":true}\n\ncurl localhost:8000/v2/models\n# Lists all loaded models with READY statusThe relationship between max_batch_size, engine build parameters, and runtime behavior:
max_batch_size: Hard limit set at build timemax_batch_size: Soft limit for request acceptanceThe TRT-LLM scheduler can form batches larger than Triton’s max_batch_size when using in-flight batching. The scheduler optimizes based on available KV cache memory and pending requests24.
Balance KV cache size against model memory requirements:
\n# Calculate KV cache memory\nkv_cache_tokens = max_batch_size * max_seq_len\nkv_cache_bytes = kv_cache_tokens * num_layers * 2 * hidden_size * dtype_bytesFor a 70B model with 80 layers, 8192 hidden size, and FP16 KV cache:
\nUse kv_cache_free_gpu_mem_fraction to limit allocation to available memory. Start with 0.85 and adjust based on OOM behavior.
TensorRT-LLM uses CUDA Graphs to reduce kernel launch overhead. The runtime captures execution graphs for common batch sizes and replays them without CPU intervention.
\nCUDA Graph padding handles mismatched batch sizes by padding to the nearest captured graph size. This trades minor compute waste for consistent low-latency execution25.
\nFor tensor parallelism across GPUs:
\n# 4-way tensor parallelism\ntrtllm-build --tp_size 4 ...\n\n# Launch with matching world size\npython3 launch_triton_server.py --world_size 4The backend uses MPI to coordinate execution across GPUs. Leader mode uses one process to manage inference; Orchestrator mode distributes coordination26.
\nTriton exposes metrics at http://localhost:8002/metrics by default. Enable with:
tritonserver --allow-metrics=true --allow-gpu-metrics=trueThe TensorRT-LLM backend exposes custom metrics:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Metric | Description |
|---|---|
nv_trt_llm_request_count | Total inference requests |
nv_trt_llm_inflight_request_count | Currently processing requests |
nv_trt_llm_kv_cache_block_usage | KV cache utilization |
nv_trt_llm_generation_tokens_per_second | Output throughput |
Standard Triton metrics include:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Metric | Description |
|---|---|
nv_inference_request_success | Successful request count |
nv_inference_compute_output_duration_us | Inference latency |
nv_gpu_utilization | GPU compute utilization |
nv_gpu_memory_used_bytes | GPU memory consumption |
NVIDIA provides pre-built Grafana dashboards in the tutorials repository27. Import the JSON configuration:
\n# Download dashboard JSON\ncurl -O https://raw.githubusercontent.com/triton-inference-server/tutorials/main/\\\nDeployment/Kubernetes/TensorRT-LLM_Autoscaling_and_Load_Balancing/\\\ngrafana_inference-metrics_dashboard.jsonConfigure Prometheus as a data source in Grafana, then import the dashboard JSON.
\nMeasure throughput and latency with GenAI-Perf:
\ngenai-perf \\\n --model ensemble \\\n --backend tensorrtllm \\\n --endpoint localhost:8001 \\\n --streaming \\\n --concurrency 32 \\\n --input-sequence-length 512 \\\n --output-sequence-length 128The tool reports time-to-first-token, inter-token latency, throughput, and percentile statistics28.
\n![\"LLM](\"https://blog.ecitis.org/feeds/figures/tensorrt-triton-inference-1.webp\")
Best for maximum throughput when you can invest in setup complexity. January 2026 benchmarks show B200 delivering 60,000 tokens per second per GPU at 1,000 tokens per second per user interactivity on Llama 3.3 70B29. On Llama 4 Scout, B200 achieves over 42,000 tokens per second with a 3.4x performance increase over H2001.
\nStrengths: Peak throughput, Tensor Core optimization, deep NVIDIA integration, EAGLE-3 speculative decoding, NVFP4 quantization\nTrade-offs: Longer setup time (1-2 weeks for production tuning), engine rebuilds required for config changes
\nBest for teams prioritizing development velocity and concurrency handling. PagedAttention provides GPU-friendly memory layout without fragmentation30. vLLM v0.14.1 (January 2026) adds W4A8 grouped GEMM on Hopper, MoE + LoRA support with AWQ Marlin, and Transformers v5 RoPE compatibility31.
\nInferact Inc. launched in January 2026 to commercialize vLLM with 800M valuation32. The vLLM project now runs on over 400,000 GPUs worldwide.
\nStrengths: Easy setup (1-2 days), consistent latency under load, active community, broad hardware support (NVIDIA, AMD, Intel, TPU)\nTrade-offs: Lower peak throughput than TensorRT-LLM on Blackwell GPUs
\nSGLang has become a production standard, generating trillions of tokens daily across deployments at xAI, AMD, NVIDIA, LinkedIn, Cursor, and major cloud providers33. On H100 hardware, SGLang achieves 16,215 tokens per second, matching LMDeploy and exceeding vLLM by 29%34.
\nStrengths: RadixAttention for prefix caching (50%+ hit rates in production), zero-overhead CPU scheduler, prefill-decode disaggregation, native C++ optimization\nTrade-offs: Smaller ecosystem than vLLM
\nTGI is now in maintenance mode, with Hugging Face recommending vLLM or SGLang for new deployments35. TGI v3 achieves 13x speedups on prompts exceeding 200,000 tokens by reusing earlier token computations36.
\nStrengths: Prefix caching, long context handling, Hugging Face ecosystem, zero-config mode\nTrade-offs: Maintenance mode limits new feature development
\n| Requirement | Recommended Engine |
|---|---|
| Maximum throughput on Blackwell | TensorRT-LLM |
| Fast iteration cycles | vLLM or SGLang |
| High concurrency, consistent latency | vLLM |
| Prefix caching in production | SGLang |
| Long chat histories (200K+ tokens) | TGI v3 |
| Kubernetes-native deployment | Triton + TensorRT-LLM |
| Datacenter-scale orchestration | NVIDIA Dynamo |
| Multi-vendor hardware support | vLLM |
End-to-end deployment of Llama 3.1 70B on 4x H100 80GB:
\n# Pull containers\ndocker pull nvcr.io/nvidia/tritonserver:25.10-py3\ndocker pull nvcr.io/nvidia/pytorch:25.10-py3\n\n# Download model\nhuggingface-cli download meta-llama/Llama-3.1-70B-Instruct \\\n --local-dir /models/llama-3.1-70bdocker run --gpus all -v /models:/models -v /engines:/engines \\\n nvcr.io/nvidia/pytorch:25.10-py3 bash -c \"\n pip install tensorrt-llm\n\n # Quantize to FP8\n python -m tensorrt_llm.commands.quantize \\\n --model_dir /models/llama-3.1-70b \\\n --qformat fp8 \\\n --kv_cache_dtype fp8 \\\n --output_dir /engines/llama-70b-ckpt \\\n --tp_size 4\n\n # Build engine\n trtllm-build \\\n --checkpoint_dir /engines/llama-70b-ckpt \\\n --output_dir /engines/llama-70b-engine \\\n --gemm_plugin fp8 \\\n --gpt_attention_plugin fp8 \\\n --max_batch_size 64 \\\n --max_input_len 4096 \\\n --max_seq_len 8192 \\\n --use_fused_mlp enable \\\n --workers 4\n\"docker run --gpus all -p 8000:8000 -p 8001:8001 -p 8002:8002 \\\n -v /engines:/engines \\\n -v /models:/models \\\n -v /triton_models:/triton_models \\\n nvcr.io/nvidia/tritonserver:25.10-py3 bash -c \"\n # Configure models (using fill_template.py as shown earlier)\n # ...\n\n tritonserver \\\n --model-repository=/triton_models \\\n --allow-metrics=true \\\n --allow-gpu-metrics=true\n\"import tritonclient.grpc as grpcclient\nimport numpy as np\n\nclient = grpcclient.InferenceServerClient(url=\"localhost:8001\")\n\n# Prepare inputs\nprompt = \"Explain the attention mechanism in transformers:\"\ninput_ids = tokenizer.encode(prompt) # Use appropriate tokenizer\n\ninputs = [\n grpcclient.InferInput(\"text_input\", [1], \"BYTES\"),\n grpcclient.InferInput(\"max_tokens\", [1], \"INT32\"),\n grpcclient.InferInput(\"stream\", [1], \"BOOL\"),\n]\n\ninputs[0].set_data_from_numpy(np.array([[prompt]], dtype=object))\ninputs[1].set_data_from_numpy(np.array([[256]], dtype=np.int32))\ninputs[2].set_data_from_numpy(np.array([[True]], dtype=bool))\n\n# Stream responses\nfor response in client.infer(\"ensemble\", inputs, stream=True):\n output = response.as_numpy(\"text_output\")\n print(output[0].decode(), end=\"\", flush=True)NVIDIA Blackwell architecture (B200, GB200, GB300) delivers substantial inference improvements over Hopper:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Metric | B200 vs H200 |
|---|---|
| Tokens per second (Llama 3.3 70B) | 4x higher throughput29 |
| Tokens per second (Llama 4 Scout) | 3.4x improvement1 |
| DeepSeek-R1 inference | 5x vs Hopper per GPU37 |
| Memory per GPU | Up to 288GB HBM3e (Blackwell Ultra) |
The GB200 NVL72 rack-scale platform connects 72 Blackwell GPUs using fifth-generation NVLink with 1,800 GB/s bidirectional bandwidth between all chips38. Blackwell Ultra (GB300) delivers 45% higher DeepSeek-R1 throughput than GB200 with 1.5x more NVFP4 compute and 2x more attention-layer acceleration37.
\nKey Blackwell optimizations in TensorRT-LLM:
\nThe January 2026 TensorRT-LLM optimizations delivered up to 2.8x throughput increases per Blackwell GPU over the previous three months39.
\nTensorRT-LLM and Triton Inference Server provide production-grade LLM serving with:
\nThe setup complexity is higher than alternatives like vLLM or SGLang, but peak performance on Blackwell GPUs is also higher. For teams already in the NVIDIA ecosystem deploying at scale, this stack delivers consistent, optimized inference. Organizations prioritizing faster iteration should evaluate vLLM (broad hardware support, active development) or SGLang (production-proven prefix caching).
\nNVIDIA Accelerates Inference on Meta Llama 4 Scout and Maverick ↩ ↩2 ↩3
\nIntroducing NVFP4 for Efficient Low-Precision Inference ↩ ↩2
\nDelivering Massive Performance Leaps for MoE Inference on Blackwell ↩
\nBlackwell Breaks 1,000 TPS/User Barrier with Llama 4 Maverick ↩
\nTensorRT-LLM Supports Recurrent Drafting for LLM Inference ↩
\nNVIDIA Blackwell Ultra Sets New Inference Records in MLPerf ↩ ↩2
\nVoice and audio AI has advanced rapidly, with models now capable of real-time transcription, natural speech synthesis, voice cloning from seconds of audio, and full-duplex conversational interactions. This article provides a technical survey of the architectures behind speech-to-text, text-to-speech, voice conversion, and audio language models. We cover the mathematical foundations, practical training considerations, and deployment strategies for building production systems.
\nAutomatic speech recognition (ASR) converts audio waveforms into text. Modern ASR systems have moved from traditional hidden Markov models with hand-crafted acoustic features to end-to-end neural networks trained on massive datasets.
\nWhisper, released by OpenAI in September 2022, is a Transformer-based encoder-decoder model trained on 680,000 hours of multilingual and multitask supervised data collected from the web [1].
\nInput Processing
\nAudio is resampled to 16 kHz and converted to an 80-channel log-magnitude Mel spectrogram using 25ms windows with 10ms stride. The spectrogram is normalized to a [-1, 1] range with near-zero mean. For the large-v3 model, this was increased to 128 Mel frequency bins [2].
\nEncoder
\nThe encoder processes the Mel spectrogram through:
\n![\"Whisper](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-0.webp\")
Decoder
\nThe decoder follows the standard Transformer decoder architecture with learned positional embeddings and tied input-output token representations (same weight matrix for input embeddings and output projection). It uses byte-pair encoding tokenization similar to GPT-2.
\nModel Sizes
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Model | Parameters | Layers | Width | Heads |
|---|---|---|---|---|
| tiny | 39M | 4 | 384 | 6 |
| base | 74M | 6 | 512 | 8 |
| small | 244M | 12 | 768 | 12 |
| medium | 769M | 24 | 1024 | 16 |
| large-v3 | 1.55B | 32 | 1280 | 20 |
Whisper’s encoder-decoder structure makes it naturally suited for batch processing but challenging for streaming applications. The encoder requires the full 30-second audio context before producing useful representations [3].
\nThe Conformer (Convolution-augmented Transformer), introduced by Google in 2020, addresses a fundamental limitation of pure Transformers: while self-attention captures global context well, it struggles with local feature patterns that are important for speech [4].
\nKey Insight
\nSpeech signals contain both local patterns (phonemes, formants) and global dependencies (grammar, semantics). CNNs excel at local feature extraction while Transformers handle global context. Conformer combines both.
\nBlock Structure
\nThe Conformer uses a “macaron” structure where two feed-forward layers sandwich the attention and convolution modules:
\n![\"Conformer](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-1.webp\")
Convolution Module Details
\nThe convolution module uses depthwise separable convolutions for efficiency:
\nThe depthwise convolution has kernel size 31 by default, meaning each output position attends to 15 frames on each side (roughly 150ms of audio context at standard 10ms frame rates).
\nPerformance
\nOn LibriSpeech, Conformer achieves 2.1%/4.3% WER without a language model and 1.9%/3.9% with an external language model on test-clean/test-other [4]. This made it the dominant architecture for production ASR systems through 2024.
\nASR systems use two main decoding paradigms with different tradeoffs [5].
\nConnectionist Temporal Classification (CTC)
\nCTC, introduced by Graves et al. in 2006, addresses the alignment problem in sequence-to-sequence tasks where input and output sequences have different lengths.
\nKey properties:
\n![\"CTC](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-2.webp\")
CTC loss marginalizes over all possible alignments between input and output:
\nP(Y|X) = Σ P(A|X) for all valid alignments AModels like Wav2Vec2, HuBERT, and M-CTC-T use CTC [5]. The main advantage is non-autoregressive decoding: all output tokens can be computed in parallel, enabling faster inference.
\nAttention-Based Encoder-Decoder (AED)
\nAED models (like Whisper) use cross-attention to learn soft alignments between encoder outputs and decoder states:
\nThe downside is autoregressive decoding: tokens must be generated sequentially, increasing latency.
\nHybrid CTC/Attention
\nMany modern systems combine both approaches. During training, a CTC loss is applied to the encoder output as a regularizer, encouraging monotonic alignment. During inference, CTC scores can be used to constrain beam search [5].
\nThe RNN-Transducer (RNN-T), used by Google and other production systems, extends CTC with a prediction network that models output dependencies without full autoregressive decoding.
\nReal-time applications like voice assistants require streaming ASR that transcribes speech with minimal latency. This is challenging because Transformer models rely on full-sequence attention [6].
\nThe Problem
\nStandard self-attention has O(n^2) complexity and requires the entire sequence:
\nAttention(Q, K, V) = softmax(QK^T / √d) VFor a 30-second audio clip at 50 frames/second, this means 1500 frames must be available before processing begins.
\nChunked Attention
\nThe primary solution is chunked (or blockwise) attention:
\n![\"Chunked](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-3.webp\")
Tradeoffs
\nResearch shows that chunked attention with 32-48 frames of left context and 16-32 frame chunks achieves a reasonable balance. The SSCFormer architecture uses sequentially sampled chunks with causal convolutions to improve accuracy within the streaming constraint [6].
\nPositional Encoding for Streaming
\nWith chunked attention, relative positional encodings work better than absolute ones. The model only needs to represent distances up to the maximum context window, not positions within an indefinitely long stream.
\nText-to-speech (TTS) converts text into natural-sounding audio. Modern TTS has evolved from concatenative synthesis (splicing recorded audio) through parametric synthesis to end-to-end neural approaches.
\nVITS (Variational Inference with adversarial learning for end-to-end Text-to-Speech) unifies the acoustic model and vocoder into a single end-to-end framework using variational inference and adversarial training [7].
\nKey Innovation
\nTraditional TTS pipelines generate mel spectrograms from text, then convert spectrograms to waveforms with a separate vocoder. This two-stage approach can cause mismatch artifacts. VITS generates waveforms directly from text.
\nArchitecture Components
\n![\"VITS](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-4.webp\")
Variational Inference Framework
\nVITS models TTS as a conditional VAE:
\nThe training objective combines:
\nStochastic Duration Predictor
\nUnlike deterministic duration predictors, VITS uses a stochastic duration predictor that models duration as a distribution. This enables generating the same text with different speaking rates and rhythms, capturing the natural variability in human speech.
\nVITS2 Improvements
\nVITS2 enhances the original with:
\nThe Tacotron models pioneered end-to-end TTS using sequence-to-sequence learning [8].
\nTacotron 1 (2017)
\nTacotron 2 (2017)
\nKey improvements over Tacotron 1:
\n![\"Tacotron](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-5.webp\")
Tacotron 2 achieved MOS of 4.53, approaching the 4.58 MOS of professionally recorded speech [8].
\nFastSpeech (2019) and FastSpeech 2 (2020)
\nFastSpeech addressed Tacotron’s slow autoregressive inference:
\nFastSpeech 2 added pitch and energy predictors for more controllable synthesis. It achieves RTF of ~0.02 on V100 (50x faster than real-time).
\nVocoders convert mel spectrograms (or other intermediate representations) into audio waveforms. This is an inverse problem: spectrograms discard phase information, which the vocoder must reconstruct.
\nHiFi-GAN
\nHiFi-GAN, published in 2020, uses GANs for efficient high-fidelity synthesis [9].
\nArchitecture:
\nThe key insight is that speech contains multiple periodic components (fundamental frequency and harmonics). By having discriminators focus on different periodicities, the model learns to generate all these components correctly.
\n![\"HiFi-GAN](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-6.webp\")
HiFi-GAN V1 (14M params) generates audio 13.4x faster than real-time on CPU.
\nBigVGAN
\nBigVGAN, from NVIDIA in 2022, scales up HiFi-GAN with architectural improvements [10]:
\nSnake activation: Periodic activation function x + sin^2(x)/a with learned frequency. Provides inductive bias for generating periodic waveforms.
\nAnti-aliased representation: Low-pass filtering before downsampling in discriminator to prevent aliasing artifacts.
\nLarger scale: Up to 112M parameters (vs 14M for HiFi-GAN V1)
\nBigVGAN trained only on clean speech (LibriTTS) generalizes to unseen speakers, languages, singing, and even instrumental music without fine-tuning.
\nZero-shot TTS generates speech in any voice given only a few seconds of reference audio.
\nVALL-E
\nVALL-E, from Microsoft in 2023, treats TTS as a language modeling problem [11]:
\n![\"VALL-E](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-7.webp\")
VALL-E 2 achieved human parity on LibriSpeech and VCTK using repetition-aware sampling and grouped code modeling [11].
\nXTTS
\nXTTS, from Coqui, builds on Tortoise with improvements for multilingual zero-shot TTS [12]:
\nXTTS v2 achieves RTF of 0.48 with 200ms time-to-first-chunk for streaming applications [12].
\nF5-TTS
\nF5-TTS uses a non-autoregressive design with flow matching:
\nVoice cloning extracts a speaker’s characteristics from reference audio and applies them to synthesize new speech [13].
\nSpeaker Encoder
\nA neural network extracts a fixed-dimension speaker embedding from reference audio:
\n![\"Speaker](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-8.webp\")
Embedding-Based Adaptation
\nThe speaker embedding conditions the TTS model:
\nMore advanced approaches use attention-based conditioning (like XTTS’s Perceiver) to capture finer-grained speaker characteristics.
\nQuality vs Data
\nVoice conversion transforms speech from one speaker to sound like another while preserving linguistic content.
\nModern voice conversion uses self-supervised models like HuBERT to extract speaker-independent content representations [14].
\nHuBERT for Content
\nHuBERT (Hidden-Unit BERT) is trained via masked prediction on audio:
\nThe resulting representations capture phonetic content while being somewhat speaker-invariant. RVC uses layer 12 of HuBERT as content features [14].
\nECAPA-TDNN for Speaker
\nECAPA-TDNN extracts speaker embeddings:
\nThe core challenge in voice conversion is separating “what is said” from “who said it” [15].
\nInformation Bottleneck
\nOne approach uses information bottlenecks to force separation:
\n![\"Voice](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-9.webp\")
Adversarial Disentanglement
\nTrain with adversarial losses to ensure:
\nCONTENTVEC Approach
\nCONTENTVEC converts all training audio to a single speaker using an unsupervised VC system, then trains HuBERT on this speaker-normalized data. The resulting representations contain minimal speaker information [15].
\nRetrieval-based Voice Conversion (RVC) is an open-source system achieving high-quality conversion with minimal data [14].
\nPipeline
\n![\"RVC](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-10.webp\")
Retrieval Module
\nRVC’s key innovation is the retrieval step:
\nThis reduces “timbre leakage” by replacing source speaker characteristics with training set features.
\nPerformance
\nRVC achieves 90ms end-to-end latency with ASIO audio interfaces and learns high-quality transformations from about 10 minutes of target speaker audio [14].
\nSo-VITS-SVC (SoftVC VITS Singing Voice Conversion) specializes in singing voice conversion [16].
\nDifferences from Speech VC
\nSinging voice conversion has additional challenges:
\nArchitecture
\nSo-VITS-SVC uses:
\nShallow Diffusion Enhancement
\nRecent versions add optional diffusion refinement:
\nClustering for Timbre Matching
\nSimilar to RVC’s retrieval, So-VITS-SVC uses feature clustering:
\nAudio language models extend the language modeling paradigm to generate audio directly, enabling unified speech-text systems.
\nAudioLM, from Google in 2022, pioneered treating audio generation as language modeling [17].
\nHybrid Tokenization
\nAudioLM uses two types of tokens to capture different aspects of audio:
\n![\"AudioLM](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-11.webp\")
Three-Stage Generation
\nAudioLM generates hierarchically:
\nThis cascade allows the model to first get the high-level content right, then progressively add acoustic detail.
\nCapabilities
\nWithout any text supervision, AudioLM generates:
\nSpeechGPT extends LLMs to natively understand and generate speech [18].
\nArchitecture
\n![\"SpeechGPT](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-12.webp\")
Training Stages
\nThe key insight is that by representing speech as tokens within the LLM’s vocabulary, knowledge transfers between modalities. The model can answer questions about speech content, translate speech, or generate speech responses.
\nMoshi, from Kyutai (French AI lab), is the first real-time full-duplex spoken dialogue system [19].
\nKey Innovation: Parallel Audio Streams
\nMoshi models two simultaneous audio streams:
\nThis removes turn-taking constraints. The model always listens and always generates (speech or silence), enabling natural interruptions and backchannels (“uh-huh”, “right”).
\n![\"Full-Duplex](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-13.webp\")
Architecture
\n![\"Moshi](\"https://blog.ecitis.org/feeds/figures/voice-audio-models-14.webp\")
Mimi Codec
\nMoshi uses a custom neural codec called Mimi:
\nInner Monologue
\nMoshi generates time-aligned text tokens as a “prefix” to audio tokens:
\nInternal: [text: \"Hello\"] [audio: \"Hello\"] [text: \"how\"] [audio: \"how\"]...This provides:
\nPerformance
\nMixture of Experts (MoE) enables scaling model capacity without proportionally increasing compute. Recent work applies MoE to audio [20].
\nMoME (Mixture of Matryoshka Experts)
\nFor audio-visual speech recognition:
\nMoHAVE (Mixture of Hierarchical Audio-Visual Experts)
\nUses hierarchical gating:
\nPractical Considerations
\nMoE for audio faces challenges:
\nTraining voice models requires careful data preparation and domain-specific techniques.
\nMel Spectrograms
\nThe standard intermediate representation for speech models [21]:
\nimport librosa\n\n# Standard preprocessing\naudio, sr = librosa.load(path, sr=16000)\nmel = librosa.feature.melspectrogram(\n y=audio,\n sr=sr,\n n_fft=1024,\n hop_length=256,\n n_mels=80\n)\nlog_mel = np.log(mel + 1e-5)MFCC
\nMel-Frequency Cepstral Coefficients add DCT to mel spectrograms:
\nMFCCs decorrelate features and compress representation. They’re more common in traditional ASR but less used in end-to-end neural models which learn their own representations [21].
\nRaw Waveform
\nSome models (Wav2Vec2, HuBERT) operate directly on raw waveforms:
\nASR Data
\nTTS Data
\nFor voice cloning:
\nForced alignment aligns transcripts to audio at the word or phone level [22].
\nMontreal Forced Aligner (MFA)
\nStandard tool for TTS data preparation:
\n# Example MFA usage\nmfa align /path/to/audio /path/to/dictionary /path/to/model /path/to/outputMFA uses Kaldi internally with:
\nCTC Segmentation
\nAlternative using neural ASR models:
\nPractical Tips
\nTTS Adaptation
\nFor adapting TTS to new speakers with limited data [23]:
\nSpeaker embedding only: Freeze model, train only speaker embedding
\nFull fine-tuning with mixing: Mix original speaker data with new speaker
\nLoRA/Adapter tuning: Add small trainable modules to frozen model
\nZero-Shot Models
\nYourTTS and XTTS can adapt to new voices without fine-tuning:
\nASR Fine-Tuning
\nFor domain-specific ASR [24]:
\nfrom transformers import WhisperForConditionalGeneration, WhisperProcessor\nfrom peft import LoraConfig, get_peft_model\n\nmodel = WhisperForConditionalGeneration.from_pretrained(\"openai/whisper-small\")\nprocessor = WhisperProcessor.from_pretrained(\"openai/whisper-small\")\n\n# LoRA config for efficient fine-tuning\nlora_config = LoraConfig(\n r=16,\n lora_alpha=32,\n target_modules=[\"q_proj\", \"v_proj\"],\n lora_dropout=0.05,\n)\nmodel = get_peft_model(model, lora_config)\n\n# Results in ~99% fewer trainable parametersFine-tuning on ~400 samples can achieve 31+ WER point improvement for domain-specific vocabulary [24].
\nDeploying audio models requires attention to latency, throughput, and resource constraints.
\nReal-Time Factor (RTF)
\nRTF = processing_time / audio_duration [25]
\nLatency Components
\nFor streaming ASR:
\nFor TTS:
\nBenchmarks
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Model | Task | RTF (GPU) | Latency |
|---|---|---|---|
| Whisper large-v3 | ASR | ~0.3 | Batch, not streaming |
| Conformer-CTC | Streaming ASR | ~0.1-0.2 | 200-400ms |
| FastSpeech 2 | TTS | 0.02 | 20ms per second of audio |
| VITS | TTS | 0.067 | 67ms per second of audio |
| XTTS v2 | Zero-shot TTS | 0.48 | 200ms first chunk |
| HiFi-GAN | Vocoder | 0.02 | ~20ms |
Chunk-Based Processing
\n# Pseudocode for streaming ASR\nchunk_size = 640 # ms\nleft_context = 480 # ms\nbuffer = []\n\nwhile audio_stream.has_data():\n chunk = audio_stream.read(chunk_size)\n buffer.append(chunk)\n\n # Keep only necessary context\n context = buffer[-left_context_chunks:]\n\n # Process with context\n features = extract_features(context + [chunk])\n text = model.decode(features)\n\n yield textEndpointer
\nDetect when user stops speaking to finalize transcription:
\nVocoders are often the bottleneck in TTS pipelines.
\nStrategies
\nMulti-Band Generation
\nSplit frequency range into bands, generate each with smaller model:
\nPost-Training Quantization (PTQ)
\nApply quantization after training [26]:
\n# INT8 quantization for faster inference\nimport torch\n\nmodel_fp32 = load_model()\nmodel_int8 = torch.quantization.quantize_dynamic(\n model_fp32,\n {torch.nn.Linear, torch.nn.Conv1d},\n dtype=torch.qint8\n)Quantization-Aware Training (QAT)
\nTrain with simulated quantization for better accuracy:
\nResults
\nFramework Support
\nInstallation
\npip install openai-whisper\n# Or with faster-whisper (CTranslate2 backend)\npip install faster-whisperBasic Transcription
\nimport whisper\n\nmodel = whisper.load_model(\"base\") # tiny, base, small, medium, large-v3\nresult = model.transcribe(\"audio.mp3\")\nprint(result[\"text\"])\n\n# With options\nresult = model.transcribe(\n \"audio.mp3\",\n language=\"en\",\n task=\"transcribe\", # or \"translate\" for X->English\n fp16=True, # Use FP16 on GPU\n condition_on_previous_text=True, # Use context\n)Faster-Whisper for Production
\nfrom faster_whisper import WhisperModel\n\n# INT8 quantization for faster CPU inference\nmodel = WhisperModel(\"large-v3\", device=\"cpu\", compute_type=\"int8\")\n\n# Or FP16 on GPU\nmodel = WhisperModel(\"large-v3\", device=\"cuda\", compute_type=\"float16\")\n\nsegments, info = model.transcribe(\"audio.mp3\", beam_size=5)\n\nfor segment in segments:\n print(f\"[{segment.start:.2f}s -> {segment.end:.2f}s] {segment.text}\")Streaming with Whisper
\nWhisper isn’t designed for streaming, but you can approximate it:
\nimport numpy as np\nfrom faster_whisper import WhisperModel\n\nmodel = WhisperModel(\"base\", device=\"cuda\")\n\ndef process_chunk(audio_chunk, previous_text=\"\"):\n # Pad to 30 seconds if needed\n if len(audio_chunk) < 30 * 16000:\n audio_chunk = np.pad(audio_chunk, (0, 30 * 16000 - len(audio_chunk)))\n\n segments, _ = model.transcribe(\n audio_chunk,\n initial_prompt=previous_text, # Context from previous chunks\n vad_filter=True, # Filter silence\n )\n return \" \".join([s.text for s in segments])Fine-tuning Coqui TTS
\n# Install\n# pip install TTS\n\nfrom TTS.api import TTS\n\n# Load pre-trained VITS model\ntts = TTS(\"tts_models/en/ljspeech/vits\")\n\n# For fine-tuning, use the training script\n# 1. Prepare data in LJSpeech format:\n# wavs/\n# audio1.wav\n# audio2.wav\n# metadata.csv: audio1|transcript one|transcript one\n# audio2|transcript two|transcript two\n\n# 2. Create config\nfrom TTS.tts.configs.vits_config import VitsConfig\nfrom TTS.tts.models.vits import Vits\n\nconfig = VitsConfig(\n audio={\"sample_rate\": 22050},\n run_name=\"my_voice\",\n batch_size=16,\n eval_batch_size=8,\n num_loader_workers=4,\n num_eval_loader_workers=4,\n run_eval=True,\n test_delay_epochs=-1,\n epochs=1000,\n text_cleaner=\"english_cleaners\",\n use_phonemes=True,\n phoneme_language=\"en-us\",\n output_path=\"output/\",\n datasets=[{\n \"name\": \"ljspeech\",\n \"path\": \"/path/to/your/data/\",\n \"meta_file_train\": \"metadata.csv\"\n }],\n)\n\n# 3. Start from pretrained checkpoint\nconfig.load_json(\"/path/to/pretrained/config.json\")\nmodel = Vits.init_from_config(config)\nmodel.load_checkpoint(config, \"/path/to/pretrained/best_model.pth\")\n\n# 4. Fine-tune\nfrom TTS.trainer import Trainer\ntrainer = Trainer(\n TrainerArgs(),\n config,\n output_path=\"output/\",\n model=model,\n)\ntrainer.fit()Fine-tuning with XTTS
\nfrom TTS.api import TTS\n\n# XTTS supports zero-shot cloning without fine-tuning\ntts = TTS(\"tts_models/multilingual/multi-dataset/xtts_v2\")\n\n# Generate with voice cloning\ntts.tts_to_file(\n text=\"Hello, this is my cloned voice!\",\n speaker_wav=\"reference_audio.wav\", # 3-10 seconds\n language=\"en\",\n file_path=\"output.wav\"\n)\n\n# For fine-tuning (better quality with more data)\n# Use the XTTS fine-tuning script with your datasetUsing RVC
\n# Clone RVC\ngit clone https://github.com/RVC-Project/Retrieval-based-Voice-Conversion-WebUI\ncd Retrieval-based-Voice-Conversion-WebUI\npip install -r requirements.txt\n\n# Download pretrained models\n# https://huggingface.co/lj1995/VoiceConversionWebUI\n\n# Launch WebUI\npython infer-web.pyProgrammatic Voice Conversion
\n# Simplified RVC inference (actual implementation more complex)\nimport torch\nfrom fairseq import checkpoint_utils\n\n# Load HuBERT for content extraction\nhubert_model, cfg, task = checkpoint_utils.load_model_ensemble_and_task(\n [\"hubert_base.pt\"]\n)\nhubert = hubert_model[0].eval()\n\n# Load RVC model\nrvc_model = torch.load(\"target_voice.pth\")\n\ndef convert_voice(source_audio):\n # 1. Extract content features\n with torch.no_grad():\n content = hubert.extract_features(source_audio)[0]\n\n # 2. Extract pitch\n f0 = extract_f0(source_audio) # RMVPE or CREPE\n\n # 3. Retrieve similar features from training set (optional)\n retrieved = faiss_index.search(content, k=3)\n content = blend(content, retrieved)\n\n # 4. Generate with RVC model\n audio = rvc_model(content, f0)\n\n return audioSo-VITS-SVC for Singing
\n# Clone So-VITS-SVC\ngit clone https://github.com/svc-develop-team/so-vits-svc\ncd so-vits-svc\npip install -r requirements.txt\n\n# Prepare training data\n# Place wav files in dataset_raw/speaker_name/\n\n# Preprocess\npython resample.py\npython preprocess_flist_config.py\npython preprocess_hubert_f0.py\n\n# Train\npython train.py -c configs/config.json -m speaker_name\n\n# Inference\npython inference_main.py -m \"logs/speaker_name/model.pth\" \\\n -c \"configs/config.json\" \\\n -n \"song.wav\" \\\n -t 0 # pitch shift in semitonesRadford, A., et al. (2022). “Robust Speech Recognition via Large-Scale Weak Supervision.” OpenAI. https://github.com/openai/whisper
\nOpenAI. (2023). “Whisper large-v3.” Hugging Face. https://huggingface.co/openai/whisper-large-v3
\nZhou, et al. (2025). “Adapting Whisper for Streaming Speech Recognition via Two-Pass Decoding.” Interspeech 2025. https://www.isca-archive.org/interspeech_2025/zhou25_interspeech.pdf
\nGulati, A., et al. (2020). “Conformer: Convolution-augmented Transformer for Speech Recognition.” Interspeech 2020. https://arxiv.org/abs/2005.08100
\nHugging Face. “CTC Architectures.” Audio Course. https://huggingface.co/learn/audio-course/chapter3/ctc
\nSpeechBrain Documentation. “Streaming Speech Recognition with Conformers.” https://speechbrain.readthedocs.io/en/v1.0.2/tutorials/nn/conformer-streaming-asr.html
\nKim, J., et al. (2021). “Conditional Variational Autoencoder with Adversarial Learning for End-to-End Text-to-Speech.” ICML 2021. https://arxiv.org/abs/2106.06103
\nShen, J., et al. (2017). “Natural TTS Synthesis by Conditioning WaveNet on Mel Spectrogram Predictions.” https://arxiv.org/abs/1712.05884
\nKong, J., et al. (2020). “HiFi-GAN: Generative Adversarial Networks for Efficient and High Fidelity Speech Synthesis.” NeurIPS 2020. https://github.com/jik876/hifi-gan
\nLee, S.-G., et al. (2022). “BigVGAN: A Universal Neural Vocoder with Large-Scale Training.” ICLR 2023. https://arxiv.org/abs/2206.04658
\nMicrosoft Research. “VALL-E.” https://www.microsoft.com/en-us/research/project/vall-e-x/
\nCasanova, E., et al. (2024). “XTTS: a Massively Multilingual Zero-Shot Text-to-Speech Model.” https://arxiv.org/html/2406.04904v1
\nVoice Cloning Survey. (2025). https://arxiv.org/html/2505.00579v1
\nRVC Project. “Retrieval-based Voice Conversion WebUI.” https://github.com/RVC-Project/Retrieval-based-Voice-Conversion-WebUI
\nQian, K., et al. (2022). “CONTENTVEC: An Improved Self-Supervised Speech Representation.” ICML 2022. https://proceedings.mlr.press/v162/qian22b/qian22b.pdf
\nSo-VITS-SVC. “SoftVC VITS Singing Voice Conversion.” https://github.com/svc-develop-team/so-vits-svc
\nBorsos, Z., et al. (2022). “AudioLM: a Language Modeling Approach to Audio Generation.” https://arxiv.org/abs/2209.03143
\nZhang, D., et al. (2023). “SpeechGPT: Empowering Large Language Models with Intrinsic Cross-Modal Conversational Abilities.” https://www.alphaxiv.org/overview/2305.11000v2
\nDéfossez, A., et al. (2024). “Moshi: a speech-text foundation model for real-time dialogue.” Kyutai. https://kyutai.org/Moshi.pdf
\nWu, et al. (2025). “MoME: Mixture of Matryoshka Experts for Audio-Visual Speech Recognition.” NeurIPS 2025. https://arxiv.org/abs/2510.04136
\nKetanhdoshi. “Audio Deep Learning Made Simple: Data Preparation and Augmentation.” https://ketanhdoshi.github.io/Audio-Augment/
\nMcAuliffe, M., et al. (2017). “Montreal Forced Aligner: Trainable Text-Speech Alignment Using Kaldi.” https://montreal-forced-aligner.readthedocs.io/
\nArik, S.O., et al. (2018). “Neural Voice Cloning with a Few Samples.” NeurIPS 2018.
\nHugging Face. “Fine-Tune Whisper For Multilingual ASR.” https://huggingface.co/blog/fine-tune-whisper
\nOpen Voice Technology Wiki. “Real-time-factor.” https://openvoice-tech.net/index.php/Real-time-factor
\n“Model Quantization Techniques for ASR/TTS.” https://apxml.com/courses/speech-recognition-synthesis-asr-tts/chapter-6-optimization-deployment-toolkits/quantization-speech-models
\nHugging Face is an American company founded in 2016 by Clement Delangue and Julien Chaumond, originally as a chatbot startup. It has since evolved into the central hub for open-source machine learning. The platform hosts over 2.4 million models and 730,000 datasets as of January 2026, serving more than 18 million monthly visitors.
\nThe company builds on a core open-source stack: Transformers, Datasets, Diffusers, PEFT, Accelerate, TRL, Timm, and Optimum. Beyond libraries, Hugging Face provides production tools like Inference Endpoints, Text Generation Inference (TGI), and Text Embeddings Inference (TEI). Over 2,000 organizations use their Enterprise Hub for private deployments with SSO, regional data storage, and audit logs.
\nHugging Face integrates with major cloud providers. AWS offers Deep Learning Containers and SageMaker integration. Azure Machine Learning and Google Vertex AI both support direct model deployment. In April 2025, the company acquired Pollen Robotics, a humanoid robotics startup, signaling expansion beyond pure software.
\nThe Hub is where you discover, evaluate, and download models. Each model repository contains the weights, configuration files, and documentation needed to run inference or continue training.
\nFilter by task (text generation, image classification, audio transcription), library (Transformers, Diffusers, GGUF), license, and language. The search indexes model names, tags, and README content. Sorting by downloads or likes surfaces popular choices; sorting by recent shows the latest uploads.
\nEvery model should have a model card in the README.md file. Cards follow a structured template covering:
\nThe metadata block at the top enables Hub features. Specify license for filtering, datasets to link training data, and metrics with eval_results to display benchmark performance in the UI. The Hub parses this YAML and renders widgets showing accuracy, F1, perplexity, or custom metrics.
Common licenses on the Hub include Apache 2.0, MIT, and various model-specific licenses like Llama’s community license or Gemma’s terms of use. The license field in metadata enables filtering. For custom licenses, use license: other with license_name and license_link fields, or include a LICENSE file in the repository.
The Evaluate library provides dozens of metrics with a consistent API:
\nimport evaluate\n\naccuracy = evaluate.load(\"accuracy\")\nresults = accuracy.compute(predictions=[0, 1, 1], references=[0, 1, 0])\nprint(results) # {'accuracy': 0.666...}\n\n# Load multiple metrics\nclf_metrics = evaluate.combine([\"accuracy\", \"f1\", \"precision\", \"recall\"])\nresults = clf_metrics.compute(predictions=[0, 1, 1, 0], references=[0, 1, 0, 1])Each metric includes a card documenting its formula, value ranges, and appropriate use cases.
\nModels come in various formats optimized for different runtimes and hardware. Understanding when to use each saves time and compute.
\n![\"Model](\"https://blog.ecitis.org/feeds/figures/huggingface-ecosystem-guide-0.webp\")
The .bin format uses Python’s pickle for serialization. Pickle can execute arbitrary code during deserialization, creating security risks when loading untrusted models.
Safetensors solves this. Developed by Hugging Face, it stores tensors in a binary format without code execution. Loading is 76x faster on CPU and 2x faster on GPU compared to pickle. The BLOOM model loads on 8 GPUs in 45 seconds with safetensors versus 10 minutes with pickle weights.
\nSafetensors also supports lazy loading through its safe_open() context manager. Tensors load on-demand rather than all at once, critical for distributed inference where each GPU only needs a shard.
from safetensors import safe_open\n\n# Lazy loading - tensors loaded only when accessed\nwith safe_open(\"model.safetensors\", framework=\"pt\") as f:\n tensor_a = f.get_tensor(\"layer.0.weight\")Transformers defaults to safetensors when available. Legacy .bin files work but carry security and performance penalties.
GGUF (Georgi Gerganov Universal Format) packages everything needed to run a model: architecture details, tokenizer, quantization parameters, and weights in a single file. It evolved from the earlier GGML format for better extensibility.
\nThe format targets llama.cpp and tools built on it like Ollama, LM Studio, and koboldcpp. GGUF excels at CPU inference and mixed CPU/GPU offloading on consumer hardware.
\nQuantization options range from 8-bit down to 1.5-bit:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Type | Description | Size Reduction |
|---|---|---|
| Q8_0 | 8-bit, block size 32 | ~2x |
| Q6_K | 6-bit K-Quant | ~2.5x |
| Q5_K_M | 5-bit K-Quant medium | ~2.8x |
| Q4_K_M | 4-bit K-Quant medium | ~3.3x |
| Q4_0 | 4-bit basic | ~4x |
| Q2_K | 2-bit K-Quant | ~6x |
Q4_K_M hits the sweet spot for most users. A 13.5GB FP16 model shrinks to 4GB while maintaining acceptable quality. K-Quant variants use different bit allocations per layer based on importance, preserving quality better than uniform quantization.
\nConvert HuggingFace models to GGUF:
\n# Clone llama.cpp\ngit clone https://github.com/ggml-org/llama.cpp\ncd llama.cpp\n\n# Convert to GGUF (F16 baseline)\npython convert_hf_to_gguf.py /path/to/hf-model --outfile model-f16.gguf\n\n# Quantize to Q4_K_M\n./llama-quantize model-f16.gguf model-q4_k_m.gguf Q4_K_MFor better quantization quality, compute an importance matrix from a calibration dataset:
\n# Generate importance matrix\n./llama-imatrix -m model-f16.gguf -f calibration.txt -o imatrix.dat\n\n# Quantize with importance matrix\n./llama-quantize --imatrix imatrix.dat model-f16.gguf model-q4_k_m.gguf Q4_K_MONNX (Open Neural Network Exchange) defines a standard graph format for neural networks. Train in PyTorch or TensorFlow, export to ONNX, run anywhere.
\nONNX Runtime powers inference across platforms: NVIDIA GPUs via TensorRT, Intel CPUs via OpenVINO, AMD GPUs via ROCm, Apple Silicon via CoreML, and Windows via DirectML. This portability makes ONNX valuable for production deployment across heterogeneous hardware.
\nExport a Transformers model to ONNX:
\nfrom optimum.onnxruntime import ORTModelForSequenceClassification\nfrom transformers import AutoTokenizer\n\nmodel_id = \"distilbert-base-uncased-finetuned-sst-2-english\"\nsave_dir = \"onnx_model\"\n\n# Export and save\nmodel = ORTModelForSequenceClassification.from_pretrained(model_id, export=True)\ntokenizer = AutoTokenizer.from_pretrained(model_id)\n\nmodel.save_pretrained(save_dir)\ntokenizer.save_pretrained(save_dir)\n\n# Load and run inference\nmodel = ORTModelForSequenceClassification.from_pretrained(save_dir)\ninputs = tokenizer(\"This movie was great!\", return_tensors=\"pt\")\noutputs = model(**inputs)The ONNX Model Zoo on Hugging Face hosts pre-exported models at huggingface.co/onnxmodelzoo.
\nThese methods reduce model precision for faster inference and lower memory usage, each with different tradeoffs.
\nGPTQ uses post-training quantization with Hessian-based optimization to minimize output error. It requires a calibration dataset and pre-quantizes weights. Best for GPU inference when you need raw throughput.
\nAWQ (Activation-aware Weight Quantization) identifies and protects important weights by observing activations. Like GPTQ, it requires calibration and pre-quantization. AWQ often preserves quality better than GPTQ, especially for instruction-tuned models.
\nbitsandbytes quantizes on-the-fly during model loading. No calibration dataset or pre-quantized checkpoint needed. Its NF4 (NormalFloat4) format assumes weights follow a Gaussian distribution and places more quantization levels near zero where weights cluster. Best for fine-tuning with QLoRA and quick experimentation.
\nfrom transformers import AutoModelForCausalLM, BitsAndBytesConfig\n\n# Load with 4-bit quantization\nbnb_config = BitsAndBytesConfig(\n load_in_4bit=True,\n bnb_4bit_quant_type=\"nf4\",\n bnb_4bit_compute_dtype=\"bfloat16\",\n)\n\nmodel = AutoModelForCausalLM.from_pretrained(\n \"meta-llama/Llama-3.1-8B\",\n quantization_config=bnb_config,\n device_map=\"auto\",\n)Quality comparison from 2025 benchmarks: bitsandbytes has the smallest quality drop, AWQ comes second, GPTQ and Marlin (GPTQ’s optimized kernel) are close behind. The practical difference matters most for your specific use case; test on your evaluation set.
\nTensorRT-LLM is NVIDIA’s library for optimizing LLM inference on their GPUs. It applies custom attention kernels, inflight batching, paged KV caching, and hardware-specific optimizations.
\nThe library supports quantization formats tied to GPU generations:
\nRecent benchmarks show DeepSeek-R1 running 3x faster with speculative decoding on TensorRT-LLM. Pre-quantized NVFP4 models for Llama 3.3 70B and DeepSeek-R1 are available on the Hub.
\nTensorRT-LLM requires building an engine specific to your GPU and model. This compilation step takes time but produces optimized inference:
\nfrom tensorrt_llm import LLM, SamplingParams\n\nllm = LLM(model=\"meta-llama/Llama-3.1-8B-Instruct\")\n\nprompts = [\"Explain quantum computing in simple terms\"]\nsampling_params = SamplingParams(temperature=0.7, max_tokens=256)\n\noutputs = llm.generate(prompts, sampling_params)| Use Case | Format |
|---|---|
| Local CPU/GPU inference, consumer hardware | GGUF |
| Production GPU serving, max throughput | TensorRT-LLM |
| Cross-platform deployment | ONNX |
| Fine-tuning with limited VRAM | bitsandbytes |
| Pre-quantized GPU inference | AWQ or GPTQ |
| Standard Transformers usage | safetensors |
The Hub hosts over 730,000 datasets with tools for exploration, streaming, and efficient loading.
\nLoad datasets with a single function call:
\nfrom datasets import load_dataset\n\n# Load from the Hub\ndataset = load_dataset(\"imdb\")\n\n# Access splits\ntrain = dataset[\"train\"]\ntest = dataset[\"test\"]\n\n# Iterate\nfor example in train:\n print(example[\"text\"], example[\"label\"])\n breakThe library handles downloading, caching, and format conversion automatically.
\nDatasets uses Apache Arrow for storage. Arrow’s columnar layout enables zero-copy reads and memory-mapped access. A dataset backed by an on-disk Arrow cache can exceed available RAM; the OS pages data in and out as needed.
\nThis architecture lets you work with terabyte-scale datasets on machines with limited memory:
\n# Large dataset - only loads what you access\ndataset = load_dataset(\"HuggingFaceFW/fineweb\", \"sample-10BT\")\n\n# Process without loading everything into memory\ndef tokenize(examples):\n return tokenizer(examples[\"text\"], truncation=True)\n\ntokenized = dataset.map(tokenize, batched=True, num_proc=4)The English split of FineWeb is 45 terabytes. Streaming lets you use it without downloading:
\nfrom datasets import load_dataset\n\n# Stream - no disk space needed\ndataset = load_dataset(\n \"HuggingFaceFW/fineweb\",\n name=\"sample-10BT\",\n split=\"train\",\n streaming=True\n)\n\n# Iterate over examples\nfor example in dataset.take(10):\n print(example[\"text\"][:100])Streaming datasets support map, filter, shuffle, and take. Data downloads on demand as you iterate.
Datasets on the Hub automatically convert to Parquet, a columnar format that enables efficient partial reads. The Dataset Viewer uses this to display data in your browser without downloading entire files.
\nParquet stores column statistics and page indexes enabling:
\n# Read specific columns from Parquet\nimport pyarrow.parquet as pq\n\n# Only download 'text' column\ntable = pq.read_table(\n \"hf://datasets/username/dataset/data.parquet\",\n columns=[\"text\"]\n)Transformers is the core library for working with pretrained models. It provides a unified API across architectures: BERT, GPT, T5, LLaMA, Mistral, Qwen, Gemma, and hundreds more.
\nPipelines abstract away tokenization, model loading, and output processing:
\nfrom transformers import pipeline\n\n# Sentiment analysis\nclassifier = pipeline(\"sentiment-analysis\")\nresult = classifier(\"I love this library!\")\n# [{'label': 'POSITIVE', 'score': 0.9998}]\n\n# Text generation\ngenerator = pipeline(\"text-generation\", model=\"meta-llama/Llama-3.2-1B\")\noutput = generator(\"The future of AI is\", max_length=50)\n\n# Question answering\nqa = pipeline(\"question-answering\")\nresult = qa(question=\"What is the capital?\", context=\"France's capital is Paris.\")\n# {'answer': 'Paris', 'score': 0.99...}Pipelines support GPU acceleration, batch processing, and half-precision:
\n# GPU with fp16\npipe = pipeline(\n \"text-generation\",\n model=\"meta-llama/Llama-3.1-8B-Instruct\",\n device_map=\"auto\",\n torch_dtype=\"auto\",\n)Tokenizers convert text to token IDs the model understands. The library provides both Python (PreTrainedTokenizer) and Rust-backed fast (PreTrainedTokenizerFast) implementations.
Transformers v5 redesigned tokenization. Tokenizers now separate architecture from learned vocabulary, similar to how PyTorch separates network structure from weights:
\nfrom transformers import AutoTokenizer\n\ntokenizer = AutoTokenizer.from_pretrained(\"meta-llama/Llama-3.1-8B\")\n\n# Encode text\ntokens = tokenizer(\"Hello world\", return_tensors=\"pt\")\n# {'input_ids': tensor([[...]]), 'attention_mask': tensor([[...]])}\n\n# Decode back\ntext = tokenizer.decode(tokens[\"input_ids\"][0])Different model families use different tokenization schemes: BPE (GPT, Llama), SentencePiece (T5, Gemma), or WordPiece (BERT). The tokenizer handles this transparently.
\nLoad any model with AutoModel classes:
from transformers import AutoModelForCausalLM, AutoTokenizer\n\nmodel_id = \"meta-llama/Llama-3.1-8B-Instruct\"\n\ntokenizer = AutoTokenizer.from_pretrained(model_id)\nmodel = AutoModelForCausalLM.from_pretrained(\n model_id,\n device_map=\"auto\", # Automatic device placement\n torch_dtype=\"auto\", # Use model's native dtype\n)\n\n# Generate\ninputs = tokenizer(\"Explain transformers:\", return_tensors=\"pt\").to(model.device)\noutputs = model.generate(**inputs, max_new_tokens=100)\nprint(tokenizer.decode(outputs[0]))Control memory usage with quantization and offloading:
\n# 4-bit quantization\nmodel = AutoModelForCausalLM.from_pretrained(\n model_id,\n load_in_4bit=True,\n device_map=\"auto\",\n)\n\n# CPU offloading for models larger than VRAM\nmodel = AutoModelForCausalLM.from_pretrained(\n model_id,\n device_map=\"auto\",\n offload_folder=\"offload\",\n)Understanding how Transformers works under the hood helps debug issues and extend functionality.
\nWhen you call AutoModelForCausalLM.from_pretrained(\"meta-llama/Llama-3.1-8B\"), the library performs several resolution steps:
\"llama\")LlamaForCausalLM)The registry lives in transformers/models/auto/modeling_auto.py. Each Auto class maintains a mapping like:
MODEL_FOR_CAUSAL_LM_MAPPING_NAMES = OrderedDict([\n (\"llama\", \"LlamaForCausalLM\"),\n (\"mistral\", \"MistralForCausalLM\"),\n (\"gpt2\", \"GPT2LMHeadModel\"),\n # ... hundreds more\n])For custom models hosted on the Hub, the config.json can include an auto_map field that points to local Python files:
{\n \"model_type\": \"custom_model\",\n \"auto_map\": {\n \"AutoConfig\": \"configuration_custom.CustomConfig\",\n \"AutoModelForCausalLM\": \"modeling_custom.CustomModelForCausalLM\"\n }\n}This requires trust_remote_code=True when loading, since it executes code from the repository. The Auto Classes documentation covers registration in detail.
Each model architecture follows a consistent file structure:
\ntransformers/models/llama/\n├── __init__.py\n├── configuration_llama.py # LlamaConfig class\n├── modeling_llama.py # LlamaModel, LlamaForCausalLM, etc.\n├── tokenization_llama.py # LlamaTokenizer (slow)\n└── tokenization_llama_fast.py # LlamaTokenizerFast (Rust)The modeling_*.py file contains the actual PyTorch implementation. Models are built from composable pieces:
A typical file structure:
\nclass LlamaAttention(nn.Module):\n \"\"\"Multi-headed attention from 'Attention Is All You Need' paper\"\"\"\n\nclass LlamaMLP(nn.Module):\n \"\"\"Feed-forward network with SiLU activation\"\"\"\n\nclass LlamaDecoderLayer(nn.Module):\n \"\"\"Single transformer block: attention + MLP\"\"\"\n\nclass LlamaModel(LlamaPreTrainedModel):\n \"\"\"The bare Llama Model outputting raw hidden-states\"\"\"\n\nclass LlamaForCausalLM(LlamaPreTrainedModel):\n \"\"\"Llama Model with a language modeling head\"\"\"Every model inherits from PreTrainedModel, which provides core functionality according to the Models documentation:
Loading and saving:
\nfrom_pretrained(): Load weights from Hub or local directorysave_pretrained(): Save model and config to directorypush_to_hub(): Upload to the HubWeight initialization:
\n_init_weights(): Initialize a module’s weights (called recursively)_is_hf_initialized flag prevents re-initializing tied parametersMemory management:
\ngradient_checkpointing_enable(): Trade compute for memoryresize_token_embeddings(): Adjust embedding size for new tokensDevice handling:
\nto(): Move model to devicehalf(), bfloat16(), float(): Change precisionKey class attributes every model defines:
\nclass LlamaPreTrainedModel(PreTrainedModel):\n config_class = LlamaConfig\n base_model_prefix = \"model\"\n supports_gradient_checkpointing = True\n _no_split_modules = [\"LlamaDecoderLayer\"]\n _skip_keys_device_placement = [\"past_key_values\"]The _no_split_modules attribute tells the device placement algorithm which modules must stay on a single device.
The GenerationMixin class adds generate() to models. It supports multiple decoding strategies documented in the Generation strategies guide:
Greedy decoding: Select the highest probability token at each step.
\noutputs = model.generate(inputs, do_sample=False)Beam search: Maintain multiple hypotheses, selecting the sequence with highest total probability.
\noutputs = model.generate(inputs, num_beams=5, early_stopping=True)Sampling with temperature: Sample from the probability distribution, with temperature controlling randomness.
\noutputs = model.generate(inputs, do_sample=True, temperature=0.7)Top-k sampling: Sample from the k most likely tokens.
\noutputs = model.generate(inputs, do_sample=True, top_k=50)Nucleus (top-p) sampling: Sample from the smallest set of tokens whose cumulative probability exceeds p. Described in Holtzman et al.’s “The Curious Case of Neural Text Degeneration.”
\noutputs = model.generate(inputs, do_sample=True, top_p=0.95)The generation loop internally:
\nDuring autoregressive generation, the model computes key and value projections for all previous tokens at each step. Without caching, this means O(n^2) compute for generating n tokens. The KV cache stores these projections for reuse.
\nThe KV cache strategies documentation describes available implementations:
\nDynamicCache (default): Grows as generation progresses. Simple but can cause memory fragmentation.
\noutputs = model.generate(inputs, use_cache=True) # DefaultStaticCache: Pre-allocates fixed-size tensors. Enables torch.compile() but wastes memory on short sequences.
\noutputs = model.generate(inputs, cache_implementation=\"static\")QuantizedCache: Compresses KV values to lower precision, based on the KIVI paper. Quantizes keys per-channel and values per-token.
\nfrom transformers import QuantizedCacheConfig\n\ncache_config = QuantizedCacheConfig(nbits=4)\noutputs = model.generate(inputs, cache_config=cache_config)OffloadedCache: Moves KV cache to CPU, prefetching asynchronously. Enables longer sequences on limited VRAM.
\nThe cache is a tuple of (key_states, value_states) for each layer, stored in the model’s past_key_values attribute during generation.
Attention masks control which tokens can attend to which. Different model types use different masking strategies:
\nPadding mask: Binary mask where 1 = real token, 0 = padding. Prevents attention to padding tokens.
\n# Tokenizer returns attention_mask automatically\ninputs = tokenizer([\"short\", \"much longer sequence\"], padding=True, return_tensors=\"pt\")\n# attention_mask: [[1, 1, 0, 0], [1, 1, 1, 1]]Causal mask: Lower-triangular mask for autoregressive models. Token at position i can only attend to positions 0..i.
\n# Created internally for decoder models\n# [[1, 0, 0, 0],\n# [1, 1, 0, 0],\n# [1, 1, 1, 0],\n# [1, 1, 1, 1]]Bidirectional mask: Full attention for encoder models like BERT. Every token attends to every other token.
\nEncoder-decoder mask: Cross-attention from decoder to encoder uses the encoder’s padding mask.
\nModels combine these masks. A causal LM with padding combines the causal mask with the padding mask using element-wise multiplication.
\nThe attention mask discussion covers the differences in detail.
\nTokenization converts raw text into the discrete tokens models consume. Modern tokenizers use subword algorithms that balance vocabulary size against sequence length.
\nFour algorithms dominate according to the tokenizer summary:
\nByte-Pair Encoding (BPE): Starts with individual characters, iteratively merges the most frequent pair. Used by GPT-2, GPT-3, GPT-4, LLaMA, RoBERTa.
\nTraining corpus: \"low lower lowest\"\nInitial: ['l', 'o', 'w', ' ', 'l', 'o', 'w', 'e', 'r', ...]\nAfter merges: ['low', 'low', 'er', 'low', 'est']WordPiece: Similar to BPE but merges based on likelihood maximization rather than frequency. Prefixes continuations with ##. Used by BERT, DistilBERT, Electra.
\"unbelievable\" → [\"un\", \"##believ\", \"##able\"]Unigram: Starts with a large vocabulary, iteratively removes tokens that least affect the training loss. Probabilistic: can produce multiple valid tokenizations. Used within SentencePiece.
\nSentencePiece: A framework that treats text as a raw byte stream, enabling language-agnostic tokenization. Can use BPE or Unigram internally. Used by T5, ALBERT, XLNet, Gemma.
\nThe tokenization algorithms comparison shows that BPE offers better contextual specialization while SentencePiece achieves better encoding efficiency.
\nFast tokenizers serialize their configuration to tokenizer.json. This file encodes:
{\n \"version\": \"1.0\",\n \"truncation\": null,\n \"padding\": null,\n \"added_tokens\": [...],\n \"normalizer\": {\n \"type\": \"Sequence\",\n \"normalizers\": [...]\n },\n \"pre_tokenizer\": {\n \"type\": \"ByteLevel\",\n \"add_prefix_space\": false\n },\n \"model\": {\n \"type\": \"BPE\",\n \"vocab\": {\"<s>\": 0, \"</s>\": 1, ...},\n \"merges\": [\"Ġ t\", \"Ġ a\", \"h e\", ...]\n },\n \"decoder\": {...}\n}The merges array encodes BPE merge rules in order of application. During tokenization, the algorithm:
Special tokens serve structural roles:
\n[CLS] / <s>: Sequence start, used for classification[SEP] / </s>: Sequence end or separator[PAD]: Padding for batching[UNK]: Unknown tokens (rare with subword tokenizers)[MASK]: Masked positions for MLM trainingModels expect specific special tokens. Using the wrong ones breaks the model:
\ntokenizer = AutoTokenizer.from_pretrained(\"meta-llama/Llama-3.1-8B\")\n\n# Chat models need proper formatting\nmessages = [{\"role\": \"user\", \"content\": \"Hello\"}]\nformatted = tokenizer.apply_chat_template(messages, tokenize=False)\n# Adds <|begin_of_text|>, <|start_header_id|>, etc.The fast tokenizers guide explains the difference:
\nSlow tokenizers (PreTrainedTokenizer): Pure Python implementation. Full control, easier to modify, but 10-100x slower.
Fast tokenizers (PreTrainedTokenizerFast): Rust backend via the tokenizers library. Parallel processing, sub-millisecond tokenization for most inputs.
The fast tokenizer provides additional features:
\ntokenizer = AutoTokenizer.from_pretrained(\"bert-base-uncased\")\nencoding = tokenizer(\"Hello world\", return_offsets_mapping=True)\n\n# Character offsets for each token\nprint(encoding.offset_mapping)\n# [(0, 5), (6, 11)] # \"Hello\", \"world\"\n\n# Map token index to word index\nprint(encoding.word_ids())\n# [0, 1]The tokenizers quicktour shows how to train custom tokenizers:
\nfrom tokenizers import Tokenizer\nfrom tokenizers.models import BPE\nfrom tokenizers.trainers import BpeTrainer\nfrom tokenizers.pre_tokenizers import Whitespace\n\n# Initialize with BPE model\ntokenizer = Tokenizer(BPE(unk_token=\"[UNK]\"))\ntokenizer.pre_tokenizer = Whitespace()\n\n# Configure trainer\ntrainer = BpeTrainer(\n vocab_size=30000,\n min_frequency=2,\n special_tokens=[\"[UNK]\", \"[CLS]\", \"[SEP]\", \"[PAD]\", \"[MASK]\"]\n)\n\n# Train on files\nfiles = [\"wiki.txt\", \"books.txt\"]\ntokenizer.train(files, trainer)\n\n# Save\ntokenizer.save(\"my-tokenizer.json\")For byte-level BPE (like GPT-2):
\nfrom tokenizers import pre_tokenizers\nfrom tokenizers.pre_tokenizers import ByteLevel\n\ntokenizer = Tokenizer(BPE(unk_token=\"[UNK]\"))\ntokenizer.pre_tokenizer = ByteLevel(add_prefix_space=False)\n\ntrainer = BpeTrainer(\n vocab_size=50257,\n initial_alphabet=pre_tokenizers.ByteLevel.alphabet(),\n special_tokens=[\"[UNK]\", \"[PAD]\"]\n)Training a tokenizer on a GB of text takes under 20 seconds with the Rust backend.
\nLoading large models requires careful memory management. Transformers and Accelerate provide several mechanisms.
\nLarge models split weights across multiple files (shards). A 70B model might have 15 shards of ~10GB each. The model.safetensors.index.json file maps parameter names to shard files:
{\n \"metadata\": {\"total_size\": 140000000000},\n \"weight_map\": {\n \"model.embed_tokens.weight\": \"model-00001-of-00015.safetensors\",\n \"model.layers.0.self_attn.q_proj.weight\": \"model-00001-of-00015.safetensors\",\n \"model.layers.0.self_attn.k_proj.weight\": \"model-00001-of-00015.safetensors\",\n ...\n }\n}During loading, Transformers:
\nThis keeps peak memory at (model size) + (largest shard size) rather than (model size) * 2.
\nThe big model inference guide explains automatic device placement:
\nmodel = AutoModelForCausalLM.from_pretrained(\n \"meta-llama/Llama-3.1-70B\",\n device_map=\"auto\",\n torch_dtype=torch.bfloat16,\n)Accelerate computes a device map by:
\n_no_split_modules crosses device boundariesAvailable strategies:
\n\"auto\": Fill GPUs in order, overflow to CPU/disk\"balanced\": Distribute evenly across GPUs\"balanced_low_0\": Keep GPU 0 lighter (useful when GPU 0 handles other tasks)\"sequential\": Fill devices completely before moving to nextView the computed map:
\nfrom accelerate import infer_auto_device_map\nfrom transformers import AutoConfig, AutoModelForCausalLM\n\nconfig = AutoConfig.from_pretrained(\"meta-llama/Llama-3.1-70B\")\nwith init_empty_weights():\n model = AutoModelForCausalLM.from_config(config)\n\ndevice_map = infer_auto_device_map(model, max_memory={0: \"24GB\", 1: \"24GB\", \"cpu\": \"100GB\"})\nprint(device_map)\n# {'model.embed_tokens': 0, 'model.layers.0': 0, ..., 'model.layers.40': 1, ...}Important limitation: device_map=\"auto\" supports inference only, not training. The hook-based execution doesn’t support backpropagation across devices.
The bitsandbytes guide details on-the-fly quantization:
\n8-bit quantization (LLM.int8):
\nmodel = AutoModelForCausalLM.from_pretrained(\n \"meta-llama/Llama-3.1-8B\",\n load_in_8bit=True,\n device_map=\"auto\",\n)Uses mixed-precision decomposition: outlier features (magnitude > 6.0 by default) stay in FP16, the rest quantizes to INT8. This preserves quality for models with outlier activations.
\n4-bit quantization (NF4/FP4):
\nfrom transformers import BitsAndBytesConfig\n\nconfig = BitsAndBytesConfig(\n load_in_4bit=True,\n bnb_4bit_quant_type=\"nf4\", # NormalFloat4 or \"fp4\"\n bnb_4bit_compute_dtype=torch.bfloat16, # Compute in bf16\n bnb_4bit_use_double_quant=True, # Quantize the quantization constants\n)NF4 (NormalFloat4) optimizes for normally-distributed weights by placing quantization levels at distribution quantiles. Double quantization applies 8-bit quantization to the scaling factors, saving an additional 0.4 bits per parameter.
\nPyTorch doesn’t support 4-bit dtypes, so bitsandbytes packs two 4-bit values into one 8-bit value, changing tensor shapes. Computation happens in 16/32-bit after dequantization.
\nThe safetensors documentation describes lazy loading:
\nfrom safetensors import safe_open\n\nwith safe_open(\"model.safetensors\", framework=\"pt\") as f:\n # Only metadata loaded at this point\n print(f.keys()) # List all tensor names\n\n # Individual tensors load on-demand\n tensor = f.get_tensor(\"model.layers.0.self_attn.q_proj.weight\")Safetensors uses memory-mapping: the OS maps the file into virtual address space, loading pages only when accessed. This enables:
\nThe file layout keeps tensor metadata contiguous at the start, enabling fast scanning without reading weight data.
\nEstimate memory requirements before attempting to load:
\nfrom accelerate.commands.estimate import estimate_command\n\n# CLI\n# accelerate estimate-memory meta-llama/Llama-3.1-70B\n\n# Programmatic\nfrom accelerate import init_empty_weights\nfrom transformers import AutoConfig, AutoModelForCausalLM\n\nconfig = AutoConfig.from_pretrained(\"meta-llama/Llama-3.1-70B\")\n\nwith init_empty_weights():\n model = AutoModelForCausalLM.from_config(config)\n\nparam_bytes = sum(p.numel() * p.element_size() for p in model.parameters())\nprint(f\"Model size: {param_bytes / 1e9:.1f} GB in {model.dtype}\")The init_empty_weights() context creates tensors on PyTorch’s “meta” device, which stores only shape and dtype, not actual data.
The Trainer documentation covers the main training API. Key components:
\nTraining loop structure:
\nfor epoch in range(num_epochs):\n for step, batch in enumerate(train_dataloader):\n # Forward pass\n outputs = model(**batch)\n loss = outputs.loss\n\n # Scale loss for gradient accumulation\n loss = loss / gradient_accumulation_steps\n\n # Backward pass\n loss.backward()\n\n # Update weights every N steps\n if (step + 1) % gradient_accumulation_steps == 0:\n optimizer.step()\n lr_scheduler.step()\n optimizer.zero_grad()Subclassing for custom behavior:
\nfrom transformers import Trainer\n\nclass CustomTrainer(Trainer):\n def compute_loss(self, model, inputs, return_outputs=False, num_items_in_batch=None):\n outputs = model(**inputs)\n loss = my_custom_loss(outputs.logits, inputs[\"labels\"])\n return (loss, outputs) if return_outputs else loss\n\n def training_step(self, model, inputs, num_items_in_batch=None):\n # Custom training step logic\n ...The gradient accumulation blog post explains the details:
\nGradient accumulation simulates larger batch sizes by accumulating gradients over multiple forward passes before updating weights.
\ntraining_args = TrainingArguments(\n per_device_train_batch_size=4,\n gradient_accumulation_steps=8,\n # Effective batch size = 4 * 8 = 32\n)Internally, the Trainer scales the loss by 1/gradient_accumulation_steps before each backward pass. This ensures the accumulated gradients match what you’d get from a single large batch.
Recent versions fixed a subtle bug: some loss functions (like cross-entropy) already average over batch elements, so the scaling was being applied twice in certain configurations. The fix introduced num_items_in_batch parameter to loss computation functions.
The PyTorch AMP documentation covers mixed precision:
\nFP16 training (requires loss scaling):
\nfrom torch.amp import autocast, GradScaler\n\nscaler = GradScaler(\"cuda\")\n\nfor batch in dataloader:\n optimizer.zero_grad()\n\n with autocast(\"cuda\", dtype=torch.float16):\n outputs = model(**batch)\n loss = outputs.loss\n\n scaler.scale(loss).backward()\n scaler.step(optimizer)\n scaler.update()GradScaler prevents gradient underflow by scaling loss up before backward (so gradients are larger), then scaling gradients down before optimizer step.
BF16 training (no loss scaling needed):
\nwith autocast(\"cuda\", dtype=torch.bfloat16):\n outputs = model(**batch)\n loss = outputs.loss\n\nloss.backward()\noptimizer.step()BFloat16 has the same exponent range as FP32, so it doesn’t suffer from underflow. GradScaler is unnecessary and can harm training.
\nWith Trainer:
\ntraining_args = TrainingArguments(\n bf16=True, # or fp16=True\n # ...\n)The PEFT integration guide shows how adapters work with Trainer:
\nfrom peft import LoraConfig, TaskType, get_peft_model\nfrom transformers import AutoModelForCausalLM, Trainer, TrainingArguments\n\n# Load base model\nmodel = AutoModelForCausalLM.from_pretrained(\"meta-llama/Llama-3.1-8B\")\n\n# Configure LoRA\nlora_config = LoraConfig(\n r=16,\n lora_alpha=32,\n target_modules=[\"q_proj\", \"v_proj\", \"k_proj\", \"o_proj\"],\n lora_dropout=0.05,\n task_type=TaskType.CAUSAL_LM,\n)\n\n# Wrap model with PEFT\nmodel = get_peft_model(model, lora_config)\nmodel.print_trainable_parameters()\n# trainable params: 13,631,488 || all params: 8,043,892,736 || trainable%: 0.17\n\n# Train normally - Trainer handles the PEFT model\ntrainer = Trainer(model=model, args=training_args, train_dataset=dataset)\ntrainer.train()PEFT works by:
\ntarget_modules)For QLoRA (quantized base + LoRA):
\nmodel = AutoModelForCausalLM.from_pretrained(\n \"meta-llama/Llama-3.1-8B\",\n load_in_4bit=True,\n bnb_4bit_quant_type=\"nf4\",\n bnb_4bit_compute_dtype=torch.bfloat16,\n)\nmodel = get_peft_model(model, lora_config)The quantized weights stay frozen (they can’t be trained anyway), and only the FP16/BF16 LoRA matrices update.
\nThe storage documentation explains file handling:
\nHistorically, Hub repositories used Git LFS (Large File Storage) for files over 10MB. LFS stores file content in a separate server, with Git tracking only pointer files.
\nAs of May 2025, new repositories default to Xet storage, which offers chunk-level deduplication. When you modify a file, only changed chunks upload, not the entire file. This matters for iterative checkpoint uploads during training.
\nFile size limits:
\nRepository limits:
\nModel repositories follow conventions that enable auto-loading:
\nmy-model/\n├── README.md # Model card with YAML frontmatter\n├── config.json # Model architecture configuration\n├── model.safetensors # Weights (or sharded)\n├── model.safetensors.index.json # Shard index if sharded\n├── tokenizer.json # Fast tokenizer config\n├── tokenizer_config.json # Tokenizer settings\n├── special_tokens_map.json # Special token definitions\n├── vocab.json # Vocabulary (some tokenizers)\n├── merges.txt # BPE merges (some tokenizers)\n└── generation_config.json # Default generation settingsDataset repositories:
\nmy-dataset/\n├── README.md # Dataset card\n├── data/\n│ ├── train-00000-of-00010.parquet\n│ ├── train-00001-of-00010.parquet\n│ └── ...\n└── dataset_info.json # Dataset metadataThe model cards documentation specifies the metadata format:
\n---\nlanguage:\n - en\n - zh\nlicense: apache-2.0\nlibrary_name: transformers\npipeline_tag: text-generation\ntags:\n - llama\n - chat\ndatasets:\n - HuggingFaceH4/ultrachat_200k\nbase_model: meta-llama/Llama-3.1-8B\nmodel-index:\n - name: my-model\n results:\n - task:\n type: text-generation\n dataset:\n name: MMLU\n type: cais/mmlu\n metrics:\n - name: accuracy\n type: accuracy\n value: 0.72\n---\n# My Model\n\nModel description here...The Hub parses this YAML to:
\npipeline_tagThe huggingface_hub documentation covers the Python client:
\nfrom huggingface_hub import HfApi, hf_hub_download, snapshot_download\n\napi = HfApi()\n\n# List repository files\nfiles = api.list_repo_files(\"meta-llama/Llama-3.1-8B\")\n\n# Get model info\ninfo = api.model_info(\"meta-llama/Llama-3.1-8B\")\nprint(info.downloads) # Download count\nprint(info.tags) # Tags like \"llama\", \"text-generation\"\n\n# Download single file (cached)\npath = hf_hub_download(\n repo_id=\"meta-llama/Llama-3.1-8B\",\n filename=\"config.json\",\n)\n\n# Download entire repo\nlocal_dir = snapshot_download(\"meta-llama/Llama-3.1-8B\")The library uses a content-addressed cache at ~/.cache/huggingface/hub/:
hub/\n├── models--meta-llama--Llama-3.1-8B/\n│ ├── refs/\n│ │ └── main # Points to commit hash\n│ ├── blobs/\n│ │ └── abc123... # Content-addressed files\n│ └── snapshots/\n│ └── def456.../ # Symlinks to blobsThis deduplicates identical files across model versions and enables instant switching between revisions.
\nThe Datasets Arrow documentation explains the storage layer:
\nArrow is a columnar memory format optimized for analytics. Key properties:
\nfrom datasets import load_dataset\n\ndataset = load_dataset(\"imdb\", split=\"train\")\n\n# Dataset is backed by Arrow file on disk\nprint(dataset.cache_files)\n# [{'filename': '~/.cache/huggingface/datasets/imdb/.../train/dataset.arrow'}]\n\n# Access uses memory mapping - doesn't load into RAM\nprint(dataset[0]) # Pages in just this exampleThis lets you iterate over datasets larger than RAM. The OS virtual memory system handles what’s actually in physical memory.
\nThe map parallelization discussion explains multiprocessing:
\ndef process(examples):\n return {\"length\": [len(t) for t in examples[\"text\"]]}\n\n# Single process\ndataset = dataset.map(process, batched=True)\n\n# Parallel processing\ndataset = dataset.map(process, batched=True, num_proc=4)With num_proc > 1:
num_proc shardsRequirements for parallelization:
\nThe streaming documentation covers iterable datasets:
\ndataset = load_dataset(\"HuggingFaceFW/fineweb\", split=\"train\", streaming=True)\n\nfor example in dataset:\n process(example)Streaming datasets:
\nFor sharded datasets, streaming fetches shards sequentially. Shuffling operates within a buffer:
\n# Shuffles within buffer of 10000 examples\ndataset = dataset.shuffle(seed=42, buffer_size=10000)To resume from a checkpoint:
\n# Skip to position (fetches from start of current shard)\ndataset = dataset.skip(1000)Resuming isn’t instant because it must re-read from the beginning of the current shard.
\nThe dataset script documentation shows how to write loaders:
\nimport datasets\n\nclass MyDataset(datasets.GeneratorBasedBuilder):\n \"\"\"My custom dataset.\"\"\"\n\n VERSION = datasets.Version(\"1.0.0\")\n\n def _info(self):\n return datasets.DatasetInfo(\n description=\"My dataset description\",\n features=datasets.Features({\n \"text\": datasets.Value(\"string\"),\n \"label\": datasets.ClassLabel(names=[\"negative\", \"positive\"]),\n }),\n )\n\n def _split_generators(self, dl_manager):\n # Download and extract data\n data_dir = dl_manager.download_and_extract(\"https://example.com/data.zip\")\n\n return [\n datasets.SplitGenerator(\n name=datasets.Split.TRAIN,\n gen_kwargs={\"filepath\": f\"{data_dir}/train.jsonl\"},\n ),\n datasets.SplitGenerator(\n name=datasets.Split.TEST,\n gen_kwargs={\"filepath\": f\"{data_dir}/test.jsonl\"},\n ),\n ]\n\n def _generate_examples(self, filepath):\n with open(filepath) as f:\n for idx, line in enumerate(f):\n data = json.loads(line)\n yield idx, {\n \"text\": data[\"text\"],\n \"label\": data[\"label\"],\n }For Arrow-based builders (better for large datasets):
\nclass MyArrowDataset(datasets.ArrowBasedBuilder):\n def _generate_tables(self, filepath):\n # Yield PyArrow tables instead of individual examples\n table = pq.read_table(filepath)\n yield 0, tableDiffusers handles diffusion models for image, video, and audio generation. It supports Stable Diffusion, SDXL, Flux, Kandinsky, and other architectures.
\nimport torch\nfrom diffusers import DiffusionPipeline\n\n# Load Stable Diffusion XL\npipe = DiffusionPipeline.from_pretrained(\n \"stabilityai/stable-diffusion-xl-base-1.0\",\n torch_dtype=torch.float16,\n)\npipe.to(\"cuda\")\n\n# Generate\nimage = pipe(\"A cat astronaut floating in space, digital art\").images[0]\nimage.save(\"cat_astronaut.png\")FLUX is a 12 billion parameter rectified flow transformer from Black Forest Labs. It produces high-quality images with strong text rendering and prompt adherence.
\nimport torch\nfrom diffusers import FluxPipeline\n\npipe = FluxPipeline.from_pretrained(\n \"black-forest-labs/FLUX.1-schnell\",\n torch_dtype=torch.bfloat16\n)\npipe.enable_model_cpu_offload()\n\n# FLUX.1-schnell generates in 1-4 steps\nimage = pipe(\n \"A photo of a mountain lake at sunset\",\n guidance_scale=0.0,\n num_inference_steps=4,\n).images[0]\nimage.save(\"lake.png\")FLUX.1-schnell is distilled for speed. FLUX.1-dev offers higher quality with more steps. FLUX.1-Kontext handles image editing with text instructions.
\nDiffusers provides multiple strategies for running on limited VRAM:
\n# CPU offloading - moves components to CPU when not in use\npipe.enable_model_cpu_offload()\n\n# Sequential CPU offloading - more aggressive, slower\npipe.enable_sequential_cpu_offload()\n\n# Attention slicing - trades compute for memory\npipe.enable_attention_slicing()\n\n# VAE tiling - generate high-res without OOM\npipe.enable_vae_tiling()Load style or concept LoRAs:
\npipe.load_lora_weights(\"username/style-lora\", weight_name=\"lora.safetensors\")\n\n# Adjust LoRA strength\npipe.fuse_lora(lora_scale=0.8)\n\n# Unload\npipe.unfuse_lora()\npipe.unload_lora_weights()Spaces are web applications hosted on Hugging Face. The key insight: Spaces are Git repositories. You can clone them, run them locally, and modify them like any codebase.
\n# Clone a Space\ngit clone https://huggingface.co/spaces/username/my-space\ncd my-space\n\n# Install dependencies\npython -m venv venv\nsource venv/bin/activate\npip install -r requirements.txt\n\n# Run locally\npython app.py # or gradio app.py for Gradio appsSpaces typically use Gradio or Streamlit for the frontend. The same code runs identically on your machine and on Hugging Face’s servers.
\nimport gradio as gr\nfrom transformers import pipeline\n\nclassifier = pipeline(\"sentiment-analysis\")\n\ndef classify(text):\n result = classifier(text)[0]\n return f\"{result['label']}: {result['score']:.4f}\"\n\ndemo = gr.Interface(fn=classify, inputs=\"text\", outputs=\"text\")\ndemo.launch()Configure a GitHub Action to push changes to both GitHub and Hugging Face:
\nname: Sync to Hugging Face\non:\n push:\n branches: [main]\njobs:\n sync:\n runs-on: ubuntu-latest\n steps:\n - uses: actions/checkout@v3\n - name: Push to HF\n run: |\n git push https://user:${{ secrets.HF_TOKEN }}@huggingface.co/spaces/user/space mainSpaces support Docker for custom environments, persistent storage for databases, and GPU runtimes for ML inference.
\nAccelerate lets you run the same PyTorch training code on any hardware configuration: single GPU, multi-GPU, TPU, or distributed clusters. Add a few lines to existing code:
\nfrom accelerate import Accelerator\n\naccelerator = Accelerator()\n\n# Wrap model, optimizer, dataloader\nmodel, optimizer, dataloader = accelerator.prepare(model, optimizer, dataloader)\n\nfor batch in dataloader:\n outputs = model(**batch)\n loss = outputs.loss\n accelerator.backward(loss)\n optimizer.step()\n optimizer.zero_grad()Configure distributed training with the CLI:
\naccelerate config # Interactive setup\naccelerate launch train.py # Launch with configAccelerate handles mixed precision (fp16, bf16, fp8), DeepSpeed integration, and FSDP for sharding large models.
\nPEFT implements parameter-efficient fine-tuning methods. LoRA is the most popular: freeze the base model and train small adapter matrices.
\nfrom peft import LoraConfig, get_peft_model\nfrom transformers import AutoModelForCausalLM\n\nmodel = AutoModelForCausalLM.from_pretrained(\"meta-llama/Llama-3.1-8B\")\n\nlora_config = LoraConfig(\n r=16, # Rank\n lora_alpha=32, # Scaling\n target_modules=\"all-linear\", # Apply to all linear layers\n lora_dropout=0.05,\n)\n\npeft_model = get_peft_model(model, lora_config)\npeft_model.print_trainable_parameters()\n# trainable params: 41,943,040 || all params: 8,030,261,248 || trainable%: 0.52A 7B model drops from training billions of parameters to millions. The base model stays frozen; only the adapter trains. Merge adapters back into the base model for inference or keep them separate to swap styles.
\nPEFT supports LoRA variants like DoRA (magnitude and direction decomposition) and methods beyond LoRA: IA3, AdaLoRA, and prompt tuning.
\nTRL provides trainers for post-training: supervised fine-tuning, RLHF, and preference optimization.
\nfrom trl import SFTTrainer\nfrom transformers import AutoModelForCausalLM, AutoTokenizer\nfrom datasets import load_dataset\n\nmodel = AutoModelForCausalLM.from_pretrained(\"meta-llama/Llama-3.1-8B\")\ntokenizer = AutoTokenizer.from_pretrained(\"meta-llama/Llama-3.1-8B\")\ndataset = load_dataset(\"your-dataset\")\n\ntrainer = SFTTrainer(\n model=model,\n train_dataset=dataset,\n tokenizer=tokenizer,\n max_seq_length=2048,\n)\n\ntrainer.train()For preference optimization, DPOTrainer implements Direct Preference Optimization:
\nfrom trl import DPOTrainer, DPOConfig\n\nconfig = DPOConfig(\n beta=0.1,\n output_dir=\"dpo_model\",\n)\n\ntrainer = DPOTrainer(\n model=model,\n ref_model=ref_model,\n args=config,\n train_dataset=preference_dataset, # Has 'chosen' and 'rejected' columns\n tokenizer=tokenizer,\n)GRPOTrainer implements Group Relative Policy Optimization, the algorithm behind DeepSeek R1. It avoids needing a separate reward model by comparing outputs within groups.
\nOptimum provides hardware-specific optimizations. Export to ONNX, quantize, and run on specialized accelerators:
\nfrom optimum.onnxruntime import ORTModelForSequenceClassification\n\n# Load and export to ONNX\nmodel = ORTModelForSequenceClassification.from_pretrained(\n \"distilbert-base-uncased-finetuned-sst-2-english\",\n export=True\n)\n\n# Or load existing ONNX model\nmodel = ORTModelForSequenceClassification.from_pretrained(\"onnx_model_dir\")Optimum integrates with:
\nThe optimum-benchmark tool compares performance across backends and quantization schemes.
\nfrom datasets import load_dataset\nfrom transformers import (\n AutoModelForCausalLM,\n AutoTokenizer,\n TrainingArguments,\n)\nfrom peft import LoraConfig\nfrom trl import SFTTrainer\n\n# Load model with 4-bit quantization\nmodel_id = \"meta-llama/Llama-3.1-8B\"\n\nmodel = AutoModelForCausalLM.from_pretrained(\n model_id,\n load_in_4bit=True,\n device_map=\"auto\",\n)\ntokenizer = AutoTokenizer.from_pretrained(model_id)\ntokenizer.pad_token = tokenizer.eos_token\n\n# Load dataset\ndataset = load_dataset(\"databricks/databricks-dolly-15k\", split=\"train\")\n\n# LoRA config for QLoRA\npeft_config = LoraConfig(\n r=16,\n lora_alpha=32,\n target_modules=\"all-linear\",\n lora_dropout=0.05,\n task_type=\"CAUSAL_LM\",\n)\n\n# Training arguments\ntraining_args = TrainingArguments(\n output_dir=\"./llama-finetuned\",\n num_train_epochs=1,\n per_device_train_batch_size=4,\n gradient_accumulation_steps=4,\n learning_rate=2e-4,\n bf16=True,\n logging_steps=10,\n save_strategy=\"epoch\",\n)\n\n# Train\ntrainer = SFTTrainer(\n model=model,\n train_dataset=dataset,\n peft_config=peft_config,\n args=training_args,\n tokenizer=tokenizer,\n)\n\ntrainer.train()\ntrainer.save_model()from sentence_transformers import SentenceTransformer\nfrom transformers import pipeline\nimport numpy as np\n\n# Embedding model\nembedder = SentenceTransformer(\"BAAI/bge-base-en-v1.5\")\n\n# Generator\ngenerator = pipeline(\n \"text-generation\",\n model=\"meta-llama/Llama-3.2-3B-Instruct\",\n device_map=\"auto\",\n)\n\n# Sample documents\ndocuments = [\n \"Python was created by Guido van Rossum and released in 1991.\",\n \"JavaScript was created by Brendan Eich in 1995.\",\n \"Rust was developed by Mozilla and released in 2015.\",\n]\n\n# Embed documents\ndoc_embeddings = embedder.encode(documents, normalize_embeddings=True)\n\ndef retrieve_and_generate(query: str, top_k: int = 2) -> str:\n # Embed query\n query_embedding = embedder.encode([query], normalize_embeddings=True)\n\n # Find similar documents\n scores = np.dot(doc_embeddings, query_embedding.T).flatten()\n top_indices = np.argsort(scores)[-top_k:][::-1]\n\n context = \"\\n\".join([documents[i] for i in top_indices])\n\n # Generate answer\n prompt = f\"\"\"Context: {context}\n\nQuestion: {query}\n\nAnswer based on the context above:\"\"\"\n\n response = generator(prompt, max_new_tokens=100, do_sample=False)\n return response[0][\"generated_text\"]\n\nanswer = retrieve_and_generate(\"When was Python created?\")\nprint(answer)import torch\nfrom diffusers import FluxPipeline\nfrom transformers import pipeline\n\n# Image generation\nflux = FluxPipeline.from_pretrained(\n \"black-forest-labs/FLUX.1-schnell\",\n torch_dtype=torch.bfloat16\n)\nflux.enable_model_cpu_offload()\n\n# Image captioning\ncaptioner = pipeline(\n \"image-to-text\",\n model=\"Salesforce/blip2-opt-2.7b\",\n device_map=\"auto\",\n)\n\n# Generate image\nprompt = \"A cozy cabin in the woods during autumn, warm lighting\"\nimage = flux(prompt, num_inference_steps=4).images[0]\nimage.save(\"cabin.png\")\n\n# Caption the generated image\ncaption = captioner(image)\nprint(f\"Generated caption: {caption[0]['generated_text']}\")# train.py\nfrom accelerate import Accelerator\nfrom transformers import AutoModelForSequenceClassification, AutoTokenizer\nfrom torch.utils.data import DataLoader\nfrom datasets import load_dataset\nimport torch\n\naccelerator = Accelerator(mixed_precision=\"bf16\")\n\n# Load model and tokenizer\nmodel = AutoModelForSequenceClassification.from_pretrained(\n \"bert-base-uncased\",\n num_labels=2,\n)\ntokenizer = AutoTokenizer.from_pretrained(\"bert-base-uncased\")\n\n# Load and tokenize dataset\ndataset = load_dataset(\"imdb\", split=\"train[:1000]\")\n\ndef tokenize(examples):\n return tokenizer(examples[\"text\"], truncation=True, padding=\"max_length\", max_length=512)\n\ndataset = dataset.map(tokenize, batched=True)\ndataset.set_format(\"torch\", columns=[\"input_ids\", \"attention_mask\", \"label\"])\n\ndataloader = DataLoader(dataset, batch_size=8, shuffle=True)\noptimizer = torch.optim.AdamW(model.parameters(), lr=2e-5)\n\n# Prepare for distributed training\nmodel, optimizer, dataloader = accelerator.prepare(model, optimizer, dataloader)\n\n# Training loop\nmodel.train()\nfor epoch in range(3):\n for batch in dataloader:\n outputs = model(\n input_ids=batch[\"input_ids\"],\n attention_mask=batch[\"attention_mask\"],\n labels=batch[\"label\"],\n )\n accelerator.backward(outputs.loss)\n optimizer.step()\n optimizer.zero_grad()\n\n accelerator.print(f\"Epoch {epoch} complete\")\n\naccelerator.save_model(model, \"trained_model\")Launch with:
\naccelerate launch --multi_gpu --num_processes 4 train.pyRunning AI models locally instead of through cloud APIs addresses four problems at once: privacy, latency, cost, and availability.
\nPrivacy: Cloud-based GenAI tools exposed approximately 3 million sensitive records per organization in the first half of 2025, according to data from Microsoft Copilot deployments [1]. Keeping inference on-device shrinks attack surface and regulatory footprint. For workflows in legal, health, and finance, avoiding data transmission to external servers is often the simplest path to compliance with GDPR and HIPAA.
\nLatency: Local GPU inference delivers sub-50ms latency versus 100-500ms for cloud roundtrips. Cactus, a Y Combinator-backed startup, demonstrated sub-50ms time-to-first-token for on-device inference [2]. TinyML solutions can achieve latencies as low as 0-5ms for inference tasks, compared to 10-500ms for cloud IoT solutions [3].
\nCost: Local inference eliminates per-token API costs. Once you own the hardware, inference is free. IDC and Gartner predict that by 2027, over 60% of all AI inference processes will happen locally rather than in the cloud [4].
\nOffline capability: Local inference removes network hops and eliminates the need for a constant internet connection. Apps keep working on factory floors, in hospitals, and in low-connectivity environments.
\nREAP is a one-shot compression method for Mixture-of-Experts (MoE) language models developed by Cerebras Research. It removes up to 50% of experts from models as large as 1 trillion parameters while largely maintaining baseline model quality [5].
\nMoE models like Mixtral, DeepSeek, and Qwen achieve high capability by routing tokens to different expert subnetworks. This architecture creates redundancy: not all experts contribute equally to every inference. REAP exploits this by identifying and removing the least important experts.
\nREAP selects experts to prune based on a saliency criterion that considers two factors:
\nBy combining these factors, REAP identifies experts that are both rarely used and have little impact when they are used. The method is one-shot, meaning it requires no fine-tuning after pruning.
\nThe key insight from the REAP paper is that expert pruning outperforms expert merging for generative tasks. The researchers proved that merging introduces an irreducible error by causing a “functional subspace collapse” due to the loss of the router’s independent, input-dependent control over experts [6].
\nOn the Qwen3-480B-Coder-FP8 model, REAP at 50% pruning retains:
\nThe method achieves near-lossless compression on code generation and tool-calling tasks with Qwen3-Coder-480B and Kimi-K2, even after pruning 50% of experts [5].
\nThe official REAP implementation is available at github.com/CerebrasResearch/reap. Pruned models are available on HuggingFace in the Cerebras REAP collection, including models like cerebras/Kimi-Linear-REAP-35B-A3B-Instruct and cerebras/MiniMax-M2-REAP-172B-A10B [7].
Speculative decoding accelerates LLM inference by predicting and verifying multiple tokens simultaneously. The technique uses a smaller draft model to propose tokens and a larger target model to verify them in parallel.
\nThe draft-target approach works as follows:
\nCompared with standard autoregressive decoding, which produces one token per pass, speculative decoding generates multiple tokens at once, cutting latency without any impact on accuracy [8].
\nTraditional draft models: The draft model must be significantly smaller (10-50x) to achieve inference acceleration. The speedup ratio increases as the target model size increases [9].
\nEAGLE (Extrapolation Algorithm for Greater Language-model Efficiency): EAGLE-3 uses a lightweight autoregressive prediction head attached to the target model’s internal layers to generate candidate tokens, eliminating the need for a separate draft model [10].
\nN-gram and Suffix Decoding: Suffix Decoding generates draft tokens by pattern-matching using the last n generated tokens against both the prompt and previous generations, using frequency counts to propose the most likely continuations [10].
\nWith vLLM, speculative decoding can be enabled via configuration:
\nfrom vllm import LLM, SamplingParams\n\nllm = LLM(\n model=\"meta-llama/Meta-Llama-3.1-70B-Instruct\",\n speculative_model=\"meta-llama/Llama-3.2-1B-Instruct\",\n num_speculative_tokens=5,\n)\n\nsampling_params = SamplingParams(temperature=0.7, max_tokens=256)\noutputs = llm.generate([\"Explain transformers:\"], sampling_params)SpecForge’s Llama 4 Maverick draft model achieves a 2.18x speedup on MT-Bench, while the Scout variant delivers a 2.0x acceleration [11]. Acceptance rate is the critical metric: high acceptance means more tokens accepted per round, fewer target model forward passes, lower latency, and better GPU utilization.
\nQuantization reduces the precision of model weights, trading a small amount of accuracy for large memory and speed gains.
\nPost-Training Quantization (PTQ) applies quantization after training is complete. It’s fast to implement but can lose accuracy, especially at low bit-widths.
\nQuantization-Aware Training (QAT) integrates quantization into the training process. The model learns to handle quantization errors during training. PyTorch demonstrated that QAT can recover up to 96% of the accuracy degradation on HellaSwag and 68% of the perplexity degradation on WikiText for Llama3 compared to PTQ [12].
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Aspect | PTQ | QAT |
|---|---|---|
| Training required | No | Yes |
| Compute cost | Low | High |
| Accuracy at INT8 | Good | Excellent |
| Accuracy at INT4 | Variable | Good |
| Time to deploy | Minutes | Hours/Days |
GGUF (Georgi Gerganov Universal Format) is designed for efficient CPU-based inference within the llama.cpp ecosystem. The format supports multiple quantization levels [13]:
\n![\"GGUF](\"https://blog.ecitis.org/feeds/figures/local-ai-inferencing-techniques-0.webp\")
| Quantization | Size (7B model) | Perplexity increase | Notes |
|---|---|---|---|
| Q8_0 | ~7.0 GB | +0.0004 | Highest quality |
| Q5_K_M | ~5.33 GB | +0.0142 | Higher quality, slightly larger |
| Q4_K_M | ~4.58 GB | +0.0535 | Recommended default, best balance |
| Q4_K_S | ~4.37 GB | +0.0992 | Smaller, lower quality |
| Q3_K_M | ~3.52 GB | +0.2437 | Aggressive compression |
Q4_K_M is the “safe default” for phones and lighter Macs. Q5_K_M improves detail and reasoning stability. Use an importance matrix (--imatrix) for optimal results [14].
# Quantize with llama.cpp\n./llama-quantize model.gguf model-Q4_K_M.gguf Q4_K_MAWQ (Activation-aware Weight Quantization): Developed by MIT-HAN lab, AWQ protects salient weights by observing activations rather than weights themselves. It assumes not all weights are equally important and skips quantizing the most critical ones. AWQ achieves 95% quality retention, outperforming GPTQ (90%) in many benchmarks [15].
\nGPTQ (Generative Pre-trained Transformer Quantization): A layer-wise post-training method that minimizes output error via Hessian-based optimization. Supports 8, 4, 3, or 2-bit quantization. GPTQ tends to overfit on its calibration data, which can hurt out-of-distribution performance [16].
\nbitsandbytes: Provides 8-bit (LLM.int8()) and 4-bit (NF4) quantization for PyTorch. The 4-bit NF4 format is specifically designed for neural network weights, assuming weights follow a normal distribution and placing quantization levels where most weights are concentrated (near zero) [17].
\nfrom transformers import AutoModelForCausalLM, BitsAndBytesConfig\n\nquantization_config = BitsAndBytesConfig(\n load_in_4bit=True,\n bnb_4bit_quant_type=\"nf4\",\n bnb_4bit_compute_dtype=torch.bfloat16,\n bnb_4bit_use_double_quant=True, # Quantize the quantization constants\n)\n\nmodel = AutoModelForCausalLM.from_pretrained(\n \"meta-llama/Llama-3.1-8B-Instruct\",\n quantization_config=quantization_config,\n)ExLlamaV2 is an inference library optimized for consumer GPUs. Its EXL2 format supports 2, 3, 4, 5, 6, and 8-bit quantization and can mix different precisions within a model to preserve the most important weights [18].
\nExLlamaV2 achieves 56.44 tokens/second on a T4 GPU, providing the highest tokens-per-second compared to GPTQ or llama.cpp. It now supports paged attention via Flash Attention 2.5.7+ and includes dynamic batching with smart prompt caching [18].
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Use Case | Recommended Method |
|---|---|
| GPU inference, high throughput | GPTQ |
| Quality-critical applications | AWQ |
| CPU/Apple devices | GGUF |
| Fine-tuned size control | EXL2 |
The key-value cache stores intermediate attention states during autoregressive generation. Without optimization, KV cache wastes 60-80% of allocated memory through fragmentation and over-allocation [19].
\n![\"Context](\"https://blog.ecitis.org/feeds/figures/local-ai-inferencing-techniques-1.webp\")
PagedAttention, introduced by vLLM, applies virtual memory concepts to KV cache management. Instead of storing each conversation’s KV cache as one contiguous block, PagedAttention breaks it into small, fixed-size “blocks” that can be stored anywhere in memory.
\nThe results: PagedAttention slashed KV cache waste to under 4%, enabling 2-4x throughput improvements [19].
\n# vLLM automatically uses PagedAttention\nfrom vllm import LLM\n\nllm = LLM(\n model=\"meta-llama/Llama-3.1-8B-Instruct\",\n gpu_memory_utilization=0.90,\n max_model_len=32768,\n)Continuous batching operates at the token level. Traditional batching processes requests in fixed groups, wasting compute when some sequences finish before others. Continuous batching walks model layers across a rotating set of in-flight sequences, reusing weight loads across heterogeneous sequence lengths [20].
\nvLLM achieves up to 24x higher throughput than Hugging Face TGI under high-concurrency workloads through continuous batching combined with PagedAttention [21].
\nHierarchical caching: vLLM takes a hierarchical approach to KV caching. It first checks GPU memory, then CPU memory on cache miss, then retrieves from configured KV connectors (like LMCache for distributed caching) [22].
\nFP8 KV cache: Hopper and Blackwell GPUs support native FP8 KV cache, which halves KV cache memory requirements with minimal accuracy impact [19].
\nPrefix caching: Automatic Prefix Caching (APC) detects common prefixes across requests and shares KV cache blocks automatically. Shared prefixes during beam search reduce KV memory usage by up to 55% [23].
\nFlashAttention is an IO-aware attention algorithm that reduces memory bandwidth bottlenecks by computing attention in tiles without materializing the full attention matrix.
\nFlashAttention-2 improved on the original by better parallelizing across thread blocks and reducing synchronization. It achieves 35% utilization on H100 GPUs and speeds up training by 3-5x compared to baseline implementations from Hugging Face, reaching up to 225 TFLOPs/sec per A100 [24].
\nFlashAttention-3 targets Hopper GPUs with three optimizations [25]:
\nPerformance on H100:
\nFlashAttention-3 is up to 2.0x faster than FlashAttention-2. FP8 FlashAttention-3 achieves 2.6x lower numerical error than baseline FP8 attention because intermediate softmax results are kept in FP32 [25].
\n# FlashAttention is integrated into transformers\nfrom transformers import AutoModelForCausalLM\n\nmodel = AutoModelForCausalLM.from_pretrained(\n \"meta-llama/Llama-3.1-8B-Instruct\",\n attn_implementation=\"flash_attention_2\",\n torch_dtype=torch.bfloat16,\n)When models exceed single-GPU memory, sharding distributes parameters across multiple devices.
\nTensor parallelism shards individual layers horizontally across GPUs. The two primary techniques are [26]:
\nWith tensor parallelism across 4 GPUs, a 512 MB weight matrix becomes 128 MB per GPU, a 4x memory reduction for that layer.
\nfrom vllm import LLM\n\n# Tensor parallelism across 4 GPUs on one node\nllm = LLM(\n model=\"meta-llama/Meta-Llama-3.1-70B-Instruct\",\n tensor_parallel_size=4,\n)Tensor parallelism has high communication volume and presents a synchronization point in forward pass. Data exchange occurs over high-speed interconnects like NVLink (600 GB/s) or PCIe (32 GB/s). Interconnect speed critically affects overall performance, making tensor parallelism costly to scale beyond 1 node [27].
\nFor multi-node inference, combine tensor parallelism with pipeline parallelism:
\nfrom vllm import LLM\n\n# Multi-node: 4 GPUs per node, 2 nodes\nllm = LLM(\n model=\"meta-llama/Meta-Llama-3.1-70B-Instruct\",\n tensor_parallel_size=4,\n pipeline_parallel_size=2,\n)Helix Parallelism, introduced in 2025, applies a hybrid execution strategy: KV parallelism during attention to shard KV caches across GPUs, then reuses the same GPUs for tensor parallelism in dense LLMs or TP x Expert Parallel (EP) in MoEs during FFN computation. Compared to conventional approaches, Helix reduces time-to-first-token by up to 1.5x and supports up to 32x larger batches under the same latency budget for DeepSeek-R1 [28].
\nWhen GPU memory is insufficient, offloading parts of the model or KV cache to CPU memory enables inference of larger models.
\n![\"Larger](\"https://blog.ecitis.org/feeds/figures/local-ai-inferencing-techniques-2.webp\")
NEO offloads part of attention compute and KV cache states from GPU to local host CPU, increasing effective GPU batch size and inference throughput. It achieves up to 14%-6.6x throughput gains using two techniques [29]:
\nThe NVLink-C2C connection and unified memory architecture on Grace Hopper enables models to use CPU memory if GPU memory is insufficient without explicit data transfer. When a model loads onto GH200, it uses 96 GB of HBM and accesses 480 GB of LPDDR memory connected to the CPU [30].
\nCPU offloading helps alleviate GPU memory limitations but shifts workload to CPU and increases data movement between CPU and GPU. For CPU-based attention operations, memory bandwidth, not compute power, determines performance. Overall training/inference speed may decrease due to synchronization overhead [30].
\nPrompt caching reuses the model’s intermediate state (KV tensors in attention layers) for prefix tokens rather than recomputing them for each request.
\nDuring prefill, the model builds a KV cache for the entire input. Prompt caching stores this KV cache keyed by the prompt tokens. For subsequent requests sharing the same prefix, the cached KV state is reused, skipping recomputation.
\nAnthropic Claude Sonnet offers prompt caching with up to 90% cost savings and 85% latency reduction for long prompts. OpenAI provides automatic caching with 50% cost savings [31].
\nfrom vllm import LLM\n\nllm = LLM(\n model=\"meta-llama/Llama-3.1-8B-Instruct\",\n enable_prefix_caching=True,\n)vLLM hashes prompt tokens and looks up cache blocks. SGLang uses Radix attention with a radix-tree for prefix caching [31].
\nInference engines handle the actual execution of LLM forward passes. Each engine makes different trade-offs between ease of use, performance, and hardware support. This section covers four engines in detail: TensorRT-LLM (NVIDIA’s production stack), vLLM (the open-source throughput leader), SGLang (structured generation specialist), and llama.cpp (the portable C++ implementation).
\nTensorRT-LLM is NVIDIA’s open-source library for optimizing LLM inference on NVIDIA GPUs. It builds on TensorRT’s graph compilation and kernel optimization capabilities, adding LLM-specific features like in-flight batching, paged KV caching, and multi-GPU parallelism [32].
\nTensorRT-LLM converts model definitions into optimized TensorRT engines through a multi-stage compilation process:
\n1. Graph construction: The Model Definition API assembles a network graph. Each layer maps to TensorRT operations that can later be traversed or transformed [33].
\n2. Pattern matching and fusion: During compilation, TensorRT identifies operation sequences that can be fused into single GPU kernels. For example, a matmul followed by ReLU becomes one kernel without intermediate memory writes. The pattern-matching algorithm identifies fusions automatically, and an advanced kernel compiler converts them to efficient code [34].
\n3. Kernel autotuning: TensorRT automatically selects optimal GPU kernels based on GPU architecture, model configuration, precision, and batch size. The AutoTuner framework (added in 2025) provides custom-op-compatible tuning for operations like fused MoE and NVFP4 linear layers [35].
\n4. Plugin support: Some fusions (like FlashAttention) cannot be discovered automatically because they interleave operations in complex ways. Engineers can explicitly replace graph sections with plugins at compile time [34].
\n# Building a TensorRT-LLM engine\nfrom tensorrt_llm import build\nfrom tensorrt_llm.models import LLaMAForCausalLM\n\n# Load model configuration\nmodel = LLaMAForCausalLM.from_hugging_face(\n \"meta-llama/Llama-3.1-8B-Instruct\",\n dtype=\"float16\"\n)\n\n# Build engine with optimizations\nengine = build(\n model,\n max_batch_size=64,\n max_input_len=2048,\n max_seq_len=4096,\n use_paged_context_fmha=True, # Enable paged KV cache\n)\nengine.save(\"llama-8b-engine\")TensorRT-LLM supports multiple quantization methods, with FP8 recommended as the default for Hopper and Blackwell GPUs [36].
\nFP8 quantization (fp8_pc_pt): Weights are quantized to FP8 per-channel. Activation ranges are calibrated and quantized per-token. FP8 preserves accuracy better than INT8 in most cases [37].
\nINT8 SmoothQuant (int8_sq): Applies smoothing to weights before INT8 channel-wise quantization. Activation ranges are calibrated tensor-wise. Used as a fallback on Ada GPUs [37].
\nThe calibration process:
\nfrom tensorrt_llm.quantization import quantize\nfrom tensorrt_llm.quantization import CalibConfig\n\n# Configure calibration\ncalib_config = CalibConfig(\n calib_dataset=\"cnn_dailymail\",\n calib_batch_size=8,\n calib_max_seq_length=512,\n)\n\n# Quantize to FP8\nquantize(\n model_dir=\"meta-llama/Llama-3.1-8B-Instruct\",\n output_dir=\"llama-8b-fp8\",\n qformat=\"fp8\",\n calib_config=calib_config,\n)In-flight batching (also called continuous batching) eliminates wait times by dynamically managing request execution. Instead of processing fixed batches, TensorRT-LLM merges incoming requests into existing GPU batches, processing context and generation phases together [39].
\nThe scheduler maintains:
\nWhen a sequence completes, its slot immediately becomes available for new requests without waiting for other sequences in the batch.
\nTensorRT-LLM implements paged KV cache with configurable block sizes [40]:
\ntrtllm-build with --tokens_per_block (must be power of 2)KV cache reuse: Pages can be shared by requests with matching prefixes. This reduces time-to-first-token for multi-turn conversations and system prompts. Priority-based eviction (added in 2025) allows specifying priority and duration for token ranges, improving cache hit rates by approximately 20% [41].
\n# Build engine with custom KV cache block size\ntrtllm-build \\\n --checkpoint_dir ./llama-checkpoint \\\n --output_dir ./llama-engine \\\n --tokens_per_block 64 \\\n --use_paged_context_fmha enable \\\n --kv_cache_type pagedTensorRT engines are architecture-specific. An engine built for H100 will not run on A100 [42].
\nSpecifying architectures at build time:
\n# Build for Ada and Hopper only\nmake -C docker release_build CUDA_ARCHS=\"89-real;90-real\"Using TensorRT Cloud for different GPUs:
\n# Build for A100\ntrt-cloud build llm \\\n --src-hf-repo=\"meta-llama/Llama-3.1-8B-Instruct\" \\\n --dtype=\"float16\" \\\n --gpu=\"A100\" \\\n --os=linux\n\n# Build for RTX 3070 (consumer GPU)\ntrt-cloud build llm \\\n --trtllm-checkpoint checkpoint.zip \\\n --gpu RTX3070 \\\n --os windows \\\n --dtype bfloat16GPU architecture codes:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| GPU Family | Compute Capability | CMake Code |
|---|---|---|
| Ampere (A100) | 8.0 | 80-real |
| Ada (RTX 4090, L40) | 8.9 | 89-real |
| Hopper (H100, H200) | 9.0 | 90-real |
| Blackwell (B200, GB200) | 10.0 | 100-real |
Full conversion and serving workflow:
\n# Step 1: Convert HuggingFace model to TensorRT-LLM checkpoint\nfrom tensorrt_llm.models import LLaMAForCausalLM\n\nmodel = LLaMAForCausalLM.from_hugging_face(\n \"meta-llama/Llama-3.1-8B-Instruct\",\n mapping=tensorrt_llm.Mapping(world_size=1, tp_size=1),\n dtype=\"bfloat16\",\n)\nmodel.save_checkpoint(\"./llama-checkpoint\")# Step 2: Build the engine\ntrtllm-build \\\n --checkpoint_dir ./llama-checkpoint \\\n --output_dir ./llama-engine \\\n --gemm_plugin bfloat16 \\\n --max_batch_size 64 \\\n --max_input_len 2048 \\\n --max_seq_len 4096 \\\n --use_paged_context_fmha enable# Step 3: Run inference\nimport tensorrt_llm\nfrom tensorrt_llm.runtime import ModelRunner\n\nrunner = ModelRunner.from_dir(\"./llama-engine\")\n\noutputs = runner.generate(\n batch_input_ids=[[1, 2, 3, 4]], # Tokenized input\n max_new_tokens=256,\n temperature=0.7,\n top_p=0.9,\n)Performance on H100 with FP8: Over 10,000 output tokens/s at peak throughput for 64 concurrent requests, with approximately 100ms time-to-first-token. H100 FP8 achieves up to 4.6x higher max throughput and 4.4x faster TTFT than A100 [43].
\nvLLM is an open-source inference engine that maximizes throughput through PagedAttention and continuous batching. As of June 2025, it has 49,200 GitHub stars and has become the de facto standard for high-throughput LLM serving [44].
\nPagedAttention applies virtual memory concepts to KV cache management. Instead of allocating contiguous memory per request, vLLM divides GPU memory into fixed-size pages (blocks) that can be stored anywhere [45].
\nBlock allocation process:
\nStep-by-step allocation example:
\nInitial state (prompt processed):\n- Logical blocks: [Block 0: 14/16 tokens]\n- Physical mapping: Logical 0 -> Physical 5\n\nAfter generating 2 tokens:\n- Logical blocks: [Block 0: 16/16 tokens (full)]\n- New allocation needed\n\nAfter generating 3rd token:\n- Logical blocks: [Block 0: 16/16], [Block 1: 1/16]\n- Physical mapping: Logical 0 -> Physical 5, Logical 1 -> Physical 12Block size trade-offs: The default is 16 tokens per block. Larger blocks increase kernel parallelism but also increase memory fragmentation. The vLLM authors tested many configurations and found 16 tokens to be a good balance [46].
\nMemory sharing: Sequences with shared prefixes point their block tables to the same physical blocks. This enables prefix caching and reduces memory usage by up to 55% during beam search [47].
\nPerformance impact: Traditional systems waste 60-80% of KV cache memory. PagedAttention reduces waste to under 4%, enabling 2-4x throughput improvements [45].
\n# vLLM automatically uses PagedAttention\nfrom vllm import LLM, SamplingParams\n\nllm = LLM(\n model=\"meta-llama/Llama-3.1-8B-Instruct\",\n gpu_memory_utilization=0.90, # Use 90% of GPU memory for KV cache\n block_size=16, # Tokens per KV block (default)\n swap_space=4, # GB of CPU memory for swapping\n)\n\nsampling_params = SamplingParams(temperature=0.7, max_tokens=256)\noutputs = llm.generate([\"Write a poem about caching:\"], sampling_params)vLLM schedules work at the iteration level, not the request level. The scheduler assembles batches dynamically at each decoding step [48].
\nRequest lifecycle:
\nScheduler architecture:
\n ┌─────────────────┐\n │ API Server │\n └────────┬────────┘\n │\n ┌────────▼────────┐\n │ AsyncLLM │\n └────────┬────────┘\n │\n ┌────────▼────────┐\n │ EngineCore │\n │ │\n │ ┌───────────┐ │\n │ │ Scheduler │ │\n │ └─────┬─────┘ │\n │ │ │\n │ ┌─────▼─────┐ │\n │ │ Executor │ │\n │ └───────────┘ │\n └─────────────────┘Step-level scheduling:
\nChunked prefill: Long prompts are split into smaller chunks to prevent single requests from monopolizing GPU time. With chunked prefill enabled, decode requests are prioritized over prefill to minimize latency for in-progress generations [49].
\nfrom vllm import LLM\n\nllm = LLM(\n model=\"meta-llama/Llama-3.1-8B-Instruct\",\n max_num_seqs=256, # Max concurrent sequences\n max_num_batched_tokens=8192, # Token budget per iteration\n enable_chunked_prefill=True, # Enable chunked prefill\n)vLLM’s Automatic Prefix Caching (APC) detects common prefixes and shares KV cache blocks automatically [50].
\nHow it works:
\nCache hierarchy: vLLM checks GPU memory first, then CPU memory, then external KV connectors like LMCache for distributed caching [51].
\nfrom vllm import LLM\n\nllm = LLM(\n model=\"meta-llama/Llama-3.1-8B-Instruct\",\n enable_prefix_caching=True, # Enable APC\n)\n\n# First request computes and caches the system prompt\nresponse1 = llm.generate([\n \"System: You are a helpful assistant.\\n\\nUser: What is 2+2?\"\n])\n\n# Second request reuses cached system prompt KV\nresponse2 = llm.generate([\n \"System: You are a helpful assistant.\\n\\nUser: What is 3+3?\"\n])vLLM supports multiple speculative decoding methods, with Eagle 3 as the current state-of-the-art [52].
\nSupported methods:
\nEagle 3 performance: Up to 2.5x speedup across diverse scenarios. The Speculators library (v0.3.0, December 2025) provides end-to-end training support for Eagle3 draft models [53].
\nfrom vllm import LLM, SamplingParams\n\n# Using a separate draft model\nllm = LLM(\n model=\"meta-llama/Meta-Llama-3.1-70B-Instruct\",\n speculative_model=\"meta-llama/Llama-3.2-1B-Instruct\",\n num_speculative_tokens=5,\n speculative_draft_tensor_parallel_size=1,\n)\n\n# Using Eagle 3\nllm = LLM(\n model=\"meta-llama/Meta-Llama-3.1-8B-Instruct\",\n speculative_config={\n \"method\": \"eagle\",\n \"model\": \"yuhuili/EAGLE3-LLaMA3.1-Instruct-8B\",\n \"num_speculative_tokens\": 5,\n },\n)Arctic Inference: Snowflake’s Arctic Inference integration achieves 4x faster inference for LLM agents on SWE-Bench tasks and up to 2.8x faster decoding for interactive workloads. It reduces MLP-based proposer latency from 1.47ms/token to 0.47ms/token [54].
\nvLLM supports tensor parallelism (TP), pipeline parallelism (PP), data parallelism (DP), and expert parallelism (EP) [55].
\nTensor parallelism: Shards each layer horizontally across GPUs using column parallelism (split along columns, concatenate results) and row parallelism (split along rows, sum results).
\nfrom vllm import LLM\n\n# Single-node 4-GPU tensor parallelism\nllm = LLM(\n model=\"meta-llama/Meta-Llama-3.1-70B-Instruct\",\n tensor_parallel_size=4,\n)\n\n# Multi-node: 4 GPUs per node, 2 nodes\nllm = LLM(\n model=\"meta-llama/Meta-Llama-3.1-70B-Instruct\",\n tensor_parallel_size=4,\n pipeline_parallel_size=2,\n)\n\n# Combined TP + DP (8 GPUs total)\n# Requires data_parallel_size=4, tensor_parallel_size=2\n# via CLI: --data-parallel-size=4 --tensor-parallel-size=2Why TP within nodes: Tensor parallelism has high communication volume but benefits from fast interconnects. Use TP within nodes (NVLink) and PP across nodes (InfiniBand) when interconnects are slow. With NVLink, TP can extend across nodes [56].
\nChecking interconnect speed:
\nnvidia-smi topo -m\n# Look for NVLink vs PIX (PCIe) connectionsvLLM’s server implements OpenAI’s API specification using FastAPI [57].
\nArchitecture:
\n┌─────────────────────────────────────────────────┐\n│ FastAPI Application │\n│ │\n│ ┌──────────────┐ ┌──────────────────────────┐│\n│ │ /v1/chat │ │ /v1/completions ││\n│ │ completions │ │ ││\n│ └──────┬───────┘ └───────────┬──────────────┘│\n│ │ │ │\n│ ┌──────▼──────────────────────▼──────┐ │\n│ │ OpenAIServingChat │ │\n│ │ OpenAIServingCompletion │ │\n│ │ OpenAIServingTokenization │ │\n│ └──────────────────┬─────────────────┘ │\n│ │ │\n│ ┌──────────────────▼─────────────────┐ │\n│ │ AsyncLLM │ │\n│ └────────────────────────────────────┘ │\n└─────────────────────────────────────────────────┘Request handling:
\n# Start the OpenAI-compatible server\nvllm serve meta-llama/Llama-3.1-8B-Instruct \\\n --host 0.0.0.0 \\\n --port 8000 \\\n --tensor-parallel-size 2\n\n# Use with OpenAI SDK\ncurl http://localhost:8000/v1/chat/completions \\\n -H \"Content-Type: application/json\" \\\n -d '{\n \"model\": \"meta-llama/Llama-3.1-8B-Instruct\",\n \"messages\": [{\"role\": \"user\", \"content\": \"Hello!\"}]\n }'Key parameters for optimizing vLLM performance [58]:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Parameter | Default | Description |
|---|---|---|
max_num_seqs | 256 | Maximum concurrent sequences |
max_num_batched_tokens | 8192 | Token budget per iteration |
gpu_memory_utilization | 0.9 | Fraction of GPU memory for KV cache |
block_size | 16 | Tokens per KV block |
swap_space | 4 | GB of CPU memory for swapping |
enable_chunked_prefill | True | Split long prompts into chunks |
max_model_len | model default | Maximum sequence length |
from vllm import LLM\n\nllm = LLM(\n model=\"meta-llama/Llama-3.1-8B-Instruct\",\n # Memory settings\n gpu_memory_utilization=0.95,\n swap_space=8,\n # Batching settings\n max_num_seqs=512,\n max_num_batched_tokens=16384,\n enable_chunked_prefill=True,\n # Performance settings\n enforce_eager=False, # Use CUDA graphs\n enable_prefix_caching=True,\n)SGLang is a high-performance serving framework that combines RadixAttention for KV cache reuse with a domain-specific language for structured generation. It achieves up to 6.4x higher throughput than baseline systems on structured workloads [59].
\nWhile vLLM’s PagedAttention optimizes memory within individual requests, RadixAttention focuses on maximizing KV cache reuse across multiple requests using a radix tree (compressed prefix tree) [60].
\nPagedAttention: Divides KV cache into fixed-size blocks. Blocks are allocated on demand and freed when sequences complete. Prefix sharing requires explicit cache lookup.
\nRadixAttention: Stores KV cache in a radix tree structure. The tree enables automatic prefix matching, insertion, and LRU eviction. KV cache persists after request completion for potential reuse.
\nKey differences:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Aspect | PagedAttention | RadixAttention |
|---|---|---|
| Data structure | Block tables | Radix tree |
| Prefix matching | Hash lookup | Tree traversal |
| Cache persistence | Cleared after request | Retained in LRU cache |
| Primary optimization | Memory efficiency | KV reuse across calls |
How RadixAttention works:
\nimport sglang as sgl\n\n# RadixAttention automatically reuses KV cache\n@sgl.function\ndef multi_turn_chat(s, turns):\n s += sgl.system(\"You are a helpful assistant.\")\n for user_msg in turns:\n s += sgl.user(user_msg)\n s += sgl.assistant(sgl.gen(\"response\", max_tokens=256))\n\n# KV cache for system prompt is computed once and reused\nruntime = sgl.Runtime(model_path=\"meta-llama/Llama-3.1-8B-Instruct\")\nsgl.set_default_backend(runtime)\n\n# These calls reuse cached system prompt\nresult1 = multi_turn_chat.run(turns=[\"What is Python?\"])\nresult2 = multi_turn_chat.run(turns=[\"What is Rust?\"])SGLang provides a domain-specific language for defining complex LLM programs with branching, parallelism, and constraints [61].
\nCore primitives:
\nimport sglang as sgl\n\n@sgl.function\ndef analyze_code(s, code):\n # Sequential generation\n s += sgl.user(f\"Analyze this code:\\n{code}\")\n s += sgl.assistant(sgl.gen(\"analysis\", max_tokens=500))\n\n # Forking for parallel evaluation\n with s.fork(2) as forks:\n forks[0] += sgl.user(\"Rate the code quality (1-10):\")\n forks[0] += sgl.assistant(sgl.gen(\"quality\", max_tokens=10))\n\n forks[1] += sgl.user(\"Suggest improvements:\")\n forks[1] += sgl.assistant(sgl.gen(\"improvements\", max_tokens=200))\n\n # Select best based on criteria\n s += sgl.select(\"best_response\", forks, criteria=\"quality\")Structured output with JSON schema:
\nfrom pydantic import BaseModel\nimport sglang as sgl\n\nclass CodeReview(BaseModel):\n quality_score: int\n issues: list[str]\n suggestions: list[str]\n\n@sgl.function\ndef structured_review(s, code):\n s += sgl.user(f\"Review this code and provide structured feedback:\\n{code}\")\n s += sgl.assistant(\n sgl.gen(\"review\", max_tokens=500, json_schema=CodeReview.model_json_schema())\n )SGLang implements constrained decoding using compressed finite-state machines (FSM), enabling generation that conforms to regular expressions or JSON schemas [62].
\nHow FSM decoding works:
\nCompressed FSM optimization: Standard FSM decoding processes one token at a time even when transitions are deterministic. SGLang’s compressed FSM collapses chains of singular transitions into single edges [62].
\nimport sglang as sgl\n\n@sgl.function\ndef extract_email(s, text):\n s += sgl.user(f\"Extract the email address from: {text}\")\n # Constrain output to valid email format\n s += sgl.assistant(\n sgl.gen(\"email\", regex=r\"[a-zA-Z0-9._%+-]+@[a-zA-Z0-9.-]+\\.[a-zA-Z]{2,}\")\n )\n\n@sgl.function\ndef generate_json(s, prompt):\n s += sgl.user(prompt)\n # Constrain to valid JSON object\n s += sgl.assistant(\n sgl.gen(\"data\", regex=r'\\{[^{}]*\\}')\n )Jump-forward decoding exploits deterministic sections of constrained output to skip unnecessary LLM forward passes [62].
\nExample: When generating JSON, after a key like \"name\", the next token must be :. Instead of running the LLM to generate :, SGLang inserts it directly.
How it works:
\nPerformance impact: For structured formats with fixed elements, jump-forward decoding can skip 30-50% of generation steps. On JSON decoding benchmarks, this optimization alone delivers up to 1.6x throughput improvement [62].
\nStandard decoding:\n{\"name\" -> LLM -> \":\" -> LLM -> \" \" -> LLM -> \"\\\"\" -> LLM -> \"John\" ...\n\nJump-forward decoding:\n{\"name\" -> INSERT \": \\\"\" -> LLM -> \"John\" ...\n(Skipped 3 LLM calls)SGLang’s runtime optimizes complex multi-call LLM programs through several mechanisms [63]:
\n1. Automatic batching: Multiple sgl.gen() calls across forked branches are batched into single LLM forward passes.
2. KV cache sharing via RadixAttention: Forks share the KV cache of their common prefix. New branches only compute KV for diverging tokens.
\n3. Scheduling optimization: The runtime schedules calls to maximize GPU utilization, interleaving prefill and decode across requests.
\nimport sglang as sgl\n\n@sgl.function\ndef tree_of_thought(s, problem):\n s += sgl.user(f\"Solve: {problem}\")\n\n # Generate 3 candidate solutions in parallel\n with s.fork(3) as candidates:\n for i, c in enumerate(candidates):\n c += sgl.assistant(sgl.gen(f\"solution_{i}\", max_tokens=200))\n\n # Evaluate each solution\n evaluations = []\n for i, c in enumerate(candidates):\n c += sgl.user(\"Rate this solution 1-10:\")\n c += sgl.assistant(sgl.gen(f\"rating_{i}\", max_tokens=5))\n evaluations.append(c)\n\n # Select best\n s += sgl.select(\"best\", evaluations, key=lambda x: int(x[\"rating\"]))Server deployment:
\n# Start SGLang server\npython -m sglang.launch_server \\\n --model-path meta-llama/Llama-3.1-8B-Instruct \\\n --port 30000 \\\n --tp 2\n\n# OpenAI-compatible endpoint\ncurl http://localhost:30000/v1/chat/completions \\\n -H \"Content-Type: application/json\" \\\n -d '{\"model\": \"default\", \"messages\": [{\"role\": \"user\", \"content\": \"Hello\"}]}'llama.cpp is a C/C++ inference engine that prioritizes portability and minimal dependencies. It runs on CPUs, Apple Silicon, NVIDIA GPUs, AMD GPUs, and various accelerators. As of August 2025, it has over 85,000 GitHub stars and 1,200 contributors [64].
\nGGML (Georgi Gerganov Machine Learning) is the tensor library underlying llama.cpp. It provides a portable foundation for neural network operations [65].
\nCore design principles:
\nTensor representation:
\nstruct ggml_tensor {\n enum ggml_type type; // Data type (F32, F16, Q4_K, etc.)\n int n_dims; // Number of dimensions\n int64_t ne[4]; // Number of elements per dimension\n size_t nb[4]; // Stride in bytes per dimension\n void * data; // Pointer to data\n struct ggml_tensor * src[2]; // Source tensors (for operations)\n // ...\n};Computation graph:
\n// Create context\nstruct ggml_context * ctx = ggml_init(params);\n\n// Define tensors\nstruct ggml_tensor * a = ggml_new_tensor_2d(ctx, GGML_TYPE_F32, 768, 768);\nstruct ggml_tensor * b = ggml_new_tensor_2d(ctx, GGML_TYPE_F32, 768, 768);\n\n// Define operation (creates graph node)\nstruct ggml_tensor * c = ggml_mul_mat(ctx, a, b);\n\n// Build computation graph\nstruct ggml_cgraph * graph = ggml_new_graph(ctx);\nggml_build_forward_expand(graph, c);\n\n// Execute on backend\nggml_backend_graph_compute(backend, graph);Backend architecture: GGML’s pluggable backend system enables the same graph to execute on different hardware. Each backend implements a standard interface for memory allocation, data transfer, and kernel execution [66].
\nThe Metal backend provides GPU acceleration on Apple Silicon through hand-optimized compute shaders [67].
\nKey features:
\nMemory management: Metal uses shared buffers that both CPU and GPU can access directly. This is a significant advantage over discrete GPUs that require explicit data transfers.
\n# Build llama.cpp with Metal (default on macOS)\ncmake -B build\ncmake --build build --config Release\n\n# Run with Metal acceleration\n./build/bin/llama-cli \\\n -m llama-3.1-8b-instruct-q4_k_m.gguf \\\n -ngl 99 \\ # Offload all layers to GPU\n -p \"Hello, world!\"Metal performance tuning:
\n# Use flash attention (reduces memory bandwidth)\n./build/bin/llama-cli -m model.gguf -fa\n\n# Adjust batch size for throughput\n./build/bin/llama-cli -m model.gguf -b 512The CUDA backend provides GPU acceleration on NVIDIA hardware with hand-tuned kernels [68].
\nRecent optimizations (2025):
\nCUDA kernel micro-optimizations:
\nmul_mat_id function# Build with CUDA support\ncmake -B build -DGGML_CUDA=ON\ncmake --build build --config Release\n\n# Enable unified memory for larger models\nexport GGML_CUDA_ENABLE_UNIFIED_MEMORY=1\n\n./build/bin/llama-cli \\\n -m llama-3.1-70b-instruct-q4_k_m.gguf \\\n -ngl 99 \\\n -fa # Flash attentionMulti-GPU with ik_llama.cpp: The ik_llama.cpp fork implements tensor parallelism at the GGML graph level (Split Mode Graph). This distributes compute graph nodes across GPUs rather than just assigning layers, achieving 3-4x performance gains over standard multi-GPU methods [69].
\nllama.cpp supports various quantization types with specialized dequantization kernels [70].
\nQuantization type families:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Family | Types | Description |
|---|---|---|
| Type-0 | Q4_0, Q5_0, Q8_0 | Global scale: w = d * q |
| Type-1 | Q4_1, Q5_1 | Scale + minimum: w = d * q + m |
| K-quants | Q4_K, Q5_K, Q6_K | Block-wise with super-blocks of 256 |
| I-quants | IQ4_XS, IQ3_XXS | Importance-based with lookup tables |
K-quant implementation details:
\nK-quants use super-blocks of 256 quantized values, subdivided into blocks of 16 or 32. Each super-block stores:
\nQ4_K_M and Q5_K_M implement mixed precision: most weights use the base precision, but half of attention.wv and feed_forward.w2 tensors use higher precision for better accuracy [71].
# Quantize a model\n./build/bin/llama-quantize \\\n model-f16.gguf \\\n model-q4_k_m.gguf \\\n Q4_K_M\n\n# Quantize with importance matrix for better quality\n./build/bin/llama-quantize \\\n model-f16.gguf \\\n model-q4_k_m.gguf \\\n Q4_K_M \\\n --imatrix imatrix.datAdvanced quantization options:
\n# Mix quantization types for different tensors\n./build/bin/llama-quantize \\\n model-f16.gguf \\\n model-mixed.gguf \\\n Q4_K_M \\\n --output-tensor-type Q8_0 \\\n --token-embedding-type Q8_0Each quantization type has a specific memory layout optimized for efficient dequantization [72].
\nQ4_0 layout (block of 32 weights):
\n[scale: fp16 (2 bytes)] [quants: 16 bytes (32 x 4-bit)]\nTotal: 18 bytes for 32 weights = 4.5 bits/weightQ4_K layout (super-block of 256 weights):
\n[d: fp16] [dmin: fp16] [scales: 12 bytes] [quants: 128 bytes]\n- 8 sub-blocks of 32 weights each\n- Each sub-block has its own 6-bit scale\nTotal: 144 bytes for 256 weights = 4.5 bits/weightQ5_K layout:
\n[d: fp16] [dmin: fp16] [scales: 12 bytes] [qh: 32 bytes] [ql: 128 bytes]\n- qh contains the 5th bit for each weight\n- ql contains lower 4 bits\nTotal: 176 bytes for 256 weights = 5.5 bits/weightDequantization kernels: Each quantization type has optimized dequantization code for each backend. The CUDA kernels use warp-level primitives for efficient parallel dequantization:
\n// Simplified Q4_K dequantization (CUDA)\n__global__ void dequantize_q4_k(const void * src, float * dst) {\n const block_q4_k * block = (const block_q4_k *)src + blockIdx.x;\n\n const float d = __half2float(block->d);\n const float dmin = __half2float(block->dmin);\n\n // Parallel dequantization across warp\n int lane = threadIdx.x % 32;\n uint8_t q = block->qs[lane];\n float scale = d * (block->scales[lane / 32] & 0x3F);\n float min = dmin * (block->scales[lane / 32] >> 4);\n\n dst[lane * 2] = scale * (q & 0xF) - min;\n dst[lane * 2 + 1] = scale * (q >> 4) - min;\n}Each engine optimizes for different points on the latency-throughput curve [73].
\nBenchmark results (Llama 3.1 8B, H100, 1000 ShareGPT prompts):
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Engine | Throughput (tok/s) | TTFT (ms) | Per-token latency (ms) |
|---|---|---|---|
| SGLang | 16,215 | 156 | 4-21 |
| LMDeploy | 16,132 | 142 | 12-35 |
| vLLM | 12,553 | 123 | 8-42 |
| TensorRT-LLM | 10,847 | 187 | 15-28 |
Key observations:
\nAt different concurrency levels (GPT-OSS-120B):
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Concurrency | vLLM (tok/s) | SGLang (tok/s) | TensorRT-LLM (tok/s) |
|---|---|---|---|
| 1 | 892 | 756 | 1,024 |
| 10 | 2,341 | 2,567 | 2,189 |
| 100 | 4,741 | 4,523 | 3,892 |
| Engine | KV Cache Approach | Memory Waste | Max Context (8B model, 24GB) |
|---|---|---|---|
| vLLM | PagedAttention | <4% | 128K tokens |
| SGLang | RadixAttention | <4% | 128K tokens |
| TensorRT-LLM | Paged + Priority eviction | <5% | 128K tokens |
| llama.cpp | Contiguous | 10-20% | 32K tokens |
KV cache quantization support:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Engine | FP8 KV | INT8 KV | NVFP4 KV |
|---|---|---|---|
| TensorRT-LLM | Yes | Yes | Yes (Blackwell) |
| vLLM | Yes | Yes | No |
| SGLang | Yes | Yes | No |
| llama.cpp | Q8_0, Q4_0 | Via type | No |
| Feature | TensorRT-LLM | vLLM | SGLang | llama.cpp |
|---|---|---|---|---|
| Quantization | ||||
| FP8 | Yes (Hopper+) | Yes | Yes | No |
| INT8 | Yes | Yes | Yes | Yes (Q8_0) |
| INT4 | Yes (AWQ) | Yes (AWQ/GPTQ) | Yes | Yes (Q4_K) |
| 2-bit | No | No | No | Yes (Q2_K) |
| Parallelism | ||||
| Tensor parallel | Yes | Yes | Yes | Limited |
| Pipeline parallel | Yes | Yes | Yes | No |
| Expert parallel | Yes | Yes | Yes | No |
| Features | ||||
| Speculative decoding | Yes | Yes (Eagle3) | Yes | Yes |
| Prefix caching | Yes | Yes (APC) | Yes (Radix) | Yes |
| Constrained decoding | No | Yes | Yes (FSM) | Yes (grammar) |
| Multi-LoRA | Yes | Yes | Yes | Yes |
| Vision models | Yes | Yes | Yes | Yes (LLaVA) |
| Deployment | ||||
| OpenAI API | Via Triton | Yes | Yes | Yes (server) |
| NVIDIA GPUs | Yes | Yes | Yes | Yes |
| AMD GPUs | No | Yes (ROCm) | Yes (ROCm) | Yes (HIP) |
| Apple Silicon | No | No | No | Yes (Metal) |
| CPU only | No | No | No | Yes |
TensorRT-LLM:
\nvLLM:
\nSGLang:
\nllama.cpp:
\nFor startup API products:
\nvLLM + OpenAI-compatible server\n- Fast setup, good defaults\n- Scale with tensor parallelism\n- Add prefix caching for repeated promptsFor enterprise on NVIDIA:
\nTensorRT-LLM + Triton Inference Server\n- Maximum throughput per GPU dollar\n- Production-grade monitoring\n- Integration with NVIDIA enterprise supportFor structured outputs:
\nSGLang\n- Native JSON schema support\n- Jump-forward decoding for speed\n- RadixAttention for multi-turn efficiencyFor local/edge deployment:
\nllama.cpp\n- Q4_K_M for balance of quality and size\n- Metal for Apple, CUDA for NVIDIA\n- Works offline with no cloud dependency| Technique | Best for | Hardware requirements |
|---|---|---|
| REAP | MoE models (Mixtral, DeepSeek, Qwen) | Same as original model |
| Speculative decoding | High-latency applications, large target models | GPU memory for both draft and target |
| Q4_K_M quantization | CPU/Apple devices, limited RAM | 4GB+ RAM for 7B models |
| AWQ/GPTQ | GPU inference, quality-sensitive tasks | CUDA GPU |
| PagedAttention | High-concurrency serving | vLLM-compatible GPU |
| FlashAttention-3 | H100/H200 deployments | Hopper architecture |
| Tensor parallelism | Models exceeding single GPU memory | Multiple GPUs with NVLink |
| CPU offloading | Memory-constrained setups | High CPU memory bandwidth |
| Prompt caching | Repeated prompts, RAG, chat systems | Sufficient memory for cache |
These techniques are not mutually exclusive. A production deployment might use:
\nThe optimal combination depends on your specific constraints: available hardware, latency requirements, throughput targets, and accuracy tolerances.
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\n[2] InfoQ - Cactus v1: Cross-Platform LLM Inference on Mobile. https://www.infoq.com/news/2025/12/cactus-on-device-inference/
\n[3] PMC - Tiny Machine Learning and On-Device Inference: A Survey. https://pmc.ncbi.nlm.nih.gov/articles/PMC12115890/
\n[4] Novus - The Rise of Local AI Models: Going Small to Go Big. https://www.novusasi.com/blog/the-rise-of-local-ai-models-going-small-to-go-big
\n[5] Cerebras - REAP: One-Shot Pruning for Trillion-Parameter MoE Models. https://www.cerebras.ai/blog/reap
\n[6] arXiv - REAP the Experts: Why Pruning Prevails for One-Shot MoE compression. https://arxiv.org/abs/2510.13999
\n[7] HuggingFace - Cerebras REAP Collection. https://huggingface.co/collections/cerebras/cerebras-reap
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\n[9] BentoML - Speculative Decoding. https://bentoml.com/llm/inference-optimization/speculative-decoding
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\n[12] PyTorch Blog - Quantization-Aware Training for Large Language Models. https://pytorch.org/blog/quantization-aware-training/
\n[13] llama.cpp GitHub - Quantize README. https://github.com/ggml-org/llama.cpp/blob/master/tools/quantize/README.md
\n[14] Local AI Zone - AI Model Quantization 2025 Guide. https://local-ai-zone.github.io/guides/what-is-ai-quantization-q4-k-m-q8-gguf-guide-2025.html
\n[15] Local AI Master - AWQ vs GPTQ vs GGUF Comparison. https://localaimaster.com/blog/quantization-explained
\n[16] Maarten Grootendorst - Which Quantization Method is Right for You? https://newsletter.maartengrootendorst.com/p/which-quantization-method-is-right
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\n[18] GitHub - ExLlamaV2. https://github.com/turboderp-org/exllamav2
\n[19] arXiv - Efficient Memory Management for LLM Serving with PagedAttention. https://arxiv.org/abs/2309.06180
\n[20] HuggingFace Blog - Continuous batching from first principles. https://huggingface.co/blog/continuous_batching
\n[21] arXiv - Comparative Analysis of LLM Inference Serving Systems. https://arxiv.org/html/2511.17593v1
\n[22] Ceph.io - KV Caching with vLLM, LMCache, and Ceph. https://ceph.io/en/news/blog/2025/vllm-kv-caching/
\n[23] vLLM Documentation - Automatic Prefix Caching. https://docs.vllm.ai/en/stable/design/prefix_caching/
\n[24] GitHub - Dao-AILab/flash-attention. https://github.com/Dao-AILab/flash-attention
\n[25] PyTorch Blog - FlashAttention-3: Fast and Accurate Attention. https://pytorch.org/blog/flashattention-3/
\n[26] Meta Engineering - Scaling LLM Inference: Innovations in Parallelism. https://engineering.fb.com/2025/10/17/ai-research/scaling-llm-inference-innovations-tensor-parallelism-context-parallelism-expert-parallelism/
\n[27] AWS Neuron Documentation - Parallelism Techniques for LLM Inference. https://awsdocs-neuron.readthedocs-hosted.com/en/latest/libraries/nxd-inference/app-notes/parallelism.html
\n[28] arXiv - Helix Parallelism: Rethinking Sharding Strategies. https://arxiv.org/html/2507.07120v1
\n[29] arXiv - NEO: Saving GPU Memory Crisis with CPU Offloading. https://arxiv.org/abs/2411.01142
\n[30] NVIDIA Technical Blog - Accelerate Large-Scale LLM Inference with CPU-GPU Memory Sharing. https://developer.nvidia.com/blog/accelerate-large-scale-llm-inference-and-kv-cache-offload-with-cpu-gpu-memory-sharing/
\n[31] ngrok Blog - Prompt caching: 10x cheaper LLM tokens, but how? https://ngrok.com/blog/prompt-caching/
\n[32] NVIDIA TensorRT-LLM Documentation - Overview. https://nvidia.github.io/TensorRT-LLM/overview.html
\n[33] NVIDIA TensorRT-LLM - Model Definition. https://nvidia.github.io/TensorRT-LLM/architecture/core-concepts.html
\n[34] NVIDIA Technical Blog - Optimizing Inference on LLMs with TensorRT-LLM. https://developer.nvidia.com/blog/optimizing-inference-on-llms-with-tensorrt-llm-now-publicly-available/
\n[35] NVIDIA TensorRT-LLM - Release Notes. https://nvidia.github.io/TensorRT-LLM/release-notes.html
\n[36] NVIDIA Technical Blog - Optimizing LLMs for Performance and Accuracy with Post-Training Quantization. https://developer.nvidia.com/blog/optimizing-llms-for-performance-and-accuracy-with-post-training-quantization/
\n[37] NVIDIA TensorRT-LLM - Numerical Precision. https://nvidia.github.io/TensorRT-LLM/reference/precision.html
\n[38] NVIDIA NeMo Framework - Quantization. https://docs.nvidia.com/nemo-framework/user-guide/latest/nemotoolkit/nlp/quantization.html
\n[39] MarkTechPost - vLLM vs TensorRT-LLM vs HF TGI vs LMDeploy Technical Comparison. https://www.marktechpost.com/2025/11/19/vllm-vs-tensorrt-llm-vs-hf-tgi-vs-lmdeploy-a-deep-technical-comparison-for-production-llm-inference/
\n[40] NVIDIA TensorRT-LLM - KV Cache Reuse. https://nvidia.github.io/TensorRT-LLM/advanced/kv-cache-reuse.html
\n[41] NVIDIA Technical Blog - KV Cache Reuse Optimizations in TensorRT-LLM. https://developer.nvidia.com/blog/introducing-new-kv-cache-reuse-optimizations-in-nvidia-tensorrt-llm/
\n[42] NVIDIA TensorRT-LLM - Building from Source. https://nvidia.github.io/TensorRT-LLM/installation/build-from-source-linux.html
\n[43] BentoML - Best Practices for Tuning TensorRT-LLM. https://www.bentoml.com/blog/tuning-tensor-rt-llm-for-optimal-serving-with-bentoml
\n[44] vLLM Blog - Inside vLLM: Anatomy of a High-Throughput LLM Inference System. https://blog.vllm.ai/2025/09/05/anatomy-of-vllm.html
\n[45] vLLM Documentation - Paged Attention. https://docs.vllm.ai/en/stable/design/paged_attention/
\n[46] Red Hat Developer - How PagedAttention resolves memory waste of LLM systems. https://developers.redhat.com/articles/2025/07/24/how-pagedattention-resolves-memory-waste-llm-systems
\n[47] arXiv - Efficient Memory Management for LLM Serving with PagedAttention. https://arxiv.org/abs/2309.06180
\n[48] Ubicloud Blog - Life of an inference request (vLLM V1). https://www.ubicloud.com/blog/life-of-an-inference-request-vllm-v1
\n[49] vLLM Documentation - Scheduler. https://docs.vllm.ai/en/stable/api/vllm/v1/core/sched/scheduler/
\n[50] vLLM Documentation - Automatic Prefix Caching. https://docs.vllm.ai/en/stable/design/prefix_caching/
\n[51] Ceph.io - KV Caching with vLLM and LMCache. https://ceph.io/en/news/blog/2025/vllm-kv-caching/
\n[52] vLLM Documentation - Speculative Decoding. https://docs.vllm.ai/en/latest/features/spec_decode/
\n[53] vLLM Blog - Speculators v0.3.0. https://blog.vllm.ai/2025/12/13/speculators-v030.html
\n[54] Snowflake Engineering Blog - Fastest Speculative Decoding with Arctic Inference. https://www.snowflake.com/en/engineering-blog/fast-speculative-decoding-vllm-arctic/
\n[55] vLLM Documentation - Parallelism and Scaling. https://docs.vllm.ai/en/stable/serving/parallelism_scaling/
\n[56] Red Hat Developer - Distributed Inference with vLLM. https://developers.redhat.com/articles/2025/02/06/distributed-inference-with-vllm
\n[57] vLLM Documentation - OpenAI-Compatible Server. https://docs.vllm.ai/en/stable/serving/openai_compatible_server/
\n[58] Java Code Geeks - Under the Hood of vLLM: Memory, Scheduling & Batching Strategies. https://www.javacodegeeks.com/2025/10/under-the-hood-of-vllm-memory-scheduling-batching-strategies.html
\n[59] LMSYS Blog - Fast and Expressive LLM Inference with RadixAttention and SGLang. https://lmsys.org/blog/2024-01-17-sglang/
\n[60] SugiV Blog - SGLang Deep Dive: Inside SGLang. https://blog.sugiv.fyi/sglang-deep-dive-inside-sglang
\n[61] SGLang Paper - Efficient Execution of Structured Language Model Programs. https://proceedings.neurips.cc/paper_files/paper/2024/file/724be4472168f31ba1c9ac630f15dec8-Paper-Conference.pdf
\n[62] LMSYS Blog - Fast JSON Decoding with Compressed Finite State Machine. https://lmsys.org/blog/2024-02-05-compressed-fsm/
\n[63] ROCm Blogs - SGLang: Fast Serving Framework on AMD Instinct GPUs. https://rocm.blogs.amd.com/artificial-intelligence/sglang/README.html
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\n[73] AIMultiple Research - LLM Inference Engines: vLLM vs LMDeploy vs SGLang. https://research.aimultiple.com/inference-engines/
", "url": "https://blog.ecitis.org/local-ai-inferencing-techniques/", "title": "Advanced Techniques for Local AI Inferencing", "summary": "Make local models faster and smaller with quantization, speculative decoding, attention optimization, caching, and runtime selection.", "image": "https://blog.ecitis.org/open-graph/local-ai-inferencing-techniques.png", "date_modified": "2026-01-18T00:00:00.000Z", "date_published": "2026-01-18T00:00:00.000Z", "author": { "name": "Aadit Agrawal", "url": "https://blog.ecitis.org/" }, "tags": [ "Inference & Deployment", "Local AI", "Quantization", "Inference" ] }, { "id": "https://blog.ecitis.org/llm-finetuning-guide/", "content_html": "Fine-tuning large language models has become accessible to individual developers and small teams. What once required clusters of expensive GPUs can now run on consumer hardware with the right techniques and tools. This guide covers the practical aspects of fine-tuning: when to do it, how to do it efficiently, and which tools to use.
\n![\"When](\"https://blog.ecitis.org/feeds/figures/llm-finetuning-guide-0.webp\")
Before investing in fine-tuning, consider whether simpler approaches will work. The decision framework looks like this:
\nStart with prompt engineering. If you can solve your problem by crafting better prompts, do that. Prompt engineering takes hours to days and requires no infrastructure changes. It works well for prototypes, MVPs, and cases where the base model’s capabilities are sufficient.
\nUse RAG when you need external knowledge. If your model hallucinates or lacks company-specific information, Retrieval-Augmented Generation is the answer. RAG connects the model to a knowledge base and retrieves relevant context before generating responses. Customer service chatbots and documentation assistants benefit from this approach.1
\nFine-tune when you need behavioral changes. If your system fails on reasoning, planning, or strict policies even with good prompts and retrieval, fine-tuning makes the difference. Use cases include:
\nFine-tuning is also appropriate when you want to distill capabilities from a larger model into a smaller one for faster inference or reduced costs.2
\nThe tradeoff is clear: prompt engineering is a sprint, RAG is a marathon with hydration stations, and fine-tuning is building a Formula 1 car from scratch. Each serves different purposes.
\nFull fine-tuning updates every parameter in the model. For a 7B parameter model, this requires over 28GB of GPU memory just for the weights in full precision. Training consumes additional memory for gradients and optimizer states.
\nThe results can be excellent. Full fine-tuning gives the model maximum flexibility to adapt to new tasks. But the costs are significant:
\nPEFT methods update only a fraction of parameters while keeping the base model frozen. The Hugging Face PEFT library demonstrates this: training bigscience/mt0-large with PEFT touches just 2,359,296 parameters out of 1,231,940,608 total. That is 0.19% of the model.4
\nPerformance remains competitive. With just 200 parameters projected into a space of millions of dimensions, you can achieve 90% of full fine-tuning performance. Some studies show PEFT techniques outperforming full fine-tuning on certain code intelligence tasks.5
\nLow-Rank Adaptation, introduced by Microsoft Research in 2021, freezes the pre-trained weights and injects trainable low-rank decomposition matrices into transformer layers. Instead of updating billions of parameters, you train small adapter matrices amounting to 1-5% of the original parameters.6
\nThe key insight: weight updates during fine-tuning have low intrinsic rank. You can represent them as the product of two smaller matrices (A and B) without losing much information.
\nLoRA has virtually no downsides for most use cases: memory usage is minimal, training is fast, and quality is high. The adapter weights can merge into the base model for inference, eliminating latency overhead.
\nQLoRA extends LoRA by adding 4-bit quantization of the base model. The frozen weights are stored in 4-bit precision while LoRA adapters train in higher precision. Gradients backpropagate through the quantized model.7
\nThree innovations make QLoRA work:
\nQLoRA enables fine-tuning 70B parameter models on hardware that would struggle with 7B models using full fine-tuning. A single A100 80GB handles models that would otherwise require 4-8 GPUs.8
\nThe tradeoff: QLoRA achieves 80-90% of full fine-tuning quality compared to LoRA’s 90-95%. For many applications, this is acceptable given the massive resource savings.
\nAdapters are small neural networks inserted into transformer layers, typically after attention or feed-forward sublayers. They have a bottleneck architecture similar to autoencoders: the input is projected down to a smaller dimension, transformed, then projected back up.9
\nThe original adapter paper showed BERT trained with adapters reached performance comparable to full fine-tuning while training only 3.6% of parameters. More recent work demonstrates that adapter-based PEFT in 7B parameter models can match or exceed the zero-shot performance of 175B parameter models on reasoning tasks.10
\nUnsloth is an open-source library that accelerates LLM fine-tuning. The claims are substantial: 2x faster training with 70% less VRAM compared to standard Hugging Face methods.11
\nThe speed comes from several optimizations:
\nA December 2025 update combined these optimizations to achieve up to 3x faster training throughput with 60% lower VRAM usage.12
\nUnsloth supports the models people actually use:
\nThe library also supports NVIDIA GPUs from Tesla T4 to H100, with portability to AMD and Intel GPUs.13
\nVRAM requirements depend on model size and quantization:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Model | QLoRA 4-bit | LoRA 16-bit |
|---|---|---|
| 7-9B parameters | 6.5GB | 24GB |
| 20B parameters | 14GB | - |
| 70B parameters | 48GB | - |
| 120B parameters | 65GB | - |
These numbers make consumer GPU fine-tuning realistic. A 24GB RTX 4090 handles most 7-9B parameter models with LoRA.
\npip install unslothFor Conda environments:
\nconda create --name unsloth python=3.11 pytorch-cuda=12.1 pytorch cudatoolkit xformers -c pytorch -c nvidia -c xformers -y\nconda activate unsloth\npip install unslothHere is a complete example fine-tuning Llama 3.2 3B with QLoRA:
\nfrom unsloth import FastLanguageModel\nfrom trl import SFTTrainer\nfrom transformers import TrainingArguments\nfrom datasets import load_dataset\n\n# Load model with 4-bit quantization\nmodel, tokenizer = FastLanguageModel.from_pretrained(\n model_name=\"unsloth/Llama-3.2-3B-Instruct-bnb-4bit\",\n max_seq_length=2048,\n load_in_4bit=True,\n)\n\n# Add LoRA adapters\nmodel = FastLanguageModel.get_peft_model(\n model,\n r=16, # LoRA rank\n target_modules=[\"q_proj\", \"k_proj\", \"v_proj\", \"o_proj\",\n \"gate_proj\", \"up_proj\", \"down_proj\"],\n lora_alpha=16,\n lora_dropout=0,\n bias=\"none\",\n use_gradient_checkpointing=\"unsloth\",\n)\n\n# Load and format dataset\ndataset = load_dataset(\"yahma/alpaca-cleaned\", split=\"train\")\n\ndef format_prompt(example):\n instruction = example[\"instruction\"]\n input_text = example[\"input\"]\n output = example[\"output\"]\n\n if input_text:\n text = f\"\"\"### Instruction:\n{instruction}\n\n### Input:\n{input_text}\n\n### Response:\n{output}\"\"\"\n else:\n text = f\"\"\"### Instruction:\n{instruction}\n\n### Response:\n{output}\"\"\"\n return {\"text\": text}\n\ndataset = dataset.map(format_prompt)\n\n# Configure training\ntrainer = SFTTrainer(\n model=model,\n tokenizer=tokenizer,\n train_dataset=dataset,\n dataset_text_field=\"text\",\n max_seq_length=2048,\n args=TrainingArguments(\n per_device_train_batch_size=4,\n gradient_accumulation_steps=4,\n warmup_steps=10,\n max_steps=100,\n learning_rate=2e-4,\n fp16=True,\n logging_steps=10,\n output_dir=\"outputs\",\n ),\n)\n\n# Train\ntrainer.train()\n\n# Save adapter weights\nmodel.save_pretrained(\"lora_model\")\n\n# For inference\nFastLanguageModel.for_inference(model)\ninputs = tokenizer(\"### Instruction:\\nWrite a haiku about coding.\\n\\n### Response:\\n\",\n return_tensors=\"pt\").to(\"cuda\")\noutputs = model.generate(**inputs, max_new_tokens=64)\nprint(tokenizer.decode(outputs[0], skip_special_tokens=True))The FastLanguageModel.for_inference() call enables Unsloth’s optimized inference mode, providing 2x speedup over standard generation.14
Tinker is a training API from Mira Murati’s Thinking Machines Lab, released in October 2025. The premise is handling infrastructure complexity while giving you control over algorithms and data.15
\nYou write simple Python scripts with four core functions, and Tinker runs them across distributed GPUs. The platform handles:
\nResearch teams at Princeton, Stanford, and Berkeley use Tinker for their work. The platform supports models up to 1 trillion parameters, including Kimi K2.16
\nTinker supports the full range of post-training methods:
\nSupervised fine-tuning for instruction following and task adaptation
\nPreference learning with a three-stage RLHF pipeline:
\nPrompt distillation for internalizing long instructions into model weights
\nMulti-agent optimization for training models to interact with other models or themselves
\nThe Tinker cookbook on GitHub contains examples for these approaches.17
\nThinking Machines published research on LoRA hyperparameters. Key finding: when picking optimal learning rates for each setting, training progresses almost identically for LoRAs with different sizes and full fine-tuning. Similar results appeared on AIME 2024 and AIME 2025 evaluations.18
\nTRL (Transformer Reinforcement Learning) is Hugging Face’s library for post-training foundation models. It supports supervised fine-tuning, GRPO (Group Relative Policy Optimization), DPO (Direct Preference Optimization), and PPO.19
\nKey features:
\nThe GRPOTrainer implements the algorithm used to train DeepSeek’s R1. It is more memory-efficient than PPO.20
\nfrom trl import SFTTrainer, DPOTrainer, GRPOTrainer\nfrom transformers import AutoModelForCausalLM, AutoTokenizer\n\n# Basic SFT example\nmodel = AutoModelForCausalLM.from_pretrained(\"meta-llama/Llama-3.2-3B\")\ntokenizer = AutoTokenizer.from_pretrained(\"meta-llama/Llama-3.2-3B\")\n\ntrainer = SFTTrainer(\n model=model,\n train_dataset=dataset,\n tokenizer=tokenizer,\n)\ntrainer.train()The combination of TRL and PEFT enables fine-tuning gpt-neo-x 20B (40GB in bfloat16) on a 24GB consumer GPU.21
\nAxolotl is Modal’s recommended framework for beginners. It offers flexibility, ease of use, and rapid adoption of new models and techniques.22
\n2025 brought significant updates:
\nAxolotl supports multi-GPU training, unlike Unsloth. If you have a large GPU cluster, Axolotl is the better choice.23
\nConfiguration uses YAML files that span the full pipeline: dataset preprocessing, training, evaluation, quantization, and inference.
\nbase_model: meta-llama/Llama-3.2-3B-Instruct\nmodel_type: AutoModelForCausalLM\ntokenizer_type: AutoTokenizer\n\nload_in_4bit: true\nadapter: qlora\nlora_r: 32\nlora_alpha: 16\nlora_dropout: 0.05\nlora_target_modules:\n - q_proj\n - v_proj\n - k_proj\n - o_proj\n - gate_proj\n - down_proj\n - up_proj\n\ndatasets:\n - path: yahma/alpaca-cleaned\n type: alpaca\n\nsequence_len: 4096\nmicro_batch_size: 2\ngradient_accumulation_steps: 4\nnum_epochs: 3\nlearning_rate: 2e-4\noptimizer: adamw_torch\nlr_scheduler: cosine\n\noutput_dir: ./outputsLLaMA-Factory provides a WebUI for fine-tuning, making it accessible to non-technical users. The toolkit supports over 100 models and received the ACL 2024 best paper award.24
\n2025 additions include:
\nTraining approaches span supervised fine-tuning, continuous pre-training, and preference tuning (PPO, DPO, KTO, ORPO). The toolkit integrates FlashAttention-2, DeepSpeed, GaLore, and BAdam optimization.25
\nInference uses OpenAI-style API, Gradio UI, or CLI with vLLM or SGLang workers.
\ntorchtune is PyTorch’s native post-training library. It offers composable building blocks without framework abstractions.26
\nIf you prefer working directly with PyTorch, torchtune is the choice. The library is designed with memory efficiency in mind, with recipes tested on consumer GPUs with 24GB VRAM.
\nFeatures include:
\n# Single-device LoRA fine-tuning\ntune run lora_finetune_single_device --config llama3_2/3B_lora_single_device\n\n# Knowledge distillation\ntune run knowledge_distillation_distributed --config qwen2/1.5B_to_0.5B_KD_lora_distributedTwo formats dominate: Alpaca and ShareGPT.
\nAlpaca format suits instruction-following tasks. Each example has three fields:
\n{\n \"instruction\": \"Write a function to calculate factorial\",\n \"input\": \"5\",\n \"output\": \"def factorial(n):\\n if n <= 1:\\n return 1\\n return n * factorial(n-1)\\n\\nprint(factorial(5)) # 120\"\n}The original Alpaca dataset contains 52,000 instruction-output pairs generated by GPT-4 from 175 seed instructions.27
\nShareGPT format handles multi-turn conversations:
\n{\n \"conversations\": [\n { \"role\": \"user\", \"content\": \"What is the capital of France?\" },\n { \"role\": \"assistant\", \"content\": \"Paris is the capital of France.\" },\n { \"role\": \"user\", \"content\": \"What is its population?\" },\n {\n \"role\": \"assistant\",\n \"content\": \"Paris has a population of about 2.1 million in the city proper, and over 12 million in the metropolitan area.\"\n }\n ]\n}ShareGPT supports additional roles: human, GPT, observation, and function. Human and observation entries appear in odd positions; GPT and function in even positions.28
\nUse Alpaca for single-turn question-and-answer tasks. Use ShareGPT for conversational chatbots, especially those with function calling.
\nQuality matters more than quantity. A few thousand well-curated examples often outperform hundreds of thousands of noisy ones.
\nCheck for:
\nClean datasets exist for common starting points. AlpacaDataCleaned removes problematic examples from the original Alpaca dataset.29
\nWhen human-labeled data is scarce, synthetic data fills the gap. Teacher-student distillation uses a larger model (like GPT-4) to generate training examples for a smaller model.30
\nStrategies for synthetic data:
\nQuestion-answer generation: Use retrieval-augmented pipelines to generate QA pairs from documents. A multi-stage framework with retriever, generator, and refinement model produces higher quality than single-pass generation.
\nActive synthetic data generation: Generate data iteratively based on the current model’s weaknesses. Simple selection criteria from active learning perform well.
\nRephrasing: Augment existing questions with paraphrased versions. This is robust even with weaker augmentation models.
\nChallenges exist. LLMs can hallucinate, producing incorrect labels or logically inconsistent examples. Validate synthetic data before training, either through automated checks or sampling for human review.31
\nRed Hat’s SDG Hub provides an open-source toolkit for synthetic data workflows.
\nThe learning rate is the most important hyperparameter. For LoRA and QLoRA fine-tuning:
\nLearning rate of 1e-4 has become standard for LoRA fine-tuning. Reducing it further helps with occasional training loss instabilities.32
\nUse warmup steps (5-10% of total steps) and a scheduler. Cosine annealing works well for most cases.
\nMaximize tokens-per-second without running out of memory. Use gradient accumulation to achieve larger effective batch sizes.
\nA common configuration:
\nper_device_train_batch_size = 4\ngradient_accumulation_steps = 4\n# Effective batch size = 16Larger batch sizes provide more stable gradients but require more memory. If you hit OOM errors, reduce per-device batch size and increase gradient accumulation.
\nRank (r): Controls the capacity of the adapter. Common values are 8, 16, 32, or 64.
\nAlpha: Scaling factor for LoRA weights. Recommendations vary:
\nIf rank is 16, start with alpha of 16 or 32. Adjust based on results.
\nTarget modules: Apply LoRA to both attention and MLP layers for best results. The minimal set is attention projections (q, k, v, o). Adding gate_proj, up_proj, and down_proj improves performance.
\nFor instruction-based datasets, 1-3 epochs work well. Training beyond 3 epochs offers diminishing returns and increases overfitting risk.34
\nMonitor validation loss. If it starts increasing while training loss continues decreasing, you are overfitting.
\nNo single benchmark suffices. Select benchmarks relevant to your use case:
\nInstruction following: MT-Bench, AlpacaEval, LMSYS Chatbot Arena
\nReasoning: GSM8K (math), MATH (competition math), BBH (Big Bench Hard), DROP
\nKnowledge: MMLU (15,000+ multiple-choice questions across 57 subjects)
\nTruthfulness: TruthfulQA (800+ questions across 38 subjects)
\nDomain-specific: Build custom evaluation sets matching your deployment scenario35
\nMT-Bench introduced using LLMs to evaluate other LLMs. GPT-4 serves as a judge to score response quality. This scales better than human evaluation for rapid iteration.36
\nOpen-source alternatives exist. Prometheus is a Llama-2-Chat model fine-tuned on 100K GPT-4 feedback examples. It achieves comparable evaluation capabilities when given appropriate reference materials.37
\nUse AlpacaEval to compute win-rate deltas before and after fine-tuning. Track metrics on held-out validation sets throughout training.
\nTools for experiment tracking:
\nAfter fine-tuning, merge LoRA weights into the base model for inference:
\n# With Unsloth\nmodel.save_pretrained_merged(\"merged_model\", tokenizer, save_method=\"merged_16bit\")\n\n# Or save as GGUF for llama.cpp\nmodel.save_pretrained_gguf(\"model_gguf\", tokenizer, quantization_method=\"q4_k_m\")Quantization reduces model size for deployment. Common options:
\nFor production inference, use vLLM, SGLang, or TGI rather than Hugging Face Transformers directly.
\nStatic benchmarks alone will not catch performance drift. Monitor in production:
\nRetrain periodically as your data distribution shifts.
\nRAG vs. Fine-tuning vs. Prompt Engineering: The Complete Guide to AI Optimization ↩
\nFine-Tuning, RAG, or Prompt Engineering? LLM Decision Guide - Moveo.AI ↩
\nExploring Parameter-Efficient Fine-Tuning Techniques for Code Generation - ACM ↩
\nParameter-Efficient Fine-Tuning of Large Language Models with LoRA and QLoRA - Analytics Vidhya ↩
\nFine-Tuning Infrastructure: LoRA, QLoRA, and PEFT at Scale - Introl ↩
\nBest GenAI Fine-Tuning Tools for 2025 - LoRA vs QLoRA - Index.dev ↩
\nLLM-Adapters: An Adapter Family for Parameter-Efficient Fine-Tuning - ACL Anthology ↩
\nUnsloth AI Makes LLM Fine-Tuning 3x Faster and 90% Cheaper - Medium ↩
\nThinking Machines makes its Tinker AI fine-tuning service generally available - SiliconANGLE ↩
\nThinking Machines’ New Tinker API Makes It Easier To Fine-Tune Models On Many GPUs - DeepLearning.AI ↩
\nFine-tuning 20B LLMs with RLHF on a 24GB consumer GPU - Hugging Face ↩
\nFine-Tuning LLMs with LLaMA-Factory: Guidance and Insights - Usee.ai ↩
\nSynthetic Data Generation Strategies for Fine-Tuning LLMs - Scale ↩
\nSynthetic Data: Benefits and Techniques for LLM Fine-Tuning in 2025 - Label Your Data ↩
\nPractical Tips for Finetuning LLMs Using LoRA - Sebastian Raschka ↩
\nLoRA fine-tuning Hyperparameters Guide - Unsloth Documentation ↩
\nLLM Evaluation: Benchmarks to Test Model Quality in 2025 - Label Your Data ↩
\n30 LLM evaluation benchmarks and how they work - Evidently AI ↩
\nVision Language Models (VLMs) combine computer vision and natural language processing into unified systems capable of reasoning about images and text together. Unlike earlier approaches that treated vision and language as separate pipelines, modern VLMs learn joint representations that enable tasks like visual question answering, image captioning, document analysis, and multimodal reasoning.
\nThis article covers VLM architecture from the ground up: how vision encoders transform pixels into tokens, how projection layers bridge modalities, and why inference is more complex than text-only LLMs. We also survey popular architectures, quantization strategies, and practical deployment options.
\nVLMs accept images (or videos) alongside text prompts and generate text responses. Concrete capabilities include:
\nThe key shift from earlier vision models: VLMs use the same interface as chat LLMs. You prompt them with natural language, optionally include images, and receive text back. This unified interface simplifies integration into existing LLM-based applications.
\nMost VLMs follow a three-component architecture:
\n![\"Vision](\"https://blog.ecitis.org/feeds/figures/vision-language-models-0.webp\")
Let’s examine each component.
\nThe vision encoder transforms raw pixels into a sequence of feature vectors. The dominant architecture is the Vision Transformer (ViT), introduced by Dosovitskiy et al. in 2020.
\nHow ViT works:
\nPatch extraction: The input image is divided into fixed-size patches (typically 14x14 or 16x16 pixels). A 224x224 image with 14x14 patches yields 256 patches.
\nLinear embedding: Each patch is flattened and projected through a linear layer to create patch embeddings. For a 14x14x3 patch (588 values), this produces a vector of dimension D (commonly 768, 1024, or 1152).
\nPosition encoding: Since transformers have no inherent notion of spatial order, learnable position embeddings are added to each patch embedding. These encode the patch’s location in the original image grid.
\nCLS token: A learnable classification token is prepended to the sequence. After processing, this token aggregates global image information.
\nTransformer blocks: The sequence passes through standard transformer encoder layers (self-attention + feedforward). Each patch attends to all other patches, capturing global context.
\nThe output is a sequence of vectors: one per patch plus the CLS token. For a 224x224 image with 14x14 patches, you get 257 vectors (256 patches + 1 CLS).
\nPopular vision encoders:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Encoder | Parameters | Patch Size | Output Dim | Notes |
|---|---|---|---|---|
| CLIP ViT-L/14 | 428M | 14x14 | 1024 | Trained on 400M image-text pairs |
| SigLIP-So400m | 400M | 14x14 | 1152 | Sigmoid loss, better small-batch training |
| InternViT-6B | 6B | 14x14 | 3200 | Scaled up for InternVL |
| DaViT | 88M | varies | varies | Dual attention (spatial + channel) |
CLIP vs SigLIP
\nCLIP (Contrastive Language-Image Pre-training) trains vision and text encoders jointly using a contrastive softmax loss. Given a batch of N image-text pairs, the model learns to match correct pairs while pushing incorrect pairs apart. The softmax normalization requires computing similarities across the entire batch.
\nSigLIP (Sigmoid Loss for Language-Image Pre-training) replaces softmax with sigmoid loss that operates on each image-text pair independently. This removes the need for cross-batch normalization, enabling:
\nSigLIP 2 (February 2025) adds self-distillation, masked prediction, and captioning objectives for improved localization and dense prediction.
\nVision encoders and language models operate in different representation spaces. The projection layer bridges this gap by transforming vision features into the language model’s embedding space.
\nSimple linear projection (LLaVA 1.0)
\nThe original LLaVA used a single linear layer:
\nvision_features: [num_patches, 1024]\n │\n ▼\n Linear(1024, 4096)\n │\n ▼\nprojected_features: [num_patches, 4096]This works but limits how much the vision representation can be transformed.
\nMLP projection (LLaVA 1.5+)
\nLLaVA 1.5 switched to a two-layer MLP with GELU activation:
\nvision_features: [num_patches, 1024]\n │\n ▼\n Linear(1024, 4096)\n │\n ▼\n GELU\n │\n ▼\n Linear(4096, 4096)\n │\n ▼\nprojected_features: [num_patches, 4096]The additional nonlinearity allows more complex transformations and improved multimodal alignment.
\nCross-attention adapters (Flamingo-style)
\nSome architectures use cross-attention layers that let language model tokens attend to vision features rather than concatenating them directly. This approach:
\nPerceiver resampler
\nPerceiver-based adapters use a fixed number of learnable query tokens that cross-attend to the variable-length vision features, producing a constant number of output tokens regardless of image resolution.
\nThe language model processes the projected vision tokens alongside text tokens. Any decoder-only transformer can serve this role:
\nThe vision tokens are typically inserted at the position of special <image> tokens in the input. The language model then processes the combined sequence autoregressively, attending to both vision and text tokens.
Token sequence structure:
\n[BOS] [system prompt tokens] [image_tok_1] [image_tok_2] ... [image_tok_N] [user prompt tokens] [assistant response]The number of image tokens depends on the vision encoder’s output and any token compression applied.
\nStandard language models use 1D position encoding. Images require 2D spatial information. VLMs handle this in several ways:
\nFlattened 1D positions: Simply assign positions sequentially to flattened patch tokens. Row-major order: patch (0,0) gets position 0, patch (0,1) gets position 1, etc.
\nSeparate 2D position embeddings in ViT: The vision encoder learns its own 2D-aware position embeddings during pretraining. These spatial relationships are then encoded into the patch representations before projection.
\nM-RoPE (Multimodal Rotary Position Embedding): Qwen2-VL introduced M-RoPE, which encodes position information across text, images, and videos in a unified way. For images, it captures both spatial positions and temporal positions for video frames.
\nVariable Visual Position Encoding (V2PE): InternVL3 uses smaller, more flexible position increments for visual tokens, improving long-context understanding.
\nLLaVA (Large Language and Vision Assistant) established the dominant paradigm: frozen CLIP encoder + MLP projector + instruction-tuned LLM.
\nLLaVA 1.0 (2023)
\nLLaVA 1.5 (2023)
\nLLaVA-NeXT / LLaVA 1.6 (2024)
\nTraining process:
\nStage 1: Projector pretraining
\nStage 2: Full fine-tuning
\nAlibaba’s Qwen vision models introduced Naive Dynamic Resolution, processing images at their native resolution rather than forcing fixed sizes.
\nKey innovations:
\nDynamic resolution: Images are converted to a variable number of visual tokens based on their actual dimensions. A small icon might use 256 tokens; a high-resolution document might use 4096+.
\nM-RoPE (Multimodal RoPE): Unified position encoding for text, images, and video. Enables the model to understand:
\n2D RoPE in ViT: The vision encoder itself uses 2D rotary position embeddings, enabling better adaptation to varying resolutions during inference.
\nModel sizes: 2B, 8B, 72B parameters.
\nQwen2.5-VL improvements (2025):
\nOpenGVLab’s InternVL scales both vision and language components, with InternViT reaching 6B parameters.
\nArchitecture: ViT-MLP-LLM paradigm with a pixel unshuffle operation that reduces visual tokens to 1/4 of the original count.
\nInternVL 2.5 / 3.0 (2025):
\nInternVL 3.5 (August 2025):
\nGoogle’s PaliGemma combines SigLIP with Gemma in a straightforward architecture.
\nComponents:
\nResolution and tokens:
\nPaliGemma 2 (2024):
\nGemma 3 with vision (2025):
\nMicrosoft’s Phi-3 Vision packs vision capabilities into a 4.2B parameter model.
\nArchitecture:
\nSpecifications:
\nStrengths:
\nPhi-3.5 Vision:
\nCogVLM introduces a Visual Expert module that adds trainable parameters to the language model specifically for processing vision features.
\nArchitecture difference: Instead of just projecting vision features into the LLM’s input space, CogVLM adds parallel QKV matrices and MLP layers for visual tokens at each transformer layer.
\nStandard layer:\n text_tokens ──▶ [QKV + MLP] ──▶ output\n\nCogVLM layer:\n text_tokens ──▶ [QKV_text + MLP_text] ──┐\n ├──▶ output\n image_tokens ──▶ [QKV_vision + MLP_vision]──┘Benefits:
\nScale: CogVLM-17B has 10B vision parameters + 7B language parameters.
\nCogVLM2 (2024):
\nMicrosoft’s Florence-2 takes a different approach: a unified sequence-to-sequence model for all vision tasks.
\nArchitecture:
\nKey insight: All vision tasks (detection, segmentation, captioning, grounding) can be formulated as sequence-to-sequence problems. The model outputs text, including coordinate tokens for localization tasks.
\nTraining data: FLD-5B dataset with 5.4B annotations across 126M images (boxes, masks, captions, grounding).
\nPerformance: Despite small size, Florence-2 outperforms much larger models on zero-shot captioning. On COCO, the 232M model (score: 133) and 771M model (score: 135.6) both beat DeepMind’s 80B Flamingo.
\nVLM inference presents challenges beyond text-only LLMs.
\nText inputs have predictable token counts (roughly 4 chars per token). Images vary wildly:
\nDynamic resolution models like Qwen2-VL convert resolution directly to token count. Memory and compute scale accordingly.
\nA batch of requests might contain:
\nThis variability complicates batching and memory allocation.
\nBefore the vision encoder runs, images require preprocessing:
\nThis preprocessing happens on CPU and can bottleneck throughput when image counts are high.
\nHigh-resolution images consume memory at multiple stages:
\nFor a 72B model processing a high-res document, the image tokens alone can consume several GB of KV cache memory.
\nText-only continuous batching works because all tokens are homogeneous. With images:
\nvLLM’s solution: Hybrid parallelism where the vision encoder uses data parallelism (each GPU processes different images) while the LLM uses tensor parallelism. This avoids synchronization overhead during vision encoding.
\nPrefix caching: vLLM V1 supports prefix caching for multimodal inputs, so repeated images don’t require re-encoding.
\nQuantization reduces model size and speeds inference by using lower-precision weights and activations.
\nVision encoders are often left at higher precision because:
\nHowever, for edge deployment, encoder quantization matters. Research shows:
\nStandard LLM quantization techniques apply:
\nThe language model dominates parameter count (e.g., 72B LLM vs 400M vision encoder), so LLM quantization provides most of the size/speed benefits.
\nQ-VLM (NeurIPS 2024) proposes cross-layer dependency mining for VLM quantization. Rather than quantizing layer-by-layer, it considers how quantization errors propagate through the full vision-language pipeline.
\nResults: 2.78x memory compression, 1.44x speedup on 13B LLaVA without performance degradation.
\nMBQ (Modality-Balanced Quantization) (CVPR 2025) observes that language modules are more sensitive to quantization than vision modules. Their approach:
\nQuantization affects different VLM capabilities differently:
\nRecommendation: Benchmark your specific use case. A model that’s fine for photo captioning might fail on document analysis when heavily quantized.
\nThe most straightforward approach for experimentation.
\nLLaVA example:
\nimport torch\nfrom transformers import AutoProcessor, LlavaForConditionalGeneration\nfrom PIL import Image\nimport requests\n\nmodel_id = \"llava-hf/llava-1.5-7b-hf\"\n\n# Load model and processor\nmodel = LlavaForConditionalGeneration.from_pretrained(\n model_id,\n torch_dtype=torch.float16,\n device_map=\"auto\"\n)\nprocessor = AutoProcessor.from_pretrained(model_id)\n\n# Prepare inputs\nurl = \"https://upload.wikimedia.org/wikipedia/commons/thumb/3/3a/Cat03.jpg/1200px-Cat03.jpg\"\nimage = Image.open(requests.get(url, stream=True).raw)\n\nconversation = [\n {\n \"role\": \"user\",\n \"content\": [\n {\"type\": \"image\"},\n {\"type\": \"text\", \"text\": \"What animal is in this image? Describe it briefly.\"}\n ]\n }\n]\n\nprompt = processor.apply_chat_template(conversation, add_generation_prompt=True)\ninputs = processor(images=image, text=prompt, return_tensors=\"pt\").to(model.device)\n\n# Generate\noutput = model.generate(**inputs, max_new_tokens=100, do_sample=False)\nresponse = processor.decode(output[0], skip_special_tokens=True)\nprint(response)Qwen2-VL example:
\nfrom transformers import Qwen2VLForConditionalGeneration, AutoProcessor\nfrom PIL import Image\n\nmodel = Qwen2VLForConditionalGeneration.from_pretrained(\n \"Qwen/Qwen2-VL-7B-Instruct\",\n torch_dtype=\"auto\",\n device_map=\"auto\"\n)\nprocessor = AutoProcessor.from_pretrained(\"Qwen/Qwen2-VL-7B-Instruct\")\n\n# Qwen2-VL supports dynamic resolution\nimage = Image.open(\"document.png\") # Any resolution\n\nmessages = [\n {\n \"role\": \"user\",\n \"content\": [\n {\"type\": \"image\", \"image\": image},\n {\"type\": \"text\", \"text\": \"Extract all text from this document.\"}\n ]\n }\n]\n\ntext = processor.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)\ninputs = processor(text=[text], images=[image], return_tensors=\"pt\").to(model.device)\n\ngenerated_ids = model.generate(**inputs, max_new_tokens=512)\noutput = processor.batch_decode(generated_ids, skip_special_tokens=True)Pipeline API (simpler):
\nfrom transformers import pipeline\n\npipe = pipeline(\"image-text-to-text\", model=\"llava-hf/llava-1.5-7b-hf\")\n\noutput = pipe(\n images=\"https://example.com/image.jpg\",\n text=\"Describe this image in detail.\",\n max_new_tokens=200\n)llama.cpp supports vision models via the mmproj (multimodal projector) architecture.
Installation:
\n# macOS\nbrew install llama.cpp\n\n# Or build from source\ngit clone https://github.com/ggml-org/llama.cpp\ncd llama.cpp && makeDownload model and projector:
\n# Pre-quantized models available from ggml-org\n# https://huggingface.co/collections/ggml-org/multimodal-ggufs\n\n# Example: Qwen2.5-VL-7B\nwget https://huggingface.co/ggml-org/Qwen2.5-VL-7B-Instruct-GGUF/resolve/main/qwen2.5-vl-7b-instruct-q4_k_m.gguf\nwget https://huggingface.co/ggml-org/Qwen2.5-VL-7B-Instruct-GGUF/resolve/main/qwen2.5-vl-7b-instruct-vision.ggufRun inference:
\n./llama-mtmd-cli \\\n -m qwen2.5-vl-7b-instruct-q4_k_m.gguf \\\n --mmproj qwen2.5-vl-7b-instruct-vision.gguf \\\n -p \"Describe this image:\" \\\n --image photo.jpgSupported models:
\nLimitations: Currently supports static images only. Video processing is not yet implemented.
\nvLLM provides high-throughput VLM serving with continuous batching.
\nInstallation:
\npip install vllmOffline inference:
\nfrom vllm import LLM, SamplingParams\nfrom vllm.multimodal import MultiModalData\n\nllm = LLM(model=\"llava-hf/llava-1.5-7b-hf\")\n\nprompt = \"USER: <image>\\nWhat is in this image?\\nASSISTANT:\"\nsampling_params = SamplingParams(temperature=0.0, max_tokens=256)\n\n# Single image\noutputs = llm.generate(\n {\n \"prompt\": prompt,\n \"multi_modal_data\": {\"image\": \"path/to/image.jpg\"}\n },\n sampling_params\n)\nprint(outputs[0].outputs[0].text)Server deployment:
\n# Start server\npython -m vllm.entrypoints.openai.api_server \\\n --model llava-hf/llava-1.5-7b-hf \\\n --chat-template llava\n\n# Query via OpenAI-compatible API\ncurl http://localhost:8000/v1/chat/completions \\\n -H \"Content-Type: application/json\" \\\n -d '{\n \"model\": \"llava-hf/llava-1.5-7b-hf\",\n \"messages\": [\n {\n \"role\": \"user\",\n \"content\": [\n {\"type\": \"text\", \"text\": \"What is in this image?\"},\n {\"type\": \"image_url\", \"image_url\": {\"url\": \"https://example.com/image.jpg\"}}\n ]\n }\n ]\n }'Performance tuning:
\n# Use data parallelism for vision encoder\npython -m vllm.entrypoints.openai.api_server \\\n --model Qwen/Qwen2-VL-7B-Instruct \\\n --mm-encoder-tp-mode data\n\n# Limit image tokens to control memory\n--limit-mm-per-prompt '{\"image\": 2048}'Supported models (partial list):
\nOllama provides the simplest local VLM experience.
\nInstallation:
\n# macOS/Linux\ncurl -fsSL https://ollama.com/install.sh | sh\n\n# Or download from ollama.comRun vision models:
\n# Pull a vision model\nollama pull llava\n\n# Interactive mode\nollama run llava\n>>> [paste image path or URL]\n>>> What's in this image?\n\n# Or with llava-phi3 (smaller, faster)\nollama pull llava-phi3\nollama run llava-phi3API usage:
\nimport ollama\n\nresponse = ollama.chat(\n model='llava',\n messages=[{\n 'role': 'user',\n 'content': 'Describe this image',\n 'images': ['./photo.jpg']\n }]\n)\nprint(response['message']['content'])Available vision models on Ollama:
\nllava (7B and 13B variants)llava-phi3 (3.8B, faster)bakllavamoondream (smaller, 1.8B)from transformers import Qwen2VLForConditionalGeneration, AutoProcessor\nfrom PIL import Image\n\nmodel = Qwen2VLForConditionalGeneration.from_pretrained(\n \"Qwen/Qwen2-VL-7B-Instruct\",\n torch_dtype=\"auto\",\n device_map=\"auto\"\n)\nprocessor = AutoProcessor.from_pretrained(\"Qwen/Qwen2-VL-7B-Instruct\")\n\n# Use high resolution for documents\nimage = Image.open(\"invoice.png\")\n\nmessages = [{\n \"role\": \"user\",\n \"content\": [\n {\"type\": \"image\", \"image\": image},\n {\"type\": \"text\", \"text\": \"Extract all text from this invoice. Format as structured data.\"}\n ]\n}]\n\ninputs = processor(\n text=processor.apply_chat_template(messages, tokenize=False, add_generation_prompt=True),\n images=[image],\n return_tensors=\"pt\"\n).to(model.device)\n\noutput = model.generate(**inputs, max_new_tokens=1024)\nprint(processor.decode(output[0], skip_special_tokens=True))from transformers import LlavaNextProcessor, LlavaNextForConditionalGeneration\nimport torch\nfrom PIL import Image\n\nmodel = LlavaNextForConditionalGeneration.from_pretrained(\n \"llava-hf/llava-v1.6-mistral-7b-hf\",\n torch_dtype=torch.float16,\n device_map=\"auto\"\n)\nprocessor = LlavaNextProcessor.from_pretrained(\"llava-hf/llava-v1.6-mistral-7b-hf\")\n\nimage1 = Image.open(\"product_v1.jpg\")\nimage2 = Image.open(\"product_v2.jpg\")\n\nprompt = \"[INST] <image>\\n<image>\\nCompare these two product images. What are the differences? [/INST]\"\n\ninputs = processor(prompt, [image1, image2], return_tensors=\"pt\").to(model.device)\noutput = model.generate(**inputs, max_new_tokens=300)\nprint(processor.decode(output[0], skip_special_tokens=True))# Using Florence-2 for detailed chart understanding\nfrom transformers import AutoProcessor, AutoModelForCausalLM\nfrom PIL import Image\n\nmodel = AutoModelForCausalLM.from_pretrained(\n \"microsoft/Florence-2-large\",\n torch_dtype=\"auto\",\n trust_remote_code=True\n).to(\"cuda\")\nprocessor = AutoProcessor.from_pretrained(\"microsoft/Florence-2-large\", trust_remote_code=True)\n\nimage = Image.open(\"sales_chart.png\")\n\n# Florence-2 uses task-specific prompts\nprompt = \"<MORE_DETAILED_CAPTION>\"\n\ninputs = processor(text=prompt, images=image, return_tensors=\"pt\").to(\"cuda\")\ngenerated_ids = model.generate(\n input_ids=inputs[\"input_ids\"],\n pixel_values=inputs[\"pixel_values\"],\n max_new_tokens=512,\n num_beams=3\n)\nresult = processor.batch_decode(generated_ids, skip_special_tokens=True)[0]\nprint(result)from vllm import LLM, SamplingParams\nimport os\n\nllm = LLM(\n model=\"Qwen/Qwen2-VL-7B-Instruct\",\n limit_mm_per_prompt={\"image\": 1}\n)\n\nsampling_params = SamplingParams(temperature=0.0, max_tokens=256)\n\n# Prepare batch of requests\nimage_dir = \"./images\"\nrequests = []\nfor img_file in os.listdir(image_dir):\n if img_file.endswith(('.jpg', '.png')):\n requests.append({\n \"prompt\": \"USER: <image>\\nDescribe this image briefly.\\nASSISTANT:\",\n \"multi_modal_data\": {\"image\": os.path.join(image_dir, img_file)}\n })\n\n# Process batch\noutputs = llm.generate(requests, sampling_params)\n\nfor i, output in enumerate(outputs):\n print(f\"Image {i}: {output.outputs[0].text}\")Modern research in machine learning and artificial intelligence requires understanding the fundamental architecture that powers computational workloads. Whether you’re training large language models, processing computer vision tasks, or running complex simulations, Graphics Processing Units (GPUs) have become the backbone of high-performance computing. This comprehensive guide explores the intricate details of GPU architecture, parallel computing paradigms, and practical implementation strategies for research-grade applications on state-of-the-art hardware.
\nUnderstanding these concepts isn’t just about knowing how to run code faster. It’s about fundamentally rethinking how we approach computational problems. The shift from CPU-centric to GPU-accelerated computing enabled breakthroughs in deep learning, scientific computing, and data processing that were previously impossible.
\nAt its most basic level, a computer is a sophisticated machine that transforms electrical signals into meaningful computation through the interaction of hardware and software components. The hardware provides the physical substrate (transistors, memory cells, interconnects) while software provides the logical instructions that orchestrate these components into useful work.
\nThis duality is crucial to understand because modern GPU programming requires intimate knowledge of both layers. Unlike traditional CPU programming where hardware details are often abstracted away, GPU programming demands awareness of the underlying architecture to achieve optimal performance.
\nThe hardware layer consists of:
\nThe software layer encompasses:
\nComputation at the hardware level involves the coordinated execution of billions of transistor switches that can be in one of two states: conducting (1) or non-conducting (0). These binary states form the foundation of all digital computation through Boolean algebra and logical operations.
\nThe basic computation cycle follows the von Neumann architecture:
\nThis cycle repeats billions of times per second, with modern processors executing multiple instructions simultaneously through techniques like:
\nCentral Processing Units (CPUs) were historically designed around the principle of sequential execution: processing one instruction at a time in a predetermined order. This design philosophy prioritizes:
\nA typical CPU core contains:
\n┌─────────────────────────────────────────────────────┐\n│ CPU Core Architecture │\n├─────────────────────────────────────────────────────┤\n│ Instruction Fetch Unit │\n│ ├─ Branch Predictor │\n│ ├─ Instruction Cache (L1-I) │\n│ └─ Prefetch Buffer │\n├─────────────────────────────────────────────────────┤\n│ Decode and Dispatch │\n│ ├─ Instruction Decoder │\n│ ├─ Micro-op Cache │\n│ └─ Reorder Buffer │\n├─────────────────────────────────────────────────────┤\n│ Execution Units │\n│ ├─ Integer ALU (multiple units) │\n│ ├─ Floating Point Unit │\n│ ├─ Vector/SIMD Unit │\n│ └─ Load/Store Unit │\n├─────────────────────────────────────────────────────┤\n│ Memory Subsystem │\n│ ├─ L1 Data Cache │\n│ ├─ L2 Cache │\n│ └─ Memory Management Unit │\n└─────────────────────────────────────────────────────┘The introduction of multi-core CPUs represented the first major shift toward parallelism in mainstream computing. However, each core still operates on the same serial computing principles; they provide multiple independent serial processors on the same chip.
\nMulti-core systems excel at:
\nHowever, they face fundamental limitations:
\nimport multiprocessing as mp\nimport numpy as np\nimport time\n\ndef cpu_intensive_task(data_chunk):\n \"\"\"Simulate CPU-intensive computation on a data chunk\"\"\"\n result = np.zeros_like(data_chunk)\n for i in range(len(data_chunk)):\n # Simulate complex computation\n result[i] = np.sin(data_chunk[i]) * np.cos(data_chunk[i]) + np.sqrt(abs(data_chunk[i]))\n return result\n\ndef serial_computation(data):\n \"\"\"Traditional serial computation\"\"\"\n start_time = time.time()\n result = cpu_intensive_task(data)\n end_time = time.time()\n return result, end_time - start_time\n\ndef parallel_computation(data, num_cores):\n \"\"\"Multi-core parallel computation\"\"\"\n start_time = time.time()\n\n # Split data into chunks\n chunk_size = len(data) // num_cores\n chunks = [data[i:i + chunk_size] for i in range(0, len(data), chunk_size)]\n\n # Process chunks in parallel\n with mp.Pool(processes=num_cores) as pool:\n results = pool.map(cpu_intensive_task, chunks)\n\n # Combine results\n final_result = np.concatenate(results)\n end_time = time.time()\n return final_result, end_time - start_time\n\n# Example usage\nif __name__ == \"__main__\":\n # Generate test data\n data_size = 1000000\n test_data = np.random.random(data_size) * 100\n\n # Compare serial vs parallel performance\n num_cores = mp.cpu_count()\n print(f\"Available CPU cores: {num_cores}\")\n\n # Serial execution\n serial_result, serial_time = serial_computation(test_data)\n print(f\"Serial execution time: {serial_time:.2f} seconds\")\n\n # Parallel execution\n parallel_result, parallel_time = parallel_computation(test_data, num_cores)\n print(f\"Parallel execution time: {parallel_time:.2f} seconds\")\n print(f\"Speedup: {serial_time / parallel_time:.2f}x\")![\"CPU](\"https://blog.ecitis.org/feeds/figures/understanding-gpus-0.webp\")
Graphics Processing Units represent a fundamental departure from CPU design philosophy. Instead of optimizing for serial performance with complex control logic, GPUs are designed around the principle of massive parallelism: executing thousands of simple operations simultaneously.
\nThis architectural difference stems from their original purpose: rendering graphics. Graphics operations are inherently parallel; each pixel can be processed independently, and the same operations (like texture sampling, lighting calculations, or color transformations) are applied to millions of pixels simultaneously.
\nThe key philosophical differences between CPU and GPU design:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Aspect | CPU | GPU |
|---|---|---|
| Design Goal | Minimize latency for complex tasks | Maximize throughput for simple tasks |
| Core Count | Few (2-64) powerful cores | Thousands of simple cores |
| Memory | Large caches, complex hierarchy | High bandwidth, simpler hierarchy |
| Control Logic | Complex branch prediction, out-of-order | Simple, in-order execution |
| Best For | Sequential code, complex branching | Parallel code, regular patterns |
Understanding the distinction between SIMD (Single Instruction, Multiple Data) and SIMT (Single Instruction, Multiple Threads) is crucial for effective GPU programming.
\nSIMD represents the traditional approach to data parallelism found in CPU vector units (like AVX-512) and some GPU architectures. In SIMD:
\nimport numpy as np\n\ndef demonstrate_simd_concept():\n \"\"\"Demonstrate SIMD-style operations using NumPy\"\"\"\n # Create large arrays\n a = np.random.random(1000000)\n b = np.random.random(1000000)\n\n # SIMD-style operation: same instruction applied to all elements\n # This gets compiled to vectorized instructions (AVX, SSE, etc.)\n result = a + b # Single instruction, multiple data elements\n\n # Element-wise operations are also SIMD-friendly\n complex_result = np.sin(a) * np.cos(b) + np.sqrt(np.abs(a * b))\n\n return result, complex_result\n\n# Contrast with scalar operations\ndef scalar_equivalent():\n \"\"\"Show what the SIMD operation looks like in scalar form\"\"\"\n a = np.random.random(1000000)\n b = np.random.random(1000000)\n result = np.zeros(1000000)\n\n # This would be much slower - one operation at a time\n for i in range(len(a)):\n result[i] = a[i] + b[i]\n\n return resultSIMT, pioneered by NVIDIA’s CUDA architecture, provides a more flexible approach:
\n// CUDA kernel demonstrating SIMT execution\n__global__ void simt_vector_add(float* a, float* b, float* c, int n) {\n // Each thread computes its unique index\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n\n // Boundary check - threads can have different execution paths\n if (tid < n) {\n c[tid] = a[tid] + b[tid];\n\n // Conditional execution - some threads may execute this, others may not\n if (a[tid] > 0.5f) {\n c[tid] *= 2.0f;\n }\n }\n // Threads that fail the boundary check essentially become idle\n}GPUs implement parallelism through a hierarchical execution model:
\nGrid (entire kernel launch)\n├─ Block 0\n│ ├─ Warp 0 (threads 0-31)\n│ ├─ Warp 1 (threads 32-63)\n│ └─ ...\n├─ Block 1\n│ ├─ Warp 0 (threads 0-31)\n│ └─ ...\n└─ ...Warp Execution Model:
\nHere’s a detailed CUDA example showing warp behavior:
\n#include <cuda_runtime.h>\n#include <stdio.h>\n\n__global__ void demonstrate_warp_behavior(int* data, int n) {\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n int warp_id = tid / 32;\n int lane_id = tid % 32;\n\n if (tid < n) {\n // All threads in warp execute this\n data[tid] = tid;\n\n // Warp divergence example\n if (lane_id < 16) {\n // First half of warp executes this\n data[tid] *= 2;\n } else {\n // Second half executes this\n data[tid] *= 3;\n }\n // Warp reconverges here\n\n data[tid] += warp_id;\n }\n}\n\n// Host code\nint main() {\n const int n = 1024;\n int* h_data = new int[n];\n int* d_data;\n\n // Allocate GPU memory\n cudaMalloc(&d_data, n * sizeof(int));\n\n // Launch kernel with appropriate grid/block dimensions\n dim3 block_size(256); // 8 warps per block\n dim3 grid_size((n + block_size.x - 1) / block_size.x);\n\n demonstrate_warp_behavior<<<grid_size, block_size>>>(d_data, n);\n\n // Copy result back\n cudaMemcpy(h_data, d_data, n * sizeof(int), cudaMemcpyDeviceToHost);\n\n // Print results for first few elements\n for (int i = 0; i < 64; i++) {\n printf(\"Thread %d: %d\\n\", i, h_data[i]);\n }\n\n delete[] h_data;\n cudaFree(d_data);\n return 0;\n}The motivation for parallel computing extends far beyond graphics:
\nGraphics and Video Processing:
\nMatrix Operations:\nModern AI workloads are fundamentally based on linear algebra operations that are highly parallelizable:
\nCode Example: GPU vs CPU Matrix & Convolution Operations (PyTorch)import torch\nimport time\n\ndef demonstrate_gpu_matrix_operations():\n \"\"\"Show the performance difference between CPU and GPU matrix operations\"\"\"\n\n # Create large matrices\n size = 4096\n cpu_a = torch.randn(size, size, dtype=torch.float32)\n cpu_b = torch.randn(size, size, dtype=torch.float32)\n\n # GPU versions\n gpu_a = cpu_a.cuda()\n gpu_b = cpu_b.cuda()\n\n # CPU matrix multiplication\n start_time = time.time()\n cpu_result = torch.matmul(cpu_a, cpu_b)\n cpu_time = time.time() - start_time\n\n # GPU matrix multiplication\n torch.cuda.synchronize() # Ensure clean timing\n start_time = time.time()\n gpu_result = torch.matmul(gpu_a, gpu_b)\n torch.cuda.synchronize() # Wait for GPU to complete\n gpu_time = time.time() - start_time\n\n print(f\"Matrix size: {size}x{size}\")\n print(f\"CPU time: {cpu_time:.4f} seconds\")\n print(f\"GPU time: {gpu_time:.4f} seconds\")\n print(f\"Speedup: {cpu_time / gpu_time:.2f}x\")\n\n # Verify results are equivalent (within floating point precision)\n difference = torch.max(torch.abs(cpu_result - gpu_result.cpu()))\n print(f\"Maximum difference: {difference:.2e}\")\n\n# More complex example: Convolution operations\ndef demonstrate_convolution_parallelism():\n \"\"\"Show how convolution operations benefit from GPU parallelism\"\"\"\n import torch.nn.functional as F\n\n # Create sample input (batch_size=32, channels=256, height=64, width=64)\n input_tensor = torch.randn(32, 256, 64, 64)\n # Convolution kernel (out_channels=512, in_channels=256, kernel_size=3x3)\n kernel = torch.randn(512, 256, 3, 3)\n\n # CPU convolution\n start_time = time.time()\n cpu_output = F.conv2d(input_tensor, kernel, padding=1)\n cpu_time = time.time() - start_time\n\n # GPU convolution\n input_gpu = input_tensor.cuda()\n kernel_gpu = kernel.cuda()\n\n torch.cuda.synchronize()\n start_time = time.time()\n gpu_output = F.conv2d(input_gpu, kernel_gpu, padding=1)\n torch.cuda.synchronize()\n gpu_time = time.time() - start_time\n\n print(f\"\\nConvolution operation:\")\n print(f\"Input shape: {input_tensor.shape}\")\n print(f\"Output shape: {cpu_output.shape}\")\n print(f\"CPU time: {cpu_time:.4f} seconds\")\n print(f\"GPU time: {gpu_time:.4f} seconds\")\n print(f\"Speedup: {cpu_time / gpu_time:.2f}x\")\n\nif __name__ == \"__main__\":\n demonstrate_gpu_matrix_operations()\n demonstrate_convolution_parallelism()Modern computing systems implement a sophisticated memory hierarchy designed to balance capacity, speed, and cost. Understanding this hierarchy is crucial for writing efficient GPU code.
\nSystem RAM serves as the primary storage for data and programs currently in use. Key characteristics:
\nimport psutil\nimport numpy as np\n\ndef analyze_system_memory():\n \"\"\"Analyze system memory characteristics\"\"\"\n memory = psutil.virtual_memory()\n\n print(\"System Memory Analysis:\")\n print(f\"Total RAM: {memory.total / (1024**3):.2f} GB\")\n print(f\"Available RAM: {memory.available / (1024**3):.2f} GB\")\n print(f\"Used RAM: {memory.used / (1024**3):.2f} GB\")\n print(f\"Memory utilization: {memory.percent:.1f}%\")\n\n # Demonstrate memory bandwidth measurement\n def measure_memory_bandwidth():\n \"\"\"Rough estimate of memory bandwidth\"\"\"\n size = 100_000_000 # 100M floats = ~400MB\n data = np.random.random(size).astype(np.float32)\n\n import time\n # Memory copy operation\n start_time = time.time()\n copy = np.copy(data) # This tests memory bandwidth\n end_time = time.time()\n\n bytes_transferred = size * 4 * 2 # 4 bytes per float, read + write\n bandwidth = bytes_transferred / (end_time - start_time) / (1024**3)\n print(f\"Estimated memory bandwidth: {bandwidth:.2f} GB/s\")\n\n measure_memory_bandwidth()\n\nanalyze_system_memory()Cache memory provides ultra-fast access to frequently used data through a hierarchy of increasingly smaller but faster storage levels:
\nL1 Cache:
\nL2 Cache:
\nL3 Cache:
\n#include <chrono>\n#include <iostream>\n#include <vector>\n#include <random>\n\nclass CacheAnalyzer {\npublic:\n static void demonstrate_cache_hierarchy() {\n // Test different data sizes to show cache effects\n std::vector<size_t> sizes = {\n 1024, // 4KB - fits in L1\n 64 * 1024, // 256KB - fits in L2\n 4 * 1024 * 1024, // 16MB - fits in L3\n 64 * 1024 * 1024 // 256MB - exceeds cache\n };\n\n for (size_t size : sizes) {\n double time = measure_access_time(size);\n std::cout << \"Size: \" << size * sizeof(int) / 1024 << \" KB, \"\n << \"Time per access: \" << time << \" ns\" << std::endl;\n }\n }\n\nprivate:\n static double measure_access_time(size_t size) {\n std::vector<int> data(size);\n\n // Initialize with random values\n std::random_device rd;\n std::mt19937 gen(rd());\n for (size_t i = 0; i < size; i++) {\n data[i] = gen() % size;\n }\n\n // Measure random access time\n volatile int sum = 0; // Prevent optimization\n auto start = std::chrono::high_resolution_clock::now();\n\n size_t iterations = 1000000;\n for (size_t i = 0; i < iterations; i++) {\n sum += data[i % size];\n }\n\n auto end = std::chrono::high_resolution_clock::now();\n auto duration = std::chrono::duration_cast<std::chrono::nanoseconds>(end - start);\n\n return static_cast<double>(duration.count()) / iterations;\n }\n};VRAM is specialized high-bandwidth memory attached directly to the GPU:
\nimport torch\nimport time\n\ndef analyze_vram_characteristics():\n \"\"\"Analyze GPU memory characteristics\"\"\"\n if not torch.cuda.is_available():\n print(\"CUDA not available\")\n return\n\n # Get GPU memory info\n device = torch.cuda.current_device()\n gpu_props = torch.cuda.get_device_properties(device)\n\n print(f\"GPU: {gpu_props.name}\")\n print(f\"Total VRAM: {gpu_props.total_memory / (1024**3):.2f} GB\")\n print(f\"Multiprocessors: {gpu_props.multi_processor_count}\")\n\n # Measure memory bandwidth\n def measure_gpu_bandwidth():\n \"\"\"Measure GPU memory bandwidth\"\"\"\n size = 100_000_000 # 100M floats\n\n # Allocate GPU memory\n data = torch.randn(size, device='cuda', dtype=torch.float32)\n\n # Warm up\n for _ in range(10):\n copy = data.clone()\n\n torch.cuda.synchronize()\n\n # Measure bandwidth\n start_time = time.time()\n iterations = 50\n for _ in range(iterations):\n copy = data.clone()\n torch.cuda.synchronize()\n end_time = time.time()\n\n bytes_per_iteration = size * 4 * 2 # read + write\n total_bytes = bytes_per_iteration * iterations\n bandwidth = total_bytes / (end_time - start_time) / (1024**3)\n\n print(f\"Measured GPU memory bandwidth: {bandwidth:.2f} GB/s\")\n\n # Compare with theoretical peak\n # This is approximate and varies by GPU\n theoretical_peak = {\n 'A100': 1555, # GB/s\n 'V100': 900,\n 'RTX 4090': 1008,\n 'RTX 3090': 936\n }\n\n for gpu_name, peak in theoretical_peak.items():\n if gpu_name.lower() in gpu_props.name.lower():\n efficiency = (bandwidth / peak) * 100\n print(f\"Theoretical peak: {peak} GB/s\")\n print(f\"Achieved efficiency: {efficiency:.1f}%\")\n break\n\n measure_gpu_bandwidth()\n\nanalyze_vram_characteristics()Modern SSDs provide fast persistent storage crucial for handling large datasets:
\nTraditional magnetic storage still used for large, infrequently accessed datasets:
\nimport os\nimport time\nimport tempfile\n\ndef benchmark_storage():\n \"\"\"Benchmark storage performance characteristics\"\"\"\n\n def benchmark_write_read(file_path, size_mb):\n \"\"\"Benchmark write and read performance\"\"\"\n data = b'0' * (1024 * 1024) # 1MB chunk\n\n # Write benchmark\n start_time = time.time()\n with open(file_path, 'wb') as f:\n for _ in range(size_mb):\n f.write(data)\n write_time = time.time() - start_time\n\n # Read benchmark\n start_time = time.time()\n with open(file_path, 'rb') as f:\n while f.read(1024 * 1024):\n pass\n read_time = time.time() - start_time\n\n # Clean up\n os.remove(file_path)\n\n write_speed = size_mb / write_time\n read_speed = size_mb / read_time\n\n return write_speed, read_speed\n\n # Test with different file sizes\n test_sizes = [100, 1000] # 100MB, 1GB\n\n for size in test_sizes:\n with tempfile.NamedTemporaryFile(delete=False) as tmp:\n write_speed, read_speed = benchmark_write_read(tmp.name, size)\n\n print(f\"File size: {size} MB\")\n print(f\"Write speed: {write_speed:.2f} MB/s\")\n print(f\"Read speed: {read_speed:.2f} MB/s\")\n print(\"-\" * 40)\n\nbenchmark_storage()Understanding the historical development of GPUs provides crucial context for their current capabilities and future directions.
\nThe early 1990s marked the beginning of consumer 3D graphics acceleration. Before this era, all graphics rendering was performed by the CPU, limiting the complexity and realism of computer graphics.
\nKey developments:
\nThe 3DFX Voodoo Graphics card revolutionized PC gaming by providing hardware acceleration for 3D graphics operations:
\nTechnical specifications:
\n// Example of early 3D graphics programming (pseudo-Glide API)\nvoid render_triangle() {\n // Set rendering state\n grColorCombine(GR_COMBINE_FUNCTION_SCALE_OTHER,\n GR_COMBINE_FACTOR_ONE,\n GR_COMBINE_LOCAL_NONE,\n GR_COMBINE_OTHER_TEXTURE);\n\n // Define triangle vertices\n GrVertex vertices[3] = {\n {100.0f, 100.0f, 0.5f, 1.0f, 0.0f, 0.0f}, // x, y, z, s, t, w\n {200.0f, 100.0f, 0.5f, 1.0f, 1.0f, 0.0f},\n {150.0f, 200.0f, 0.5f, 1.0f, 0.5f, 1.0f}\n };\n\n // Render the triangle\n grDrawTriangle(&vertices[0], &vertices[1], &vertices[2]);\n}This period saw the integration of 2D and 3D graphics capabilities:
\nNVIDIA RIVA 128:
\nATI Rage Pro:
\nForward-thinking researchers recognized that graphics hardware could be useful for non-graphics computations:
\nEarly GPGPU techniques:
\n1996: Stanford BrookGPU - Stream/Kernel Programming Model
\nStanford researchers developed BrookGPU, one of the first systematic approaches to general-purpose GPU programming. This pioneering work introduced the concept of stream processing - treating data as streams that flow through computational kernels.
\n// BrookGPU example: vector addition using stream processing\nkernel void vector_add(float a<>, float b<>, out float result<>) {\n result = a + b; // Applied to entire streams element-wise\n}\n\nvoid main() {\n float input_stream_a<1000>; // Stream of 1000 floats\n float input_stream_b<1000>; // Stream of 1000 floats\n float output_stream<1000>; // Output stream\n\n // Initialize streams\n streamRead(input_stream_a, host_array_a);\n streamRead(input_stream_b, host_array_b);\n\n // Execute kernel on GPU\n vector_add(input_stream_a, input_stream_b, output_stream);\n\n // Read results back\n streamWrite(output_stream, host_result_array);\n}NVIDIA’s introduction of CUDA (Compute Unified Device Architecture) marked the true beginning of mainstream GPGPU computing. For the first time, developers could write GPU code using familiar C/C++ syntax instead of graphics shaders.
\nCUDA’s revolutionary features:
\n// CUDA example: Matrix multiplication (naive implementation)\n__global__ void matrix_multiply(float* A, float* B, float* C, int N) {\n // Calculate thread's position in the grid\n int row = blockIdx.y * blockDim.y + threadIdx.y;\n int col = blockIdx.x * blockDim.x + threadIdx.x;\n\n if (row < N && col < N) {\n float sum = 0.0f;\n\n // Compute dot product of row and column\n for (int k = 0; k < N; k++) {\n sum += A[row * N + k] * B[k * N + col];\n }\n\n C[row * N + col] = sum;\n }\n}\n\n// Host code\nint main() {\n const int N = 1024;\n size_t size = N * N * sizeof(float);\n\n // Allocate host memory\n float *h_A, *h_B, *h_C;\n h_A = (float*)malloc(size);\n h_B = (float*)malloc(size);\n h_C = (float*)malloc(size);\n\n // Allocate device memory\n float *d_A, *d_B, *d_C;\n cudaMalloc(&d_A, size);\n cudaMalloc(&d_B, size);\n cudaMalloc(&d_C, size);\n\n // Initialize matrices (omitted for brevity)\n\n // Copy data to GPU\n cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);\n cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);\n\n // Launch kernel\n dim3 blockSize(16, 16);\n dim3 gridSize((N + blockSize.x - 1) / blockSize.x,\n (N + blockSize.y - 1) / blockSize.y);\n\n matrix_multiply<<<gridSize, blockSize>>>(d_A, d_B, d_C, N);\n\n // Copy result back\n cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);\n\n // Cleanup\n cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);\n free(h_A); free(h_B); free(h_C);\n\n return 0;\n}The Khronos Group introduced OpenCL (Open Computing Language) to provide vendor-neutral parallel computing across different hardware platforms.
\nOpenCL advantages:
\n// OpenCL example: Vector addition\nconst char* kernel_source = R\"(\n__kernel void vector_add(__global const float* A,\n __global const float* B,\n __global float* C) {\n int idx = get_global_id(0);\n C[idx] = A[idx] + B[idx];\n}\n)\";\n\nint main() {\n const int ARRAY_SIZE = 1024;\n\n // Get platform and device info\n cl_platform_id platform_id;\n cl_device_id device_id;\n clGetPlatformIDs(1, &platform_id, NULL);\n clGetDeviceIDs(platform_id, CL_DEVICE_TYPE_GPU, 1, &device_id, NULL);\n\n // Create context and command queue\n cl_context context = clCreateContext(NULL, 1, &device_id, NULL, NULL, NULL);\n cl_command_queue queue = clCreateCommandQueue(context, device_id, 0, NULL);\n\n // Create and build program\n cl_program program = clCreateProgramWithSource(context, 1, &kernel_source, NULL, NULL);\n clBuildProgram(program, 1, &device_id, NULL, NULL, NULL);\n\n // Create kernel\n cl_kernel kernel = clCreateKernel(program, \"vector_add\", NULL);\n\n // Create buffers\n size_t size = ARRAY_SIZE * sizeof(float);\n cl_mem buffer_A = clCreateBuffer(context, CL_MEM_READ_ONLY, size, NULL, NULL);\n cl_mem buffer_B = clCreateBuffer(context, CL_MEM_READ_ONLY, size, NULL, NULL);\n cl_mem buffer_C = clCreateBuffer(context, CL_MEM_WRITE_ONLY, size, NULL, NULL);\n\n // Set kernel arguments\n clSetKernelArg(kernel, 0, sizeof(cl_mem), &buffer_A);\n clSetKernelArg(kernel, 1, sizeof(cl_mem), &buffer_B);\n clSetKernelArg(kernel, 2, sizeof(cl_mem), &buffer_C);\n\n // Execute kernel\n size_t global_work_size = ARRAY_SIZE;\n clEnqueueNDRangeKernel(queue, kernel, 1, NULL, &global_work_size, NULL, 0, NULL, NULL);\n\n // Read result\n float* result = (float*)malloc(size);\n clEnqueueReadBuffer(queue, buffer_C, CL_TRUE, 0, size, result, 0, NULL, NULL);\n\n // Cleanup (omitted for brevity)\n return 0;\n}As deep learning gained momentum, NVIDIA recognized the need for highly optimized library implementations of common operations.
\ncuBLAS (CUDA Basic Linear Algebra Subprograms):
\n#include <cublas_v2.h>\n\nvoid optimized_matrix_multiply() {\n const int M = 2048, N = 2048, K = 2048;\n const float alpha = 1.0f, beta = 0.0f;\n\n // Allocate GPU memory\n float *d_A, *d_B, *d_C;\n cudaMalloc(&d_A, M * K * sizeof(float));\n cudaMalloc(&d_B, K * N * sizeof(float));\n cudaMalloc(&d_C, M * N * sizeof(float));\n\n // Create cuBLAS handle\n cublasHandle_t handle;\n cublasCreate(&handle);\n\n // Perform matrix multiplication: C = alpha * A * B + beta * C\n // Note: cuBLAS assumes column-major storage\n cublasSgemm(handle, CUBLAS_OP_N, CUBLAS_OP_N,\n N, M, K, // Dimensions (swapped for column-major)\n &alpha, // Scaling factor\n d_B, N, // Matrix B and leading dimension\n d_A, K, // Matrix A and leading dimension\n &beta, // Beta scaling factor\n d_C, N); // Result matrix C and leading dimension\n\n // This single call is typically 10-100x faster than naive implementation\n // due to:\n // - Optimized memory access patterns\n // - Use of Tensor Cores on supported hardware\n // - Advanced tiling and blocking strategies\n // - Assembly-level optimizations\n\n cublasDestroy(handle);\n cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);\n}cuDNN (CUDA Deep Neural Network library):
\n#include <cudnn.h>\n\nvoid optimized_convolution() {\n cudnnHandle_t cudnn;\n cudnnCreate(&cudnn);\n\n // Create tensor descriptors\n cudnnTensorDescriptor_t input_desc, output_desc, bias_desc;\n cudnnFilterDescriptor_t filter_desc;\n cudnnConvolutionDescriptor_t conv_desc;\n\n cudnnCreateTensorDescriptor(&input_desc);\n cudnnCreateTensorDescriptor(&output_desc);\n cudnnCreateTensorDescriptor(&bias_desc);\n cudnnCreateFilterDescriptor(&filter_desc);\n cudnnCreateConvolutionDescriptor(&conv_desc);\n\n // Set descriptors (batch=32, channels=256, height=32, width=32)\n cudnnSetTensorNdDescriptor(input_desc, CUDNN_DATA_FLOAT, 4,\n (int[]){32, 256, 32, 32}, // dimensions\n (int[]){262144, 1024, 32, 1}); // strides\n\n // Set filter descriptor (512 output channels, 256 input channels, 3x3 kernel)\n cudnnSetFilterNdDescriptor(filter_desc, CUDNN_DATA_FLOAT, CUDNN_TENSOR_NCHW, 4,\n (int[]){512, 256, 3, 3});\n\n // Set convolution parameters\n cudnnSetConvolutionNdDescriptor(conv_desc, 2, // 2D convolution\n (int[]){1, 1}, // padding\n (int[]){1, 1}, // stride\n (int[]){1, 1}, // dilation\n CUDNN_CROSS_CORRELATION, // correlation mode\n CUDNN_DATA_FLOAT); // data type\n\n // Find best algorithm\n cudnnConvolutionFwdAlgoPerf_t algo_perf[10];\n int returned_algo_count;\n cudnnFindConvolutionForwardAlgorithm(cudnn, input_desc, filter_desc, conv_desc, output_desc,\n 10, &returned_algo_count, algo_perf);\n\n // cuDNN automatically selects optimal algorithm based on:\n // - Hardware capabilities (Tensor Cores, memory bandwidth)\n // - Input dimensions and data types\n // - Available memory for workspace\n\n cudnnDestroy(cudnn);\n}The current era of GPU computing is characterized by:
\nAdvanced Data Types and Precision:
\nSparsity Acceleration:\nModern GPUs include hardware support for sparse computations, crucial for efficient neural network inference:
\nimport torch\nimport torch.nn.utils.prune as prune\n\n# Example: Structured sparsity with 2:4 pattern (2 non-zeros in every 4 elements)\ndef apply_structured_sparsity(model):\n \"\"\"Apply 2:4 structured sparsity pattern\"\"\"\n for module in model.modules():\n if isinstance(module, torch.nn.Linear):\n # Apply structured pruning that's hardware-accelerated on A100/H100\n prune.structured(module, 'weight', amount=0.5, dim=1)\n\n return model\n\n# Modern sparse operations can achieve:\n# - 2x speedup in compute\n# - 2x reduction in memory bandwidth\n# - Minimal accuracy loss when properly trainedAttention-Specific Kernels:\nThe transformer architecture has driven development of specialized kernels:
\nCode Example: Flash Attention Concept (Python)import torch\nimport torch.nn.functional as F\n\ndef flash_attention_concept(Q, K, V):\n \"\"\"\n Conceptual implementation of Flash Attention algorithm\n Real implementation uses custom CUDA kernels for optimal memory usage\n \"\"\"\n B, H, N, D = Q.shape # Batch, Heads, Sequence, Dimension\n\n # Traditional attention: O(N²) memory usage\n # scores = Q @ K.transpose(-2, -1) / math.sqrt(D) # N x N matrix\n # attn = F.softmax(scores, dim=-1)\n # output = attn @ V\n\n # Flash Attention: Tiled computation with O(N) memory\n block_size = 128 # Tile size chosen based on SRAM capacity\n output = torch.zeros_like(Q)\n\n for i in range(0, N, block_size):\n # Load Q tile into SRAM\n Q_block = Q[:, :, i:i+block_size, :]\n\n for j in range(0, N, block_size):\n # Load K,V tile into SRAM\n K_block = K[:, :, j:j+block_size, :]\n V_block = V[:, :, j:j+block_size, :]\n\n # Compute attention block entirely in SRAM\n scores_block = Q_block @ K_block.transpose(-2, -1)\n attn_block = F.softmax(scores_block, dim=-1)\n output_block = attn_block @ V_block\n\n # Accumulate results (with proper scaling for softmax)\n output[:, :, i:i+block_size, :] += output_block\n\n return output\n\n# Benefits of Flash Attention:\n# - Reduces memory usage from O(N²) to O(N)\n# - Enables training on much longer sequences\n# - 2-4x faster than standard attention on A100/H100Advanced Compiler Stacks:
\nCode Example: Triton GPU Kernel ProgrammingTriton: Python-based GPU kernel programming
import triton\nimport triton.language as tl\n\n@triton.jit\ndef vector_add_kernel(x_ptr, y_ptr, output_ptr, n_elements, BLOCK_SIZE: tl.constexpr):\n \"\"\"High-performance vector addition using Triton\"\"\"\n pid = tl.program_id(axis=0)\n block_start = pid * BLOCK_SIZE\n offsets = block_start + tl.arange(0, BLOCK_SIZE)\n\n # Mask for boundary checking\n mask = offsets < n_elements\n\n # Load data\n x = tl.load(x_ptr + offsets, mask=mask)\n y = tl.load(y_ptr + offsets, mask=mask)\n\n # Compute\n output = x + y\n\n # Store result\n tl.store(output_ptr + offsets, output, mask=mask)\n\ndef vector_add(x, y):\n output = torch.empty_like(x)\n n_elements = output.numel()\n\n # Auto-tuning finds optimal block size\n grid = lambda meta: (triton.cdiv(n_elements, meta['BLOCK_SIZE']),)\n\n vector_add_kernel[grid](x, y, output, n_elements, BLOCK_SIZE=1024)\n return outputCUDA Graphs: Reduce kernel launch overhead
import torch\n\ndef cuda_graph_optimization():\n \"\"\"Demonstrate CUDA Graphs for reducing launch overhead\"\"\"\n\n # Warmup\n x = torch.randn(10000, device='cuda')\n y = torch.randn(10000, device='cuda')\n\n # Capture computation graph\n g = torch.cuda.CUDAGraph()\n\n # Warmup\n s = torch.cuda.Stream()\n s.wait_stream(torch.cuda.current_stream())\n\n with torch.cuda.stream(s):\n for _ in range(3): # Warmup runs\n z = x + y\n z = z * 2\n z = torch.relu(z)\n\n torch.cuda.current_stream().wait_stream(s)\n\n # Capture\n with torch.cuda.graph(g):\n z = x + y\n z = z * 2\n z = torch.relu(z)\n\n # Replay graph (much faster than individual kernel launches)\n g.replay()\n\n # Benefits:\n # - Eliminates CPU-GPU synchronization overhead\n # - Reduces kernel launch latency from ~10µs to ~1µs\n # - Enables optimization across kernel boundariesThis evolution from graphics-centric hardware to general-purpose parallel computing platforms represents one of the most significant developments in modern computer science, enabling the current AI revolution and continuing to drive innovations in scientific computing, machine learning, and high-performance computing applications.
\nModern GPUs are built around Streaming Multiprocessors (SMs), which are the fundamental compute units that execute parallel workloads. Each SM contains hundreds of cores, shared memory, registers, and specialized compute units like Tensor Cores.
\nThe GPU execution hierarchy follows a well-defined structure:
\nGPU Device\n├─ Streaming Multiprocessor 0 (SM0)\n│ ├─ CUDA Cores (FP32/INT32): ~64-128 cores\n│ ├─ Tensor Cores: 4-8 units (for AI workloads)\n│ ├─ Shared Memory: 48-164 KB (configurable)\n│ ├─ Register File: 256 KB (65,536 32-bit registers)\n│ ├─ L1 Cache/Texture Cache: 128 KB\n│ └─ Warp Schedulers: 4 units\n├─ Streaming Multiprocessor 1 (SM1)\n│ └─ [Same structure as SM0]\n└─ ... (up to 132 SMs in A100)Understanding the GPU thread hierarchy is crucial for writing efficient parallel code:
\n1. Thread: The smallest unit of execution
\n2. Warp: Group of 32 threads executed in lockstep
\n3. Block: Collection of threads (up to 1024) that can cooperate
\n__syncthreads()4. Grid: Collection of blocks that compose the entire kernel launch
\n#include <cuda_runtime.h>\n#include <stdio.h>\n\n__global__ void demonstrate_thread_hierarchy(int* data, int n) {\n // Thread identification within the hierarchy\n int global_thread_id = blockIdx.x * blockDim.x + threadIdx.x;\n int warp_id = global_thread_id / 32;\n int lane_id = global_thread_id % 32;\n int block_id = blockIdx.x;\n int thread_in_block = threadIdx.x;\n\n if (global_thread_id < n) {\n // Each thread processes its unique data element\n data[global_thread_id] = global_thread_id;\n\n // Demonstrate warp-level operations\n // All threads in the same warp see the same warp_id\n if (lane_id == 0) {\n printf(\"Warp %d in Block %d starting execution\\n\", warp_id, block_id);\n }\n\n // Warp-level primitive: ballot (which threads meet condition)\n int mask = __ballot_sync(0xFFFFFFFF, data[global_thread_id] % 2 == 0);\n if (lane_id == 0) {\n printf(\"Warp %d: threads with even values: 0x%08x\\n\", warp_id, mask);\n }\n }\n}\n\nvoid launch_hierarchical_kernel() {\n const int N = 2048;\n int* h_data = new int[N];\n int* d_data;\n\n cudaMalloc(&d_data, N * sizeof(int));\n\n // Configure kernel launch parameters\n int threads_per_block = 256; // 8 warps per block\n int blocks_per_grid = (N + threads_per_block - 1) / threads_per_block;\n\n printf(\"Launching kernel with:\\n\");\n printf(\" Threads per block: %d\\n\", threads_per_block);\n printf(\" Blocks per grid: %d\\n\", blocks_per_grid);\n printf(\" Total threads: %d\\n\", blocks_per_grid * threads_per_block);\n\n demonstrate_thread_hierarchy<<<blocks_per_grid, threads_per_block>>>(d_data, N);\n cudaDeviceSynchronize();\n\n cudaMemcpy(h_data, d_data, N * sizeof(int), cudaMemcpyDeviceToHost);\n\n delete[] h_data;\n cudaFree(d_data);\n}A kernel is a function that runs on the GPU and is executed by thousands of threads in parallel. Unlike CPU functions that execute once, kernels are launched over a grid of thread blocks:
\n// Kernel declaration with __global__ qualifier\n__global__ void matrix_vector_multiply(float* matrix, float* vector, float* result, int rows, int cols) {\n // Each thread computes one element of the result vector\n int row = blockIdx.x * blockDim.x + threadIdx.x;\n\n if (row < rows) {\n float sum = 0.0f;\n for (int col = 0; col < cols; col++) {\n sum += matrix[row * cols + col] * vector[col];\n }\n result[row] = sum;\n }\n}\n\nvoid launch_matrix_vector_kernel() {\n const int ROWS = 4096, COLS = 4096;\n\n // Host memory allocation\n float* h_matrix = new float[ROWS * COLS];\n float* h_vector = new float[COLS];\n float* h_result = new float[ROWS];\n\n // Initialize data\n for (int i = 0; i < ROWS * COLS; i++) h_matrix[i] = (float)rand() / RAND_MAX;\n for (int i = 0; i < COLS; i++) h_vector[i] = (float)rand() / RAND_MAX;\n\n // Device memory allocation\n float *d_matrix, *d_vector, *d_result;\n cudaMalloc(&d_matrix, ROWS * COLS * sizeof(float));\n cudaMalloc(&d_vector, COLS * sizeof(float));\n cudaMalloc(&d_result, ROWS * sizeof(float));\n\n // Data transfer to device\n cudaMemcpy(d_matrix, h_matrix, ROWS * COLS * sizeof(float), cudaMemcpyHostToDevice);\n cudaMemcpy(d_vector, h_vector, COLS * sizeof(float), cudaMemcpyHostToDevice);\n\n // Kernel launch configuration\n int block_size = 256;\n int grid_size = (ROWS + block_size - 1) / block_size;\n\n // Launch kernel over grid of blocks\n matrix_vector_multiply<<<grid_size, block_size>>>(d_matrix, d_vector, d_result, ROWS, COLS);\n\n // Copy result back\n cudaMemcpy(h_result, d_result, ROWS * sizeof(float), cudaMemcpyDeviceToHost);\n\n // Cleanup\n delete[] h_matrix; delete[] h_vector; delete[] h_result;\n cudaFree(d_matrix); cudaFree(d_vector); cudaFree(d_result);\n}Threads within the same block can cooperate through shared memory, a fast on-chip memory space that enables data sharing and synchronization:
\n__global__ void cooperative_reduction(float* input, float* output, int n) {\n // Shared memory allocation - shared by all threads in the block\n __shared__ float shared_data[256]; // Assuming block size of 256\n\n int tid = threadIdx.x;\n int global_id = blockIdx.x * blockDim.x + threadIdx.x;\n\n // Load data into shared memory\n if (global_id < n) {\n shared_data[tid] = input[global_id];\n } else {\n shared_data[tid] = 0.0f;\n }\n\n // Synchronize to ensure all threads have loaded their data\n __syncthreads();\n\n // Parallel reduction in shared memory\n for (int stride = blockDim.x / 2; stride > 0; stride >>= 1) {\n if (tid < stride) {\n shared_data[tid] += shared_data[tid + stride];\n }\n __syncthreads(); // Synchronize after each reduction step\n }\n\n // Thread 0 writes the block's result\n if (tid == 0) {\n output[blockIdx.x] = shared_data[0];\n }\n}High Bandwidth Memory (HBM) or VRAM serves as the main memory for GPU computations:
\nCharacteristics:
\nimport torch\nimport time\n\ndef demonstrate_memory_coalescing():\n \"\"\"Show the importance of memory access patterns\"\"\"\n device = torch.device('cuda' if torch.cuda.is_available() else 'cpu')\n\n # Large matrix to stress memory system\n N = 4096\n matrix = torch.randn(N, N, device=device, dtype=torch.float32)\n\n # Coalesced access: consecutive threads access consecutive memory\n def coalesced_access(mat):\n torch.cuda.synchronize()\n start_time = time.time()\n\n # Row-major access - coalesced for C-style arrays\n result = mat.sum(dim=1) # Sum along rows\n\n torch.cuda.synchronize()\n return time.time() - start_time\n\n # Non-coalesced access: strided memory access\n def strided_access(mat):\n torch.cuda.synchronize()\n start_time = time.time()\n\n # Column-major access - non-coalesced, poor cache usage\n result = mat.sum(dim=0) # Sum along columns\n\n torch.cuda.synchronize()\n return time.time() - start_time\n\n # Memory bandwidth test\n def measure_bandwidth():\n size_mb = 1000\n elements = (size_mb * 1024 * 1024) // 4 # 4 bytes per float32\n data = torch.randn(elements, device=device, dtype=torch.float32)\n\n torch.cuda.synchronize()\n start_time = time.time()\n\n # Simple copy operation to measure raw bandwidth\n copy = data.clone()\n\n torch.cuda.synchronize()\n elapsed = time.time() - start_time\n\n # Calculate bandwidth (read + write)\n bytes_transferred = elements * 4 * 2 # read + write\n bandwidth_gb_s = bytes_transferred / elapsed / (1024**3)\n\n return bandwidth_gb_s\n\n coalesced_time = coalesced_access(matrix)\n strided_time = strided_access(matrix)\n bandwidth = measure_bandwidth()\n\n print(f\"Coalesced access time: {coalesced_time:.4f}s\")\n print(f\"Strided access time: {strided_time:.4f}s\")\n print(f\"Performance ratio: {strided_time/coalesced_time:.2f}x slower for strided\")\n print(f\"Measured memory bandwidth: {bandwidth:.1f} GB/s\")\n\ndemonstrate_memory_coalescing()Modern GPUs implement a sophisticated cache hierarchy to reduce memory latency:
\nL2 Cache:
\nL1 Cache/Texture Cache:
\n__global__ void cache_friendly_stencil(float* input, float* output, int width, int height) {\n int x = blockIdx.x * blockDim.x + threadIdx.x;\n int y = blockIdx.y * blockDim.y + threadIdx.y;\n\n if (x > 0 && x < width-1 && y > 0 && y < height-1) {\n int idx = y * width + x;\n\n // 5-point stencil operation - benefits from L1 cache due to spatial locality\n float center = input[idx];\n float left = input[idx - 1];\n float right = input[idx + 1];\n float up = input[idx - width];\n float down = input[idx + width];\n\n // Weighted average - neighboring elements likely in L1 cache\n output[idx] = 0.2f * (center + left + right + up + down);\n }\n}Shared Memory is the programmer’s primary tool for optimizing memory access patterns:
\nCharacteristics:
\n#define TILE_SIZE 16\n\n__global__ void tiled_matrix_multiply(float* A, float* B, float* C, int N) {\n // Shared memory tiles - allocated per thread block\n __shared__ float tile_A[TILE_SIZE][TILE_SIZE];\n __shared__ float tile_B[TILE_SIZE][TILE_SIZE];\n\n int row = blockIdx.y * blockDim.y + threadIdx.y;\n int col = blockIdx.x * blockDim.x + threadIdx.x;\n\n float sum = 0.0f;\n\n // Loop over tiles\n for (int tile = 0; tile < (N + TILE_SIZE - 1) / TILE_SIZE; tile++) {\n // Collaborative loading: each thread loads one element\n int tile_row = tile * TILE_SIZE + threadIdx.x;\n int tile_col = tile * TILE_SIZE + threadIdx.y;\n\n // Load tile of A\n if (row < N && tile_row < N) {\n tile_A[threadIdx.y][threadIdx.x] = A[row * N + tile_row];\n } else {\n tile_A[threadIdx.y][threadIdx.x] = 0.0f;\n }\n\n // Load tile of B\n if (tile_col < N && col < N) {\n tile_B[threadIdx.y][threadIdx.x] = B[tile_col * N + col];\n } else {\n tile_B[threadIdx.y][threadIdx.x] = 0.0f;\n }\n\n // Synchronize to ensure tile loading is complete\n __syncthreads();\n\n // Compute using data in shared memory (much faster than global memory)\n for (int k = 0; k < TILE_SIZE; k++) {\n sum += tile_A[threadIdx.y][k] * tile_B[k][threadIdx.x];\n }\n\n // Synchronize before loading next tile\n __syncthreads();\n }\n\n // Write result\n if (row < N && col < N) {\n C[row * N + col] = sum;\n }\n}Registers provide the fastest memory access but are limited in quantity:
\nCharacteristics:
\n__global__ void register_usage_example(float* data, int n) {\n int tid = blockIdx.x * blockDim.x + threadIdx.x;\n\n if (tid < n) {\n // These variables are stored in registers (fastest access)\n float reg1 = data[tid];\n float reg2 = reg1 * 2.0f;\n float reg3 = reg2 + 1.0f;\n float reg4 = reg3 / 3.0f;\n\n // Complex computation using registers\n for (int i = 0; i < 10; i++) {\n reg1 = sinf(reg1) + cosf(reg2);\n reg2 = sqrtf(reg3) * reg4;\n reg3 = reg1 + reg2;\n reg4 = reg3 - reg1;\n }\n\n data[tid] = reg4;\n }\n}Understanding whether your kernel is memory-bound or compute-bound is crucial for optimization:
\nMemory-Bound Kernels:
\nCompute-Bound Kernels:
\nArithmetic Intensity (AI) = FLOPs / Bytes transferred from HBM
\nThis metric determines the performance ceiling of your kernel:
\nCode Example: Arithmetic Intensity Analysisimport torch\nimport time\n\ndef analyze_arithmetic_intensity():\n \"\"\"Demonstrate the concept of arithmetic intensity\"\"\"\n\n device = torch.device('cuda')\n N = 4096\n\n # Example 1: Low arithmetic intensity (memory-bound)\n def vector_add_analysis():\n a = torch.randn(N, N, device=device, dtype=torch.float32)\n b = torch.randn(N, N, device=device, dtype=torch.float32)\n\n torch.cuda.synchronize()\n start = time.time()\n c = a + b # 1 FLOP per element\n torch.cuda.synchronize()\n elapsed = time.time() - start\n\n elements = N * N\n flops = elements # 1 FLOP per element\n bytes_transferred = elements * 4 * 3 # 3 arrays × 4 bytes per float32\n arithmetic_intensity = flops / bytes_transferred\n\n print(f\"Vector Addition:\")\n print(f\" Arithmetic Intensity: {arithmetic_intensity:.3f} FLOPs/Byte\")\n print(f\" Time: {elapsed:.4f}s\")\n print(f\" Performance: {flops / elapsed / 1e9:.2f} GFLOPS\")\n\n return arithmetic_intensity\n\n # Example 2: High arithmetic intensity (compute-bound)\n def matrix_multiply_analysis():\n a = torch.randn(N, N, device=device, dtype=torch.float32)\n b = torch.randn(N, N, device=device, dtype=torch.float32)\n\n torch.cuda.synchronize()\n start = time.time()\n c = torch.matmul(a, b) # N³ FLOPs for N×N matrices\n torch.cuda.synchronize()\n elapsed = time.time() - start\n\n flops = 2 * N * N * N # N³ multiply-add operations\n bytes_transferred = N * N * 4 * 3 # 3 matrices × 4 bytes per float32\n arithmetic_intensity = flops / bytes_transferred\n\n print(f\"\\nMatrix Multiplication:\")\n print(f\" Arithmetic Intensity: {arithmetic_intensity:.3f} FLOPs/Byte\")\n print(f\" Time: {elapsed:.4f}s\")\n print(f\" Performance: {flops / elapsed / 1e12:.2f} TFLOPS\")\n\n return arithmetic_intensity\n\n # Example 3: Medium arithmetic intensity\n def convolution_analysis():\n # 3D convolution: batch=32, channels=256, spatial=64x64, kernel=3x3\n input_tensor = torch.randn(32, 256, 64, 64, device=device, dtype=torch.float32)\n kernel = torch.randn(512, 256, 3, 3, device=device, dtype=torch.float32)\n\n torch.cuda.synchronize()\n start = time.time()\n output = torch.nn.functional.conv2d(input_tensor, kernel, padding=1)\n torch.cuda.synchronize()\n elapsed = time.time() - start\n\n # Approximate FLOP count for convolution\n batch_size, in_channels, height, width = input_tensor.shape\n out_channels, _, kernel_h, kernel_w = kernel.shape\n\n flops = batch_size * out_channels * height * width * in_channels * kernel_h * kernel_w * 2\n input_bytes = input_tensor.numel() * 4\n kernel_bytes = kernel.numel() * 4\n output_bytes = output.numel() * 4\n bytes_transferred = input_bytes + kernel_bytes + output_bytes\n\n arithmetic_intensity = flops / bytes_transferred\n\n print(f\"\\nConvolution:\")\n print(f\" Arithmetic Intensity: {arithmetic_intensity:.3f} FLOPs/Byte\")\n print(f\" Time: {elapsed:.4f}s\")\n print(f\" Performance: {flops / elapsed / 1e12:.2f} TFLOPS\")\n\n return arithmetic_intensity\n\n ai_low = vector_add_analysis()\n ai_high = matrix_multiply_analysis()\n ai_medium = convolution_analysis()\n\n return ai_low, ai_medium, ai_high\n\nanalyze_arithmetic_intensity()Let’s analyze the NVIDIA A100’s performance characteristics:
\nCode Example: A100 Performance Modeldef a100_performance_model():\n \"\"\"Model A100 performance characteristics\"\"\"\n\n # A100 specifications\n specs = {\n 'peak_fp32_compute': 19.5, # TFLOPS\n 'peak_hbm_bandwidth': 1.5, # TB/s\n 'hbm_capacity': 40, # GB (base model)\n 'sm_count': 108,\n 'tensor_core_fp16': 312, # TFLOPS with sparsity\n 'l2_cache': 40, # MB\n 'shared_memory_per_sm': 164, # KB\n }\n\n # Calculate ridge point (arithmetic intensity threshold)\n ridge_point = specs['peak_fp32_compute'] / specs['peak_hbm_bandwidth']\n\n print(\"NVIDIA A100 Performance Analysis:\")\n print(f\"Peak FP32 Compute: {specs['peak_fp32_compute']} TFLOPS\")\n print(f\"Peak HBM Bandwidth: {specs['peak_hbm_bandwidth']} TB/s\")\n print(f\"Ridge Point: {ridge_point:.1f} FLOPs/Byte\")\n print(f\"L2 Cache: {specs['l2_cache']} MB\")\n print(f\"Shared Memory per SM: {specs['shared_memory_per_sm']} KB\")\n\n print(\"\\nPerformance Predictions:\")\n\n # Analyze different operation types\n operations = [\n (\"Vector Add\", 1, \"Memory-bound\"),\n (\"Convolution (typical)\", 50, \"Balanced\"),\n (\"Dense GEMM\", 100, \"Compute-bound\"),\n (\"Sparse GEMM (2:4)\", 200, \"Highly compute-bound\")\n ]\n\n for op_name, ai, classification in operations:\n if ai < ridge_point:\n max_performance = ai * specs['peak_hbm_bandwidth']\n bottleneck = \"Memory bandwidth\"\n else:\n max_performance = specs['peak_fp32_compute']\n bottleneck = \"Compute throughput\"\n\n print(f\"{op_name:20} | AI: {ai:3.0f} | Max: {max_performance:5.1f} TFLOPS | {bottleneck}\")\n\n return specs, ridge_point\n\nspecs, ridge_point = a100_performance_model()Many applications suffer from overhead-bound performance, where kernel launch and dispatch overhead dominates:
\nCode Example: Kernel Launch Overhead Analysisimport torch\nimport time\n\ndef demonstrate_overhead_bound():\n \"\"\"Show how small kernels can be overhead-bound\"\"\"\n\n device = torch.device('cuda')\n\n def measure_kernel_overhead(size, num_launches):\n \"\"\"Measure overhead for small vs large kernels\"\"\"\n\n a = torch.randn(size, device=device, dtype=torch.float32)\n b = torch.randn(size, device=device, dtype=torch.float32)\n\n # Warm up\n for _ in range(10):\n c = a + b\n\n torch.cuda.synchronize()\n start = time.time()\n\n for _ in range(num_launches):\n c = a + b\n\n torch.cuda.synchronize()\n elapsed = time.time() - start\n\n time_per_kernel = elapsed / num_launches * 1000 # milliseconds\n elements_per_second = size * num_launches / elapsed / 1e9 # billion elements/sec\n\n return time_per_kernel, elements_per_second\n\n print(\"Kernel Launch Overhead Analysis:\")\n print(\"Size\\t\\tTime/Kernel\\tBandwidth\")\n print(\"-\" * 40)\n\n sizes = [100, 1000, 10000, 100000, 1000000, 10000000]\n num_launches = 1000\n\n for size in sizes:\n time_per_kernel, throughput = measure_kernel_overhead(size, num_launches)\n print(f\"{size:8d}\\t{time_per_kernel:8.3f}ms\\t{throughput:8.2f} GEl/s\")\n\n print(\"\\nObservations:\")\n print(\"- Small kernels show high overhead (low throughput)\")\n print(\"- Large kernels amortize launch overhead\")\n print(\"- Async execution can help hide overhead\")\n\ndemonstrate_overhead_bound()Operator Fusion combines multiple operations to reduce memory traffic and kernel launch overhead:
\nCode Example: Operator Fusion with Tritonimport torch\nimport triton\nimport triton.language as tl\n\n# Traditional unfused operations\ndef unfused_operations(x):\n \"\"\"Separate kernels for each operation\"\"\"\n temp1 = x + 1.0 # Kernel 1: load x, store temp1\n temp2 = torch.relu(temp1) # Kernel 2: load temp1, store temp2\n result = temp2 * 2.0 # Kernel 3: load temp2, store result\n return result\n\n# Fused kernel using Triton\n@triton.jit\ndef fused_kernel(x_ptr, output_ptr, n_elements, BLOCK_SIZE: tl.constexpr):\n \"\"\"Fused kernel: x -> (x + 1) -> ReLU -> (* 2) in one pass\"\"\"\n\n pid = tl.program_id(axis=0)\n block_start = pid * BLOCK_SIZE\n offsets = block_start + tl.arange(0, BLOCK_SIZE)\n mask = offsets < n_elements\n\n # Load input once\n x = tl.load(x_ptr + offsets, mask=mask)\n\n # Perform all operations in registers\n temp = x + 1.0\n temp = tl.where(temp > 0, temp, 0.0) # ReLU\n result = temp * 2.0\n\n # Store result once\n tl.store(output_ptr + offsets, result, mask=mask)\n\ndef fused_operations(x):\n \"\"\"Fused version using Triton\"\"\"\n output = torch.empty_like(x)\n n_elements = output.numel()\n\n # Auto-tune block size for optimal performance\n grid = lambda meta: (triton.cdiv(n_elements, meta['BLOCK_SIZE']),)\n fused_kernel[grid](x, output, n_elements, BLOCK_SIZE=1024)\n\n return output\n\ndef benchmark_fusion():\n \"\"\"Compare fused vs unfused performance\"\"\"\n device = torch.device('cuda')\n x = torch.randn(10_000_000, device=device, dtype=torch.float32)\n\n # Benchmark unfused\n torch.cuda.synchronize()\n start = time.time()\n for _ in range(100):\n result1 = unfused_operations(x)\n torch.cuda.synchronize()\n unfused_time = time.time() - start\n\n # Benchmark fused\n torch.cuda.synchronize()\n start = time.time()\n for _ in range(100):\n result2 = fused_operations(x)\n torch.cuda.synchronize()\n fused_time = time.time() - start\n\n # Verify results are equivalent\n assert torch.allclose(result1, result2, atol=1e-6)\n\n print(f\"Unfused time: {unfused_time:.4f}s\")\n print(f\"Fused time: {fused_time:.4f}s\")\n print(f\"Speedup: {unfused_time / fused_time:.2f}x\")\n\n # Memory traffic analysis\n element_count = x.numel()\n unfused_traffic = element_count * 4 * 6 # 6 memory transactions\n fused_traffic = element_count * 4 * 2 # 2 memory transactions\n\n print(f\"Memory traffic reduction: {unfused_traffic / fused_traffic:.2f}x\")\n\n# benchmark_fusion() # Uncomment to runTiling is a fundamental optimization technique that improves the performance of compute-intensive operations by exploiting the GPU’s memory hierarchy. The core idea is to load data into fast shared memory and reuse it multiple times, thereby increasing arithmetic intensity and reducing the number of expensive global memory accesses.
\nWhy Tiling Works:
\nWhen performing operations like matrix multiplication, the naive approach requires each thread to load data from global memory multiple times. For example, in a matrix multiplication C = A × B, each element of the result matrix C[i,j] requires loading an entire row from matrix A and an entire column from matrix B. Without tiling, this leads to:
\nTiling addresses these issues by:
\nDetailed Implementation Example:
\n#define TILE_SIZE 32\n\n__global__ void tiled_gemm_optimized(float* A, float* B, float* C, int M, int N, int K) {\n // Shared memory tiles - allocated per thread block\n // Each tile can hold TILE_SIZE × TILE_SIZE elements\n __shared__ float As[TILE_SIZE][TILE_SIZE];\n __shared__ float Bs[TILE_SIZE][TILE_SIZE];\n\n // Block and thread indices for navigation\n int bx = blockIdx.x, by = blockIdx.y;\n int tx = threadIdx.x, ty = threadIdx.y;\n\n // Global indices for this thread\n int row = by * TILE_SIZE + ty; // Row in matrix C\n int col = bx * TILE_SIZE + tx; // Column in matrix C\n\n float sum = 0.0f; // Accumulator for this thread's result\n\n // Main tiling loop: iterate through tiles of A and B\n // Number of tiles needed to cover dimension K\n int num_tiles = (K + TILE_SIZE - 1) / TILE_SIZE;\n\n for (int tile_idx = 0; tile_idx < num_tiles; tile_idx++) {\n\n // Phase 1: Collaborative loading of tiles into shared memory\n\n // Load tile from matrix A\n int a_row = row; // Same row as output\n int a_col = tile_idx * TILE_SIZE + tx; // Column shifts with tile\n\n if (a_row < M && a_col < K) {\n As[ty][tx] = A[a_row * K + a_col];\n } else {\n As[ty][tx] = 0.0f; // Handle boundary cases\n }\n\n // Load tile from matrix B\n int b_row = tile_idx * TILE_SIZE + ty; // Row shifts with tile\n int b_col = col; // Same column as output\n\n if (b_row < K && b_col < N) {\n Bs[ty][tx] = B[b_row * N + b_col];\n } else {\n Bs[ty][tx] = 0.0f; // Handle boundary cases\n }\n\n // Synchronization barrier: ensure all threads have finished loading\n __syncthreads();\n\n // Phase 2: Computation using shared memory data\n // Each thread computes its portion using the loaded tiles\n for (int k = 0; k < TILE_SIZE; k++) {\n // This access is to shared memory (very fast)\n sum += As[ty][k] * Bs[k][tx];\n }\n\n // Another synchronization barrier before loading next tile\n __syncthreads();\n }\n\n // Phase 3: Write result to global memory\n if (row < M && col < N) {\n C[row * N + col] = sum;\n }\n}\n\n// Advanced tiling with register blocking for even better performance\n__global__ void tiled_gemm_register_blocked(float* A, float* B, float* C, int M, int N, int K) {\n // Shared memory tiles\n __shared__ float As[TILE_SIZE][TILE_SIZE];\n __shared__ float Bs[TILE_SIZE][TILE_SIZE];\n\n // Register blocking: each thread computes multiple output elements\n #define REG_TILE_M 4\n #define REG_TILE_N 4\n\n float reg_c[REG_TILE_M][REG_TILE_N] = {{0.0f}}; // Register tile for results\n float reg_a[REG_TILE_M]; // Register cache for A values\n float reg_b[REG_TILE_N]; // Register cache for B values\n\n int bx = blockIdx.x, by = blockIdx.y;\n int tx = threadIdx.x, ty = threadIdx.y;\n\n // Each thread block handles a larger tile due to register blocking\n int block_row_start = by * (TILE_SIZE * REG_TILE_M);\n int block_col_start = bx * (TILE_SIZE * REG_TILE_N);\n\n // This thread's starting position within the block's output region\n int thread_row_start = block_row_start + ty * REG_TILE_M;\n int thread_col_start = block_col_start + tx * REG_TILE_N;\n\n // Main computation loop over K dimension\n for (int tile_k = 0; tile_k < K; tile_k += TILE_SIZE) {\n\n // Load tiles into shared memory (similar to previous example)\n // ... loading code omitted for brevity ...\n\n __syncthreads();\n\n // Inner loop over the tile in shared memory\n for (int k = 0; k < TILE_SIZE; k++) {\n // Load values into registers for reuse\n for (int i = 0; i < REG_TILE_M; i++) {\n reg_a[i] = As[ty * REG_TILE_M + i][k];\n }\n for (int j = 0; j < REG_TILE_N; j++) {\n reg_b[j] = Bs[k][tx * REG_TILE_N + j];\n }\n\n // Compute outer product of register vectors\n for (int i = 0; i < REG_TILE_M; i++) {\n for (int j = 0; j < REG_TILE_N; j++) {\n reg_c[i][j] += reg_a[i] * reg_b[j];\n }\n }\n }\n\n __syncthreads();\n }\n\n // Write register tile back to global memory\n for (int i = 0; i < REG_TILE_M; i++) {\n for (int j = 0; j < REG_TILE_N; j++) {\n int global_row = thread_row_start + i;\n int global_col = thread_col_start + j;\n if (global_row < M && global_col < N) {\n C[global_row * N + global_col] = reg_c[i][j];\n }\n }\n }\n}Performance Analysis of Tiling:
\nimport torch\nimport time\nimport numpy as np\n\ndef analyze_tiling_performance():\n \"\"\"Comprehensive analysis of tiling performance benefits\"\"\"\n\n device = torch.device('cuda')\n\n # Test different matrix sizes\n sizes = [512, 1024, 2048, 4096]\n\n print(\"Tiling Performance Analysis:\")\n print(\"=\" * 60)\n print(f\"{'Size':>6} {'Naive (ms)':>12} {'Tiled (ms)':>12} {'Speedup':>10} {'AI Improvement':>15}\")\n print(\"-\" * 60)\n\n for size in sizes:\n # Create matrices\n A = torch.randn(size, size, device=device, dtype=torch.float32)\n B = torch.randn(size, size, device=device, dtype=torch.float32)\n\n # Naive implementation (PyTorch automatically uses optimized kernels)\n # For demonstration, we'll use a simple operation that isn't optimized\n torch.cuda.synchronize()\n start_time = time.time()\n\n # Simulate naive memory access pattern\n for _ in range(10):\n C_naive = torch.matmul(A, B) # This is actually optimized\n\n torch.cuda.synchronize()\n naive_time = (time.time() - start_time) / 10\n\n # Optimized tiled implementation (cuBLAS)\n torch.cuda.synchronize()\n start_time = time.time()\n\n for _ in range(10):\n C_tiled = torch.matmul(A, B) # Uses highly optimized tiled kernels\n\n torch.cuda.synchronize()\n tiled_time = (time.time() - start_time) / 10\n\n # Calculate theoretical arithmetic intensity improvement\n # Naive: each element loaded once per use\n # Tiled: each element loaded once per tile and reused TILE_SIZE times\n tile_size = 32 # Typical tile size\n ai_improvement = tile_size # Simplified calculation\n\n speedup = naive_time / tiled_time if tiled_time > 0 else float('inf')\n\n print(f\"{size:6d} {naive_time*1000:11.2f} {tiled_time*1000:11.2f} {speedup:9.1f}x {ai_improvement:14.1f}x\")\n\n print(\"\\nMemory Access Pattern Analysis:\")\n print(\"-\" * 40)\n\n # Demonstrate memory access patterns\n def calculate_memory_accesses(matrix_size, tile_size):\n \"\"\"Calculate memory accesses for tiled vs naive GEMM\"\"\"\n\n # Naive GEMM: each output element requires loading full row and column\n naive_loads = matrix_size ** 3 # N³ elements loaded\n\n # Tiled GEMM: each tile loaded once and reused\n tiles_per_dim = (matrix_size + tile_size - 1) // tile_size\n tile_loads = 2 * tiles_per_dim ** 3 * tile_size ** 2 # A and B tiles\n\n return naive_loads, tile_loads\n\n matrix_size = 1024\n tile_size = 32\n\n naive_loads, tiled_loads = calculate_memory_accesses(matrix_size, tile_size)\n\n print(f\"Matrix size: {matrix_size}×{matrix_size}\")\n print(f\"Tile size: {tile_size}×{tile_size}\")\n print(f\"Naive memory loads: {naive_loads:,}\")\n print(f\"Tiled memory loads: {tiled_loads:,}\")\n print(f\"Memory access reduction: {naive_loads/tiled_loads:.1f}x\")\n\n# Run the analysis\nanalyze_tiling_performance()Advanced Tiling Strategies:
\n1. Hierarchical Tiling:\nUses multiple levels of the memory hierarchy by combining L2 cache, shared memory, and register tiling:
\n__global__ void hierarchical_tiled_gemm(float* A, float* B, float* C, int M, int N, int K) {\n // Level 1: L2 cache tiling (handled by block scheduling)\n // Level 2: Shared memory tiling\n __shared__ float As[TILE_SIZE][TILE_SIZE];\n __shared__ float Bs[TILE_SIZE][TILE_SIZE];\n\n // Level 3: Register tiling\n float reg_tile[4][4] = {{0.0f}};\n\n // Implementation combines all three levels for maximum performance\n // ... (detailed implementation would be quite complex)\n}2. Double Buffering:\nOverlaps computation with memory loading to hide latency:
\n__global__ void double_buffered_gemm(float* A, float* B, float* C, int M, int N, int K) {\n // Double buffer: two sets of shared memory\n __shared__ float As[2][TILE_SIZE][TILE_SIZE];\n __shared__ float Bs[2][TILE_SIZE][TILE_SIZE];\n\n int read_buf = 0, compute_buf = 1;\n\n // Pipeline: load next tile while computing current tile\n for (int tile = 0; tile < num_tiles; tile++) {\n // Swap buffers\n read_buf = 1 - read_buf;\n compute_buf = 1 - compute_buf;\n\n // Asynchronously load next tile\n // Compute using current tile\n // Overlap memory and compute operations\n }\n}Real-World Application: Convolution Optimization:
\nimport torch\nimport torch.nn.functional as F\nimport time\n\ndef optimized_convolution_tiling():\n \"\"\"Demonstrate tiling in convolution operations\"\"\"\n\n device = torch.device('cuda')\n\n # Large convolution problem\n batch_size = 32\n in_channels = 256\n out_channels = 512\n height, width = 64, 64\n kernel_size = 3\n\n # Input tensor and kernel\n input_tensor = torch.randn(batch_size, in_channels, height, width, device=device)\n kernel = torch.randn(out_channels, in_channels, kernel_size, kernel_size, device=device)\n\n print(\"Convolution Tiling Analysis:\")\n print(\"-\" * 40)\n\n # Standard convolution (uses optimized tiled kernels internally)\n torch.cuda.synchronize()\n start_time = time.time()\n\n for _ in range(100):\n output = F.conv2d(input_tensor, kernel, padding=1)\n\n torch.cuda.synchronize()\n optimized_time = time.time() - start_time\n\n # Calculate theoretical arithmetic intensity\n # Each output pixel requires in_channels × kernel_size² operations\n flops = (batch_size * out_channels * height * width *\n in_channels * kernel_size * kernel_size * 2) # multiply-add\n\n # Memory traffic (input + kernel + output)\n input_bytes = input_tensor.numel() * 4\n kernel_bytes = kernel.numel() * 4\n output_bytes = output.numel() * 4\n total_bytes = input_bytes + kernel_bytes + output_bytes\n\n arithmetic_intensity = flops / total_bytes\n\n print(f\"Convolution performance: {optimized_time/100*1000:.2f} ms per forward pass\")\n print(f\"Arithmetic intensity: {arithmetic_intensity:.2f} FLOPs/byte\")\n print(f\"Throughput: {flops/optimized_time/1e12*100:.2f} TFLOPS\")\n\n # Tiling strategy for convolution:\n # 1. Tile input feature maps to fit in shared memory\n # 2. Load kernel weights once per tile\n # 3. Compute multiple output channels simultaneously\n # 4. Use register blocking for output accumulation\n\n return arithmetic_intensity\n\noptimized_convolution_tiling()Tiling Best Practices:
\nChoose Optimal Tile Size:
\nMinimize Bank Conflicts:
\nMaximize Data Reuse:
\nHandle Boundary Conditions:
\nConsider Memory Coalescing:
\nTiling is one of the most powerful optimization techniques for GPU computing, often providing 5-50x performance improvements for memory-bound operations by fundamentally changing the arithmetic intensity profile of algorithms.
\nModern research computing relies heavily on High-Performance Computing (HPC) systems that combine powerful hardware with sophisticated software stacks. Understanding how to effectively utilize these systems is crucial for researchers working at the cutting edge of computational science, machine learning, and artificial intelligence.
\nHPC System Architecture:
\n┌─────────────────────────────────────────────────────────────────┐\n│ HPC Cluster Overview │\n├─────────────────────────────────────────────────────────────────┤\n│ Login Nodes │ Compute Nodes │ Storage │\n│ ┌─────────────────┐ │ ┌─────────────────────┐ │ ┌───────────┐ │\n│ │ User Access │ │ │ CPU: 2x64-core AMD │ │ │ Parallel │ │\n│ │ Job Submission │ │ │ RAM: 512GB-2TB │ │ │ File │ │\n│ │ Code Development│ │ │ GPU: 4-8x A100/H100 │ │ │ System │ │\n│ │ Data Analysis │ │ │ NVLink/Infiniband │ │ │ (Lustre/ │ │\n│ └─────────────────┘ │ └─────────────────────┘ │ │ GPFS) │ │\n│ │ │ │ 10-100 PB │ │\n│ Resource Mgmt │ Scheduler (SLURM) │ └───────────┘ │\n│ ┌─────────────────┐ │ ┌─────────────────────┐ │ │\n│ │ Job Queues │ │ │ GPU Allocation │ │ Networking │\n│ │ User Limits │ │ │ Memory Management │ │ ┌───────────┐ │\n│ │ Fair Sharing │ │ │ Process Isolation │ │ │ InfiniBand│ │\n│ └─────────────────┘ │ └─────────────────────┘ │ │ 200-400 │ │\n└─────────────────────────────────────────────────────────────────┤ Gbps │ │\n │ │ Low Latency│ │\n │ └───────────┘ │\n └─────────────────┘Understanding modern GPU architectures is fundamental for researchers working with high-performance computing. The evolution from graphics-focused processors to general-purpose parallel computing engines has created unprecedented opportunities for scientific discovery and computational research.
\nNVIDIA A100 (Ampere Architecture) - The Research Workhorse:
\nThe A100 represents a paradigm shift in GPU design, specifically engineered for AI and HPC workloads. Unlike consumer GPUs that balance gaming and compute performance, the A100 is purpose-built for sustained computational throughput with features that directly address the needs of research computing.
\nArchitectural Deep Dive:
\nThe A100’s architecture is built around the concept of Streaming Multiprocessors (SMs), each containing multiple types of processing units optimized for different computational patterns:
\nMemory Subsystem Design:
\nThe A100’s memory architecture reflects a deep understanding of modern workload requirements:
\nMulti-Instance GPU (MIG) Technology:
\nOne of the A100’s most innovative features is MIG, which allows a single GPU to be partitioned into up to seven independent instances. This is particularly valuable for research environments where:
\ndef analyze_a100_capabilities():\n \"\"\"Comprehensive analysis of A100 computational capabilities\"\"\"\n\n # A100 specifications demonstrate the scale of modern research hardware\n a100_specs = {\n 'sm_count': 108, # Massive parallelism through many SMs\n 'cuda_cores_per_sm': 64, # Traditional scalar processing power\n 'tensor_cores_per_sm': 4, # Matrix acceleration per SM\n 'total_cuda_cores': 6912, # Total scalar processing units\n 'hbm2_memory': 40, # GB - Can be 80GB in larger variants\n 'memory_bandwidth': 1555, # GB/s - Critical for data-intensive research\n 'nvlink_bandwidth': 600, # GB/s bidirectional for multi-GPU scaling\n 'pcie_bandwidth': 64, # GB/s (PCIe 4.0) for host communication\n\n # Compute Performance demonstrates specialization for different precisions\n 'fp32_performance': 19.5, # TFLOPS - Traditional scientific computing\n 'tensor_fp16': 312, # TFLOPS - AI training acceleration\n 'tensor_bfloat16': 312, # TFLOPS - Improved numerical stability\n 'tensor_int8': 624, # TOPS - Inference optimization\n 'tensor_int4': 1248, # TOPS - Extreme quantization with sparsity\n\n # Research-specific features\n 'mig_support': True, # Multi-tenancy for shared research clusters\n 'sparsity_support': True, # 2:4 structured sparsity acceleration\n 'multi_precision': True, # Mixed-precision training capabilities\n 'nvlink_generation': 3, # High-speed inter-GPU communication\n 'memory_error_correction': True, # Critical for long-running simulations\n }\n\n print(\"NVIDIA A100 Research Capabilities Analysis:\")\n print(\"=\" * 60)\n\n # The ridge point calculation reveals the balance between compute and memory\n ridge_point = a100_specs['fp32_performance'] / (a100_specs['memory_bandwidth'] / 1000)\n print(f\"Peak FP32 Performance: {a100_specs['fp32_performance']} TFLOPS\")\n print(f\"Peak Memory Bandwidth: {a100_specs['memory_bandwidth']} GB/s\")\n print(f\"Ridge Point (AI threshold): {ridge_point:.1f} FLOPs/Byte\")\n print(f\" -> Operations with AI < {ridge_point:.1f} are memory-bound\")\n print(f\" -> Operations with AI > {ridge_point:.1f} can achieve compute-bound performance\")\n\n print(f\"\\nSpecialized Compute Units for Research:\")\n print(f\"FP16 Tensor Performance: {a100_specs['tensor_fp16']} TFLOPS\")\n print(f\" -> {a100_specs['tensor_fp16'] / a100_specs['fp32_performance']:.1f}x faster than FP32 for compatible workloads\")\n print(f\"INT8 Performance: {a100_specs['tensor_int8']} TOPS\")\n print(f\" -> {a100_specs['tensor_int8'] / a100_specs['fp32_performance']:.1f}x throughput for quantized inference\")\n print(f\"Sparse INT4 Performance: {a100_specs['tensor_int4']} TOPS\")\n print(f\" -> {a100_specs['tensor_int4'] / a100_specs['fp32_performance']:.1f}x theoretical peak with aggressive optimization\")\n\n # Memory hierarchy analysis shows the importance of data locality\n l2_cache_size = 40 # MB - Shared across all SMs\n shared_mem_per_sm = 164 # KB - Programmer-controlled fast memory\n register_file_per_sm = 256 # KB - Fastest per-thread storage\n\n print(f\"\\nMemory Hierarchy for Optimal Performance:\")\n print(f\"L2 Cache: {l2_cache_size} MB (shared across all {a100_specs['sm_count']} SMs)\")\n print(f\" -> Hardware-managed, reduces global memory pressure\")\n print(f\"Shared Memory per SM: {shared_mem_per_sm} KB\")\n print(f\" -> Programmer-controlled, enables collaborative algorithms\")\n print(f\"Register File per SM: {register_file_per_sm} KB\")\n print(f\" -> Per-thread storage, highest bandwidth but limited capacity\")\n print(f\"Total Fast Memory: {shared_mem_per_sm * a100_specs['sm_count'] / 1024:.1f} MB\")\n print(f\" -> Critical for staging data and avoiding memory bottlenecks\")\n\n # Research implications\n print(f\"\\nResearch Computing Implications:\")\n print(f\"Multi-Instance GPU: Up to 7 independent partitions\")\n print(f\" -> Enables secure multi-tenancy in shared research environments\")\n print(f\"NVLink Bandwidth: {a100_specs['nvlink_bandwidth']} GB/s\")\n print(f\" -> Supports large model training across multiple GPUs\")\n print(f\"Error Correction: Full ECC support\")\n print(f\" -> Essential for long-running simulations and reliable results\")\n\n return a100_specs\n\n# Demonstrate A100 capabilities for research applications\na100_specs = analyze_a100_capabilities()NVIDIA H100 (Hopper Architecture) - The Next Generation:
\nThe H100 represents the latest evolution in GPU architecture, incorporating lessons learned from the AI revolution and pushing the boundaries of what’s possible in computational research. Built on advanced process technology and featuring revolutionary architectural improvements, the H100 addresses the scaling challenges faced by modern AI research.
\nKey Architectural Innovations:
\nTransformer Engine: The H100 introduces hardware specifically designed for transformer architectures, the foundation of modern large language models. This includes:
\nAdvanced Memory Architecture:
\nThis comparison illustrates the exponential improvement in research computing capabilities across three major GPU generations:
\n| Specification | Value |
|---|---|
| Memory | 32 GB |
| Memory Bandwidth | 900 GB/s |
| FP32 Performance | 15.7 TFLOPS |
| Tensor FP16 Performance | 125 TFLOPS |
| Architecture | Volta (1st gen Tensor Cores) |
| Process Node | 12nm TSMC |
| Key Innovation | First Tensor Cores - mixed-precision training |
| Research Impact | Enabled modern deep learning research |
| Specification | Value |
|---|---|
| Memory | 80 GB (max variant) |
| Memory Bandwidth | 2,039 GB/s |
| FP32 Performance | 19.5 TFLOPS |
| Tensor FP16 Performance | 312 TFLOPS |
| Architecture | Ampere (2nd gen with sparsity) |
| Process Node | 7nm |
| Tensor Cores | Gen 3 - more data types |
| Key Innovation | MIG + 2 structured sparsity |
| Research Impact | Large-scale language model training |
| Specification | Value |
|---|---|
| Memory | 80 GB |
| Memory Bandwidth | 3,350 GB/s |
| FP32 Performance | 67 TFLOPS (with sparsity) |
| Tensor FP16 Performance | 1,979 TFLOPS (with sparsity) |
| Architecture | Hopper (4th gen with transformer engine) |
| Process Node | 4nm |
| Tensor Cores | Gen 4 - transformer-optimized |
| Key Innovation | Transformer Engine, FP8 support, confidential computing |
| Research Impact | Trillion-parameter model research |
| Metric | A100 vs V100 | H100 vs V100 |
|---|---|---|
| Memory Capacity | 2.5x | 2.5x |
| Memory Bandwidth | 2.3x | 3.7x |
| Tensor Compute | 2.5x | 15.8x |
| Research Capability | ~5.7x | ~9.3x |
| Training Efficiency | ~5.7x | ~58.5x |
| V100 (2017) | A100 (2020) | H100 (2022) |
|---|---|---|
| BERT | GPT-3 | GPT-4 class models |
| GPT-1 | PaLM | Multi-modal transformers |
| ResNet at scale | Stable Diffusion | Real-time inference |
The software ecosystem surrounding GPU computing has evolved, creating a complex landscape of tools, frameworks, and libraries. Understanding this ecosystem is crucial for making informed decisions about research infrastructure and development approaches.
\nThe Modern Deep Learning Framework Landscape:
\nThe choice of deep learning framework fundamentally affects research productivity, debugging capabilities, and ultimate performance. Each framework embodies different philosophies about how computational graphs should be constructed, optimized, and executed.
\nPyTorch - The Research Standard:
\nPyTorch’s success in research environments stems from its eager execution model, which means operations are executed immediately as they are encountered in Python code. This design philosophy prioritizes developer experience and debugging ease over execution efficiency.
\nKey Research Advantages:
\nDynamic Computation Graphs: The computational graph is built on-the-fly, enabling easy implementation of dynamic architectures like recursive neural networks, attention mechanisms with variable sequence lengths, and reinforcement learning algorithms where the computation depends on runtime decisions.
\nPythonic Interface: PyTorch feels like native Python, making it intuitive for researchers who are primarily domain experts rather than systems programmers. This reduces the cognitive overhead of implementing complex algorithms.
\nDebugging Experience: Standard Python debugging tools work seamlessly with PyTorch, enabling researchers to set breakpoints, inspect tensor values, and trace execution flow using familiar tools.
\nResearch Ecosystem: The majority of recent research papers provide PyTorch implementations, creating a network effect where researchers can easily build upon previous work.
\nJAX - High-Performance Scientific Computing:
\nJAX represents a different approach, emphasizing functional programming and mathematical composability. It’s designed around the principle that research code should be mathematically clear and amenable to automatic optimization.
\nKey Research Advantages:
\nAutomatic Differentiation: JAX can automatically compute derivatives of arbitrary Python functions, including higher-order derivatives, which is crucial for certain research areas like meta-learning and physics-informed neural networks.
\nTransformation System: JAX provides composable transformations (jit, grad, vmap, pmap) that can be combined to automatically parallelize, vectorize, and optimize research code without manual kernel writing.
\nNumPy Compatibility: JAX provides a drop-in replacement for NumPy, making it easier to accelerate existing scientific computing code.
\nXLA Backend: Leverages Google’s XLA compiler for aggressive optimization, often achieving better performance than PyTorch for research code that fits the functional programming paradigm.
\nTensorFlow - Production and Scale:
\nWhile less popular in pure research settings, TensorFlow remains important for research that needs to scale to production or requires specific ecosystem features.
\nKey Capabilities:
\n| Aspect | PyTorch | JAX | TensorFlow |
|---|---|---|---|
| Execution Model | Eager with dynamic graphs | Functional with transformations | Graph with eager option |
| Research Suitability | Excellent | Excellent | Moderate |
| Debugging | Excellent | Good | Moderate |
| Performance | Good | Excellent | Excellent |
| Learning Curve | Moderate | Steep | Moderate-High |
| Auto-optimization | Limited | Excellent (XLA) | Good |
| Community | Academic research | Scientific computing | Industry/production |
Primary Use Cases:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Framework | Best For |
|---|---|
| PyTorch | Novel architectures, rapid prototyping, CV, NLP, RL, generative models |
| JAX | Scientific ML, physics-informed NNs, Bayesian DL, meta-learning, optimization |
| TensorFlow | Production systems, distributed training, federated learning, mobile/edge AI |
Framework Selection Quick Reference:
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n| Research Area | Recommended Framework |
|---|---|
| Novel Architecture Development | PyTorch |
| High-Performance Scientific Computing | JAX |
| Large-Scale Production Research | TensorFlow |
| Rapid Prototyping | PyTorch |
| Mathematical/Physics-Informed ML | JAX |
| Distributed Training Research | PyTorch or TensorFlow |
| Edge/Mobile AI Research | TensorFlow |
| Optimization Algorithm Development | JAX |
| Computer Vision Research | PyTorch |
| Natural Language Processing | PyTorch |
| Federated Learning | TensorFlow |
| Bayesian Deep Learning | JAX |
Performance-Optimized Libraries - The Hidden Performance Multipliers:
\nBeyond the main frameworks, the choice of supporting libraries can impact research productivity and computational efficiency. Many researchers unknowingly accept performance bottlenecks by using standard libraries when high-performance alternatives exist.
\nThe Performance Library Ecosystem:
\nModern research computing benefits enormously from libraries specifically designed for high-performance workloads. These libraries often provide 5-50x performance improvements over standard Python libraries through techniques like:
\n| Domain | Standard | Optimized | Speedup | Memory Improvement |
|---|---|---|---|---|
| Data Processing | pandas | polars | 5-50x | 2-10x less |
| Numerical Computing | numpy | numba | 10-100x | Near C-level |
| Deep Learning | PyTorch (eager) | JAX + XLA | 2-10x | Better fusion |
| Visualization | matplotlib | bokeh + datashader | 3-20x | Streaming reduces needs |
| Machine Learning | scikit-learn | rapids-cuml | 10-50x | GPU utilization |
Key Technical Innovations:
Research Applications:
When to Use: Datasets > 1GB, complex transformations, memory constraints
\nNumerical Computing: numpy → numbaKey Technical Innovations:
Research Applications:
When to Use: Compute-heavy loops, numerical algorithms, custom kernels needed
\nDeep Learning: PyTorch → JAX + XLAKey Technical Innovations:
Research Applications:
When to Use: Performance-critical training, large models, production research
\nVisualization: matplotlib → bokeh + datashaderKey Technical Innovations:
Research Applications:
When to Use: >1M data points, interactive analysis, web deployment needed
\nMachine Learning: scikit-learn → rapids-cumlKey Technical Innovations:
Research Applications:
When to Use: Traditional ML on large datasets, GPU resources available
\n| Migration | Difficulty | Time | API Compatibility | Tip |
|---|---|---|---|---|
| pandas → polars | Easy | 1-2 hrs | High | Start with .lazy() operations |
| numpy → numba | Moderate | 4-8 hrs | Medium | Add @numba.jit to heavy functions |
| matplotlib → bokeh | Moderate | 6-10 hrs | Low | Start simple, add interactivity |
| scikit-learn → rapids | Easy | 2-4 hrs | High | Ensure CUDA compatibility first |
This comprehensive guide explores the evolution of computing from traditional CPUs to modern GPU-accelerated systems, providing researchers and engineers with essential knowledge for high-performance computing.
\n| Section | Topics |
|---|---|
| Fundamental Concepts | Hardware-software duality, CPU architecture, parallel computing paradigm shift |
| GPU Architecture | SIMD vs SIMT, thread hierarchy, memory architecture |
| Performance Analysis | Arithmetic intensity, memory-bound vs compute-bound kernels, A100 modeling |
| Optimization Strategies | Operator fusion, tiling techniques, hierarchical optimization |
| Research Hardware | V100 → A100 → H100 evolution, HPC infrastructure, MIG |
| Software Ecosystem | PyTorch/JAX/TensorFlow comparison, performance libraries, migration strategies |
This guide enables researchers to make informed decisions about hardware selection, software frameworks, and optimization strategies. Understanding these concepts is crucial for maximizing computational efficiency in modern research workflows, from small-scale experimentation to large-scale distributed training.
\nResearchers, graduate students, and engineers in computational science, machine learning, and high-performance computing who need to understand and optimize GPU-accelerated workflows.
", "url": "https://blog.ecitis.org/understanding-gpus/", "title": "Understanding GPUs and Parallel Computing", "summary": "Build a mental model of GPU architecture, memory, kernels, and parallel execution for modern machine-learning workloads.", "image": "https://blog.ecitis.org/open-graph/understanding-gpus.png", "date_modified": "2025-09-19T00:00:00.000Z", "date_published": "2025-09-19T00:00:00.000Z", "author": { "name": "Aadit Agrawal", "url": "https://blog.ecitis.org/" }, "tags": [ "Hardware & Systems", "GPU", "CUDA", "Parallel computing" ] }, { "id": "https://blog.ecitis.org/generative-ai-guide/", "content_html": "Modern generative AI moves quickly. Don’t lock yourself into defaults like “BERT + FAISS + all-MiniLM” just because a quick tutorial said so. Learn the landscape, then pick the right tools for your use case. This guide covers Hugging Face (models, datasets, formats), local and server runtimes (llama.cpp, Ollama, vLLM), and multi-provider access via OpenRouter. It also includes practical patterns for building solid projects.
\n![\"Generative](\"https://blog.ecitis.org/feeds/figures/generative-ai-guide-0.webp\")
Hugging Face is a community hub for models, datasets, and apps (Spaces). You’ll use it to:
\nTypical repository contents for Transformer LLMs:
\nconfig.json (architecture and hyperparameters)tokenizer.json or tokenizer.model (+ vocab files).safetensors (preferred) or legacy .bingeneration_config.json (sampling defaults)You’ll find families like Llama, Mistral, Qwen, Phi, Gemma, OpenMistral, etc., in multiple sizes and instruction variants. Read model cards for:
\nUse the datasets library for large and streaming loads:
from datasets import load_dataset\n\n# Stream JSONL shards directly from the Hub\nds = load_dataset(\"my-org/my-dataset\", split=\"train\", streaming=True)\nfor row in ds.take(3):\n print(row)\n\n# Local JSONL\nds_local = load_dataset(\"json\", data_files={\"train\": \"data.jsonl\"})Datasets support map/filter/shuffle, memory-mapped Arrow, and push/pull for collaboration. Prefer canonical public datasets for benchmarking when possible.
\n.safetensors (zero-copy, safe); the default for Transformersllama.cpp and OllamaUse format-native runtimes when you want portability (GGUF), maximum throughput (TensorRT-LLM), or server features (vLLM).
\nBest for lightweight local inference and experimentation; strong CPU quantization support and GPU offload.
\nllama.cpp repo):# Example flow (exact script names vary by model family)\npython llama.cpp/convert.py --model /path/to/hf-model --out model.gguf --dtype q4_k_m./main -m model.gguf -p \"Explain transformers in 3 bullet points\" -n 256 --temp 0.7Tips:
\nOllama wraps GGUF models with a simple CLI and local REST API.
\n# Install from docs, then:\nollama pull llama3.1\nollama run llama3.1Custom Modelfile:
FROM llama3.1\nPARAMETER temperature 0.7\nSYSTEM You are a helpful, terse assistant.Then:
\nollama create my-assistant -f Modelfile\nollama run my-assistantUse the local HTTP API for apps. Good for prototypes and offline demos.
\nvLLM is a high-throughput LLM server with PagedAttention and continuous batching. It serves HF models via an OpenAI-compatible API.
\nRun a model:
\npip install vllm\npython -m vllm.entrypoints.openai.api_server \\\n --model meta-llama/Meta-Llama-3.1-8B-Instruct \\\n --max-model-len 32768 \\\n --tensor-parallel-size 1Client (OpenAI SDK-style):
\nfrom openai import OpenAI\n\nclient = OpenAI(base_url=\"http://localhost:8000/v1\", api_key=\"sk-no-key\")\nresp = client.chat.completions.create(\n model=\"meta-llama/Meta-Llama-3.1-8B-Instruct\",\n messages=[{\"role\": \"user\", \"content\": \"Write a haiku about GPUs.\"}],\n)\nprint(resp.choices[0].message.content)Notes:
\n--gpu-memory-utilization, --max-model-len, and tensor parallel degree to hardware.OpenRouter aggregates frontier and open models behind a single, OpenAI-compatible API. You pick the model; they route to providers (price/perf vary by model).
\nSetup:
\nbase_url and your key.from openai import OpenAI\nimport os\n\nclient = OpenAI(\n base_url=\"https://openrouter.ai/api/v1\",\n api_key=os.environ[\"OPENROUTER_API_KEY\"],\n)\n\nresp = client.chat.completions.create(\n model=\"anthropic/claude-3.5-sonnet\",\n messages=[{\"role\": \"user\", \"content\": \"Compare Llama 3.1 and Qwen 2.\"}],\n)\nprint(resp.choices[0].message.content)Why use it:
\nInstead of always picking all-MiniLM + FAISS:
bge-base(-en)-v1.5, gte-*, e5-*, voyage-* (paid), domain-specific encoders. Use public evals (MTEB) and your own retrieval tests.Minimal retrieval sketch (HF embeddings + Qdrant):
\nfrom sentence_transformers import SentenceTransformer\nfrom qdrant_client import QdrantClient\nfrom qdrant_client.models import Distance, VectorParams, PointStruct\n\nmodel = SentenceTransformer(\"sentence-transformers/all-MiniLM-L6-v2\") # swap for stronger embeddings\nclient = QdrantClient(host=\"localhost\", port=6333)\n\nclient.recreate_collection(\n collection_name=\"docs\",\n vectors_config=VectorParams(size=384, distance=Distance.COSINE),\n)\n\ntexts = [\"Doc A...\", \"Doc B...\"]\nvecs = model.encode(texts, normalize_embeddings=True)\nclient.upsert(\"docs\", [PointStruct(id=i, vector=vecs[i], payload={\"text\": t}) for i, t in enumerate(texts)])\n\nquery = \"What is in Doc B?\"\nqvec = model.encode([query], normalize_embeddings=True)[0]\nhits = client.search(\"docs\", query_vector=qvec, limit=3)Swap the encoder, add reranking, and evaluate retrieval quality. Don’t assume defaults are best.
\nOllama (GGUF) or llama.cpp; low setup, great UX.vLLM; high throughput, OpenAI-compatible API for apps.OpenRouter; fast model switching/comparison across providers.TensorRT-LLM, Hugging Face TGI, or vendor-specific services for maximum perf.ollama pull mistral\nollama run mistralpython -m vllm.entrypoints.openai.api_server --model meta-llama/Meta-Llama-3.1-8B-Instructfrom openai import OpenAI\nclient = OpenAI(base_url=\"http://localhost:8000/v1\", api_key=\"sk-no-key\")\nprint(client.chat.completions.create(model=\"meta-llama/Meta-Llama-3.1-8B-Instruct\", messages=[{\"role\": \"user\", \"content\": \"Say hi\"}]).choices[0].message.content)from openai import OpenAI\nimport os\nclient = OpenAI(base_url=\"https://openrouter.ai/api/v1\", api_key=os.environ[\"OPENROUTER_API_KEY\"])\nprint(client.chat.completions.create(model=\"openai/gpt-4o\", messages=[{\"role\": \"user\", \"content\": \"Give 3 project ideas with data sources.\"}]).choices[0].message.content)This guide shows how to use Astral’s uv for fast, reproducible Python environments on HPC systems, install PyTorch with CUDA for NVIDIA A100 GPUs, tune performance (data loading, AMP/TF32, memory format, compile, CUDA Graphs, DDP), and monitor with nvidia-smi, nvtop, and NVIDIA Nsight tools.
![\"HPC](\"https://blog.ecitis.org/feeds/figures/hpc-guide-0.webp\")
Links you’ll use often:
\nuv is a fast package/project manager and Python launcher. It replaces pip, virtualenv, some poetry tasks, and even manages Python interpreters.
On Linux/macOS:
\ncurl -LsSf https://astral.sh/uv/install.sh | sh\nuv --versionOn Windows (PowerShell):
\npowershell -ExecutionPolicy ByPass -c \"irm https://astral.sh/uv/install.ps1 | iex\"\nuv --versionIf your cluster forbids curl-based installers, you can fall back to:
\npip install --user uv\n~/.local/bin/uv --versionKeep project-specific Python consistent to avoid ABI mismatches with CUDA.
\nuv python listuv python install 3.11 3.12.python-version):uv python pin 3.11When running on shared clusters, ensure your job loads the same Python (via pinning) on login nodes and compute nodes.
\nRecommended: put a .venv/ in the project root and commit .venv/ to .gitignore.
uv venv --python 3.11source .venv/bin/activate.venv\\Scripts\\Activateuv pip install -U pip setuptools wheelpyproject.toml yet:uv pip freeze > requirements.txtTip: uv can also manage project deps via pyproject.toml + uv.lock with uv add and uv sync if you prefer lockfiles.
nvidia-smi\nnvidia-smi topo -m # NUMA / PCIe fabric viewCheck the “CUDA Version” reported by nvidia-smi (this reflects the driver-supported CUDA runtime). On many A100 systems you’ll see CUDA 11.8 or 12.1+.
# CUDA 11.8\nuv pip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/cu118\n\n# CUDA 12.1\nuv pip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/cu121If your cluster uses modules, load them first (example):
\nmodule load cuda/12.1 # or the site-provided module that matches your driversimport torch\nprint(torch.__version__)\nprint(torch.version.cuda)\nprint(torch.cuda.is_available())\nprint(torch.cuda.get_device_name(0))If is_available() is False, check that you’re on a GPU node, the right module is loaded, and your PyTorch wheels match the available CUDA runtime.
The A100 is very fast; most training slowdowns are input-bound. Key DataLoader knobs:
num_workers: parallel CPU workers. Start near the number of physical cores per GPU slice, then sweep.pin_memory=True: enables page-locked host buffers for faster H2D copies.persistent_workers=True: avoid worker teardown cost between epochs (when num_workers>0).prefetch_factor: number of batches preloaded by each worker (default 2). Increase if GPU starves..to(device, non_blocking=True).Example:
\nimport os\nfrom torch.utils.data import DataLoader\n\nnum_cpu = os.cpu_count() or 8\nloader = DataLoader(\n dataset,\n batch_size=64,\n shuffle=True,\n num_workers=min(8, num_cpu),\n pin_memory=True,\n persistent_workers=True,\n prefetch_factor=4,\n)Watch GPU-Util vs CPU load. If GPU < 90% while CPUs are busy, increase prefetch_factor/num_workers. If CPUs are idle and GPU is low-util, you may be I/O bound (optimize storage, caching, or preprocessing).
torch.cuda.amp for FP16/BF16 where safe.Minimal training loop sketch:
\nimport torch\nfrom torch.cuda.amp import autocast, GradScaler\n\ndevice = torch.device('cuda')\nmodel = model.to(device)\nmodel = model.to(memory_format=torch.channels_last)\n\n# Enable cudnn autotuner (best algos per input shapes)\ntorch.backends.cudnn.benchmark = True\n\n# Prefer higher TF32 throughput where numerically OK\ntorch.backends.cuda.matmul.allow_tf32 = True\ntorch.backends.cudnn.allow_tf32 = True\n\nscaler = GradScaler() # use torch.amp.GradScaler for BF16 on newer PyTorch\n\nfor images, targets in loader:\n images = images.to(device, non_blocking=True)\n images = images.to(memory_format=torch.channels_last)\n targets = targets.to(device, non_blocking=True)\n\n optimizer.zero_grad(set_to_none=True)\n with autocast():\n outputs = model(images)\n loss = criterion(outputs, targets)\n scaler.scale(loss).backward()\n scaler.step(optimizer)\n scaler.update()Notes:
\ncudnn.benchmark benefit.torch.compile (PyTorch 2.x) can fuse kernels and reduce Python overhead. Try safe modes first:compiled_model = torch.compile(model, mode='max-autotune')import torch\n\nstatic_inp = torch.empty_like(example_inp, device='cuda')\ng = torch.cuda.CUDAGraph()\n\n# warm-up allocations\n_ = model(example_inp)\n\noptimizer.zero_grad(set_to_none=True)\nwith torch.cuda.graph(g):\n out = model(static_inp)\n loss = criterion(out, static_target)\n loss.backward()\n optimizer.step()\n\nfor inp, tgt in loader:\n static_inp.copy_(inp.to('cuda', non_blocking=True))\n static_target.copy_(tgt.to('cuda', non_blocking=True))\n g.replay()Both features benefit stable shapes and control flow; avoid random control paths inside the captured region.
\nUse Distributed Data Parallel (NCCL) to scale across A100s.
\nLauncher (single node, 8 GPUs):
\ntorchrun --standalone --nproc_per_node=8 train.py --arg1 ...Inside train.py:
import os, torch, torch.distributed as dist\nfrom torch.nn.parallel import DistributedDataParallel as DDP\n\ndist.init_process_group('nccl')\nrank = dist.get_rank()\ntorch.cuda.set_device(rank % torch.cuda.device_count())\ndevice = torch.device('cuda', rank % torch.cuda.device_count())\n\nmodel = model.to(device)\nmodel = DDP(model, device_ids=[device.index])Use DistributedSampler for datasets and call sampler.set_epoch(epoch) each epoch.
--cpus-per-task to match num_workers and set threads:import os, torch\ntorch.set_num_threads(int(os.environ.get('SLURM_CPUS_PER_TASK', '4')))\ntorch.set_num_interop_threads(1)nvidia-smi # snapshot\nwatch -n 1 nvidia-smi # live refresh\nnvidia-smi dmon -s pucm # per-GPU perf counters (Power/Util/Clock/Memory)\nnvidia-smi topo -m # topology (NVLink/PCIe/NUMA)How to read:
\nsudo apt-get install nvtop # Debian/Ubuntu\nnvtopShows per-process SM/memory utilization and graphs. Useful to identify which PID is starving or leaking memory.
\nfrom torch.profiler import profile, record_function, ProfilerActivity\n\nwith profile(\n activities=[ProfilerActivity.CPU, ProfilerActivity.CUDA],\n record_shapes=True,\n profile_memory=True,\n with_stack=True,\n) as prof:\n for step, (x, y) in enumerate(loader):\n if step == 100: break\n with record_function('train_step'):\n x = x.to('cuda', non_blocking=True)\n y = y.to('cuda', non_blocking=True)\n out = model(x)\n loss = criterion(out, y)\n loss.backward()\n optimizer.step(); optimizer.zero_grad(set_to_none=True)\n\nprint(prof.key_averages().table(sort_by='cuda_time_total', row_limit=15))\nprof.export_chrome_trace('trace.json')Open trace.json in Chrome’s tracing viewer or TensorBoard’s profiler plugin for timelines.
nsys profile -o profile_report python train.pyUse the GUI to inspect kernel launches, H2D/D2H copies, CPU stalls, and NCCL collectives.
\nncu --set full --target-processes all python train.pyDrill into specific kernels to see occupancy, memory throughput, and bottlenecks.
\ncu118/cu121) must be compatible with your driver’s CUDA runtime. Reinstall with the right --index-url.num_workers, prefetch_factor, enable pin_memory, move preprocessing to workers.nvidia-smi topo -m for NVLink/PCIe topology, ensure NCCL is the backend, and avoid CPU oversubscription.# 0) (If needed) load site modules\nmodule load cuda/12.1 # as required by your cluster\n\n# 1) Install uv and create project venv\ncurl -LsSf https://astral.sh/uv/install.sh | sh\nuv python install 3.11\nuv python pin 3.11\nuv venv --python 3.11\nsource .venv/bin/activate\n\n# 2) Install PyTorch CUDA wheels\nuv pip install torch torchvision torchaudio --index-url https://download.pytorch.org/whl/cu121\n\n# 3) Sanity check\npython - <<'PY'\nimport torch\nprint('Torch:', torch.__version__, 'CUDA:', torch.version.cuda)\nprint('GPU available:', torch.cuda.is_available())\nprint('Device:', torch.cuda.get_device_name(0))\nPYThen apply the loader/AMP/TF32/compile practices above and watch nvidia-smi/nvtop for sustained high utilization.